46 results on '"Ferreira, Pietro M."'
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2. Neuromorphic analog spiking-modulator for audio signal processing
3. Revisiting the Ultra-Low Power Electronic Neuron Towards a Faithful Biomimetic Behavior
4. Jitter Noise Impact on Analog Spiking Neural Networks: STDP Limitations
5. A Tunable Morris-Lecar Spiking Neuron in CMOS
6. Design considerations of CMOS active inductor for low power applications
7. Physics Informed Spiking Neural Networks: Application to Digital Predistortion for Power Amplifier Linearization
8. Dual-band Transmitter Linearization using Spiking Neural Networks
9. Analysis of an Inverter-Based CMOS Envelope Detector
10. Sub-nJ per Decision Schmitt Trigger Comparator for Neuromorphic Spike Detection in 55 nm Technology
11. Smart IoT - Implementation of Neuromorphic Circuits
12. Deep Neural Network Feasibility Using Analog Spiking Neurons
13. 1.2 nW Neuromorphic Enhanced Wake-Up Radio
14. Analysis and Implementation of OVSF Address Decoders
15. Analog Spiking Neural Network Synthesis for the MNIST.
16. Reliability Aware AMS/RF Performance Optimization
17. Current mode read-out circuit for InGaAs photodiode applications
18. A 237 ppm/°C L-Band Active Inductance Based Voltage Controlled Oscillator in SOI 0.18 µm
19. A Flexible Low-Cost Discrete-Time Wake-up Receiver for LoRaWAN applications
20. A 0.35 μm CMOS AM demodulator
21. A comparative study between E‐neurons mathematical model and circuit model
22. Neuromorphic analog spiking-modulator for audio signal processing
23. A Chopper Stabilization Audio Instrumentation Amplifier for IoT Applications
24. A Sub-pJ/Bit, Low-ER Mach–Zehnder-Based Transmitter for Chip-to-Chip Optical Interconnects
25. A Chopper Negative-R Delta-Sigma ADC for Audio MEMS Sensors.
26. A General gm/ID Temperature-Aware Design Methodology Using 180 nm CMOS up to 250 ◦C.
27. Surface versus Performance Trade-offs: A Review of Layout Techniques.
28. A Compact Active Phaser with Enhanced Group Delay Linearity for Analog Signal Processing
29. An Adaptative Ratio-Metric Analog-To-Digital Interface For Weakly-Coupled Resonant Sensors Based On Mutually Injection-Locked Oscillators
30. Process-Voltage-Temperature Analysis of a CMOS-MEMS Readout Architecture
31. Implications of Small Geometry Effects on$g_m/I_D$Based Design Methodology for Analog Circuits
32. Energy efficient fJ/spike LTS e-Neuron using 55-nm node
33. A CMOS Envelope Detector for Low Power Wireless Receiver Applications
34. Design considerations of CMOS active inductor for low power applications
35. Design considerations of a CMOS envelope detector for low power wireless receiver applications
36. Implications of Small Geometry Effects on $g_m/I_D$ Based Design Methodology for Analog Circuits.
37. 1-20 GHz k Omega-range BiCMOS 55 nm Reflectometer
38. A Unified Explanation of gm/ID-Based Noise Analysis
39. A$g_{m}/I_{D}$-Based Noise Optimization for CMOS Folded-Cascode Operational Amplifier
40. 1–20 Ghz kΩ-range BiCMOS 55 nm reflectometer
41. Experimental Demonstration of <i>g<sub>m</sub></i>/I<i><sub>D</sub></i> Based Noise Analysis
42. Transconductance/drain current based sensitivity analysis for analog CMOS integrated circuits
43. A new synthesis methodology for reliable RF front-end Design
44. AMS and RF design for reliability methodology
45. A Unified Explanation of gm/ID-Based Noise Analysis.
46. A gm/ID-Based Noise Optimization for CMOS Folded-Cascode Operational Amplifier.
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