Search

Due to rapid growth in the integrated circuit (IC) industry, the demand for compact digital system design is high. However, the continued technology reductions made the feasibility of further scaling down transistor size more challenging. In response to the growing demand for ultra-compact IC designs, the revolutionary quantum-dot cellular automata (QCA) technology has emerged as a promising solution. In a digital era, the counters are widely adopted in the peer-to-peer process flow to establish a mechanism for generating unique values for each identifier/number. In this work, a unique synchronous and asynchronous counters architecture is proposed with a reliable D and T flip-flop design. The proposed QCA architecture is implemented and validated with the QCA designer tool. Furthermore, in QCA technology, unreliable QCA designs can lead to frequent errors and malfunctions in the implemented logic. To overcome this challenge, the proposed design prioritizes cell placement (the relative positions of QCA cells) to make the circuit more robust. As a result, the circuit can still produce the expected functionality even if some QCA cells malfunction. Hence, to ensure the reliability of the proposed QCA architecture, the missing cell defect analysis is carried out in comparison with existing state-of-the-art designs. Based on comparison results, the unique designs like the proposed multiplexer, D flip-flop and T flip-flop design exhibit success rates of 67.28, 77.04 and 85.15%, respectively. The experimental results demonstrate that the proposed counter-architecture outperforms existing architectures. [ABSTRACT FROM AUTHOR]

We report a detailed spectro-temporal analysis of the black hole low mass X-ray binary 4U 1543−475 during its 2021 outburst using the data from the Large Area X-ray Proportional Counter and the Soft X-ray Telescope instruments on board AstroSat. We studied the energy and frequency dependency of the source variability to probe the origin of the disc/coronal fluctuations. Following the state transition (from soft to intermediate state), the emergence of a band-limited noise component is observed along with the power law noise when the disk is recovering from a sudden decrease in the inner disk radius. A possible correlation between the low-frequency root mean square (RMS) variability amplitude and the covering fraction of the non-thermal component is detected. During the final AstroSat observation, a flip-flop phenomenon is reported, where rapid variation in RMS occurs in concurrence with sudden flux transition. An indication of the evolution of inner disk temperature along with a significant change in thermal flux was observed during the flip-flop phase, arguing for a disk instability-driven origin for this phenomenon. Our results suggest that the long-term variability evolution is primarily affected by the coronal changes, whereas the disk behavior governs the short-term variability evolution. [ABSTRACT FROM AUTHOR]

Host restriction factor SERINC5 (SER5) incorporates into the HIV-1 membrane and inhibits infectivity by a poorly understood mechanism. Recently, SER5 was found to exhibit scramblase-like activity leading to the externalization of phosphatidylserine (PS) on the viral surface, which has been proposed to be responsible for SER5's antiviral activity. This and other reports that document modulation of HIV-1 infectivity by viral lipid composition prompted us to investigate the role of PS in regulating SER5-mediated HIV-1 restriction. First, we show that the level of SER5 incorporation into virions correlates with an increase in PS levels in the outer leaflet of the viral membrane. We developed an assay to estimate the PS distribution across the viral membrane and found that SER5, but not SER2, which lacks antiviral activity, abrogates PS asymmetry by externalizing this lipid. Second, SER5 incorporation diminished the infectivity of pseudoviruses produced from cells lacking a flippase subunit CDC50a and, therefore, exhibited a higher baseline level of surface-accessible PS. Finally, exogenous manipulation of the viral PS levels utilizing methyl-alpha-cyclodextrin revealed a lack of correlation between external PS and virion infectivity. Taken together, our study implies that the increased PS exposure to SER5-containing virions itself is not directly linked to HIV-1 restriction. [ABSTRACT FROM AUTHOR]

The need for a low-power and high-speed technology for computation of digital signals is rising due to the fast growth of technological innovations. Flip-flops serve as fundamental elements in signal processing technologies. Hybrid logic has great potential for constructing flip-flop circuits because of its minimal transistor count as well as low-power properties.The present investigation presents a design for a tiny and low-power hybrid flip-flop that operates fully statically. The design has been developed by utilizing different circuitry-reduction techniques. It incorporates a hybrid logic approach combining pass transistor logic to decrease circuit complexity. The ongoing work utilizes a hybrid logic with low delay and low power to generate flip-flops. The proposed flip-flop design significantly decreases latency compared to the existing master-slave flip-flops. This flip-flop remains immune to clock overloading, resulting in reduced power consumption. Reducing the quantity of PFET (P-channel Field Effect Transistor) transistors enhances the circuit's delay, area, and power consumption. Implementing these circuit optimization techniques yields several benefits, such as reduced CLOCK-to-OUT and DIN-to-OUT node delays, decreased average power consumption, lower leakage power, and a transistor count of only 18. The results were achieved using Cadence Virtuoso at 18 nm finFET technology, with varied process corners, supply voltages ranging from 0.7 V to 1 V, and temperatures ranging from -50 °C to 75 °C. This study also presents a Monte Carlo simulation of power consumption, leakage, and delay for the suggested flip-flop. According to the simulations, the recommended flip-flop exhibits exceptional stability. The recommended flip-flop has lower power usage by at least 17.95 % compared to standard architectures due to the lower number of PFET transistors.

The scaling limitations of Complementary Metal-Oxide-Semiconductor (CMOS) transistors to achieve better performance have led to the attention of other structures to improve circuit performance. One of these structures is multi-valued circuits. In this paper, we will first study Carbon Nanotube Transistors (CNT). CNT transistors offer a viable means to implement multi-valued logic due to their variable and controllable threshold voltage. Subsequently, we delve into the realm of three-valued flip-flop circuits, which find extensive utility in digital electronics. Leveraging the insights gained from our analysis, we propose a novel D-type flip-flop structure. The presented structure boasts a remarkably low power consumption, showcasing a reduction exceeding 61% compared to other existing structures. Furthermore, the proposed circuit incorporates a reduced number of transistors, resulting in a reduced footprint. Importantly, this circuit exhibits negligible static power consumption in generating intermediate values, rendering it robust against process variations. Overall, the proposed circuits demonstrate a 29.7% increase in delay compared to the compared structures. However, they showcase a 96.1% reduction in power-delay product (PDP) compared to the other structures. The number of transistors is also 8.3% less than other structures. Additionally, their figure of merits (FOM) are 19.7% better than the best-compared circuit, underscoring its advantages in power efficiency, chip area, and performance.

Dual modulus pre-scalers (DMPS) are programmable counters used in phase-locked loops (PLL). The dual modulus division capability improves the circuit functionality and can be used as a divider of N/N + 1 cycles, which can be controlled through a master input. This paper proposes power and area efficient divide-by-16/17 DMPS designs, which incorporate true single-phase clocking (TSPC) based D flip-flops, which consume less power with minimal area. Power reduction is achieved by integrating adaptive voltage level-source (AVLS) circuit to DMPS. The proposed-I divide-by-16/17 DMPS has been implemented by using TSPC based D flip-flops incorporating the AVLS technique. The proposed DMPS consumes 146.6 µW (34%) less power when compared to the reference architecture, in divide-by-16 mode. Further optimization of the pre-scaler design is done by using a minimum number of transistors, involving pushing the logic (AND) into the first stage of TSPC based D flip-flops which results in an area as well as power efficient design. The proposed-II circuit is realized by using optimized TSPC based D flip-flops, along with incorporation of the AVLS technique, resulting in a power efficient design. For instance, in divide-by-16 mode of operation, a 100 µW (21%) reduction in the total power is observed when a DMPS circuit is realized in CMOS 180 nm technology. Also, when the proposed DMPSs are realized in CMOS 45 nm technology, the same trend of power reduction is observed, which are analyzed at an operating frequency of 1 GHz. The circuits are realized in Cadence Virtuoso and simulated in Spectre. [ABSTRACT FROM AUTHOR]

The scaling limitations of Complementary Metal-Oxide-Semiconductor (CMOS) transistors to achieve better performance have led to the attention of other structures to improve circuit performance. One of these structures is multi-valued circuits. In this paper, we will first study Carbon Nanotube Transistors (CNT). CNT transistors offer a viable means to implement multi-valued logic due to their variable and controllable threshold voltage. Subsequently, we delve into the realm of three-valued flip-flop circuits, which find extensive utility in digital electronics. Leveraging the insights gained from our analysis, we propose a novel D-type flip-flop structure. The presented structure boasts a remarkably low power consumption, showcasing a reduction exceeding 61% compared to other existing structures. Furthermore, the proposed circuit incorporates a reduced number of transistors, resulting in a reduced footprint. Importantly, this circuit exhibits negligible static power consumption in generating intermediate values, rendering it robust against process variations. Overall, the proposed circuits demonstrate a 29.7% increase in delay compared to the compared structures. However, they showcase a 96.1% reduction in power-delay product (PDP) compared to the other structures. The number of transistors is also 8.3% less than other structures. Additionally, their figure of merits (FOM) are 19.7% better than the best-compared circuit, underscoring its advantages in power efficiency, chip area, and performance. [ABSTRACT FROM AUTHOR]

Sequential decision-making tasks that require information integration over extended durations of time are challenging for several reasons, including the problem of vanishing gradients, long training times and significant memory requirements. To this end, we propose a neuron model fashioned after the JK flip-flops in digital systems. A flip-flop is a sequential device that can store state information of the previous history. We incorporate the JK flip-flop neuron into several deep network architectures and apply the networks to difficult sequence processing problems. The proposed architectures include flip-flop neural networks (FFNNs), bidirectional flip-flop neural networks (BiFFNNs), convolutional flip-flop neural networks (ConvFFNNs), and bidirectional convolutional flip-flop neural networks (BiConvFFNNs). Learning rules of proposed architectures have also been derived. We have considered the most popular benchmark sequential tasks like signal generation, sentiment analysis, handwriting generation, text generation, video frame prediction, lung volume prediction, and action recognition to evaluate the proposed networks. Finally, we compare the results of our networks with the results from analogous networks with Long Short-Term Memory (LSTM) neurons on the same sequential tasks. Our results show that the JK flip-flop networks outperform the LSTM networks significantly or marginally on all the tasks, with only half of the trainable parameters. [ABSTRACT FROM AUTHOR]

Objectives: To test the association of 45 single nucleotide polymorphisms (SNPs) with transition to psychiatric disorders in a cohort of individuals at ultrahigh risk (UHR) mental state for psychosis. Methods: Through general population screening, 88 non-help-seeking UHR subjects and 130 healthy control individuals were genotyped for 45 SNPs related to psychosis. They were followed for a mean of 2.5 years, and conversion to psychotic and to general psychiatric disorders was assessed. Genotype frequencies between controls, converters, and non-converters were analyzed. Results: There were no differences in sociodemographics between controls and UHR. Also, UHR converters and non-converters had no differences in their baseline symptoms scores. The dopamine receptor D2 gene (DRD2) SNP rs6277 was significantly more common among UHR who transitioned to psychosis (p < 0.001) and to UHR who transitioned to any psychiatric disorders (p = 0.001) when compared to UHR who did not transition. The rs6277 T allele was related to psychiatric morbidity in a dose-response fashion, being significantly more frequent in UHR converters than UHR non-converters and control subjects (p = 0.003). Conclusion: Our findings suggest that rs6277 could potentially constitute a genetic marker of transition to psychiatric disorders in subjects with at-risk mental states, warranting further investigation in larger samples.

Host restriction factor SERINC5 (SER5) incorporates into the HIV-1 membrane and inhibits infectivity by a poorly understood mechanism. Recently, SER5 was found to exhibit scramblase-like activity leading to the externalization of phosphatidylserine (PS) on the viral surface, which has been proposed to be responsible for SER5’s antiviral activity. This and other reports that document modulation of HIV-1 infectivity by viral lipid composition prompted us to investigate the role of PS in regulating SER5-mediated HIV-1 restriction. First, we show that the level of SER5 incorporation into virions correlates with an increase in PS levels in the outer leaflet of the viral membrane. We developed an assay to estimate the PS distribution across the viral membrane and found that SER5, but not SER2, which lacks antiviral activity, abrogates PS asymmetry by externalizing this lipid. Second, SER5 incorporation diminished the infectivity of pseudoviruses produced from cells lacking a flippase subunit CDC50a and, therefore, exhibited a higher baseline level of surface-accessible PS. Finally, exogenous manipulation of the viral PS levels utilizing methyl-alpha-cyclodextrin revealed a lack of correlation between external PS and virion infectivity. Taken together, our study implies that the increased PS exposure to SER5-containing virions itself is not directly linked to HIV-1 restriction.

Objectives: Pain, fever and inflammation associated with protozoan infections caused by Trypanosomes, Babesia, Entamoeba, Leishmania and Pneumocystis have necessitated the search for polypharmacy,that could be used for treatment of protozoan infections in dogs. Methods: Randomized cross-over controlled trial was adopted for kinetic study of piroxicam (3.5 mg/kg) and piroxicam (3.5 mg/kg) administered with diminazene aceturate (3.5 mg/kg) in Nigerian indigenous dogs. Ten dogs comprised 5 males and females, each of about 8 ± 2 months and weighed 10 ± 0.5 kg were administered piroxicam, after one month the dogs were administered piroxicam and diminazene aceturate at different thigh muscles. Single dose was administered to avoid toxicity. Blood samples were collected at 0, 0.08, 0.25, 0.5, 1.0, 1.5, 2.0, 3.0, 4.0, 6.0, 8.0, 10, 12, 24, 48, 72 and 96 h for plasma analysis of piroxicam. Results: Findings have shown that piroxicam was significantly (p

Power consumption plays a significant role in any integrated circuit. In this study, an explicit type pulse trigger flip-flop is implemented using the CMOS 90 nm technology. For low-power dissipation, 1 V supply will optimize the size of gate terminal. This explicit type flip-flop uses an explicit source for pulse generation, that is, the double edge-triggered pulse generator, which requires half of clock frequency compared to the single edge-triggered pulse generator. The proposed new double edge-triggered pulse generator uses the pulse generation logic, which is used to share many numbers of flip-flop results at low power. In this article, circuits with low power, low heat generation, and increased durability are achieved. [ABSTRACT FROM AUTHOR]

Political leaders may change their mind about a policy, or even a significant moral issue. While genuinely changing one's mind is not hypocritical, there are reasons to think that leaders who claim such a change are merely hypocritically pandering for political advantage. Indeed, some social science studies allegedly confirm that constituents will judge political leaders who change positions as hypocritical. Yet these studies are missing crucial details that we normally use to distinguish genuine mind changers from hollow hypocrites. These details suggest ways in which political leaders can communicate that their mind change is genuine without necessarily being judged hypocritical. [ABSTRACT FROM AUTHOR]

The exciting properties of multi-valued logic (MVL) in overcoming the limitations of binary systems have led to widespread research on this topic. Considering various types of MVL, quaternary logic is more compatible with the existing binary systems. This paper proposes a nonvolatile quaternary flip-flop (NQFF) based on the unique features of the carbon nanotube field-effect transistors (CNTFETs) and magnetic tunnel junctions (MTJs). The proposed NQFF utilizes Spin-Hall effect (SHE)-assisted spin-transfer torque (STT) MTJs to provide nonvolatility with lower write energy, and multi-Vt gate-all-around (GAA) CNTFETs offer higher performance. On the other side, due to the usage of a shadow latch and the design of the proposed circuit, the delay of MTJ switching does not affect the delay of the whole circuit. The simulation results show that the proposed NQFF offers 50% lower PDP when the system is idle for only 25% of its total operational time. [ABSTRACT FROM AUTHOR]

Conventional high-performance flip-flops suffer from large power consumption at the nominal supply region and unreliable operation in the low-voltage region. To overcome these drawbacks, this paper proposes conditional-bridging flip-flops (CBFFs) that can conditionally activate the shorting device in the sense-amplifier stage. There are two versions of the proposed flip-flop. The single-ended version (CBFF-S) adopts a single-ended latching stage to optimize in terms of power consumption and area. For applications requiring high speed with differential outputs, the speed-optimized differential version (CBFF-D) is also proposed. Since the shorting device is adaptively turned on only when it is necessary, the flip-flops have fully static operations with reduced switching power consumption. The conditional bridging technique can also help minimize the effective parasitic capacitance relevant to the shorting device by relieving the design burden of weakening the device, resulting in further power reduction. The technique also provides the complete separation of complementary precharge nodes in the sense-amplifier stage during input sampling, achieving a fast and reliable operation. To further reduce power consumption and latency, the latching stage is designed to have no glitches and signal fighting and to be driven by the first stage output without signal inversion. Moreover, the conditionally bridged sense-amplifier stage having a reliable pull-down of precharge nodes and the latching stage having a contention-free operation allow the flip-flops to provide stable operation down to the near-threshold voltage (NTV) region. The proposed flip-flops were designed in a 28-nm CMOS process, whose performance evaluation results indicated that the power consumption of CBFF-S is reduced by up to 56.2% compared to conventional single-ended flip-flops at 0.1 switching activity. The minimum DQ latency was also reduced by up to 33.6%. They also indicated that CBFF-D offers up to 33.8% less power at 0.1 switching activity and up to 24.1% lower minimum DQ latency than those of conventional differential flip-flops. The resulting power-delay product (PDP) of CBFFs was at least 27.8% less than those of conventional flip-flops. The Monte-Carlo simulation results considering the process, voltage, and temperature (PVT) variations indicated that CBFFs could operate reliably down to a supply voltage of 0.3 V.

In this paper, a graphene-based plasmonic D flip-flop with the ability to remain in the states has been designed. A graphene layer is sandwiched between two SnO2 layers for guiding the surface plasmon polaritons. The structure consists of three input ports D, CLK, and Bias, and two output ports Q and Q′ where output Q is connected to input D through a waveguide, and output Q′ is activated via interference among the inputs D, CLK, and Bias. The proposed structure is based on wave dividing and interfering, and works at a wavelength of 13.8 µm. In comparison to the previous works, the flip-flop remains its previous state by using the Bias signal when CLK becomes inactive. The finite difference time domain method has been used to simulate the proposed structure. The area of the subwavelength structure is as small as 1.62 µm2, and the contrast ratio for Q and Q′ is equal to 5.9 dB and 15.2 dB, respectively. [ABSTRACT FROM AUTHOR]

Objectives: To test the association of 45 single nucleotide polymorphisms (SNPs) with transition to psychiatric disorders in a cohort of individuals at ultrahigh risk (UHR) mental state for psychosis. Methods: Through general population screening, 88 non-help-seeking UHR subjects and 130 healthy control individuals were genotyped for 45 SNPs related to psychosis. They were followed for a mean of 2.5 years, and conversion to psychotic and to general psychiatric disorders was assessed. Genotype frequencies between controls, converters, and non-converters were analyzed. Results: There were no differences in sociodemographics between controls and UHR. Also, UHR converters and non-converters had no differences in their baseline symptoms scores. The dopamine receptor D2 gene (DRD2) SNP rs6277 was significantly more common among UHR who transitioned to psychosis (p < 0.001) and to UHR who transitioned to any psychiatric disorders (p = 0.001) when compared to UHR who did not transition. The rs6277 T allele was related to psychiatric morbidity in a dose-response fashion, being significantly more frequent in UHR converters than UHR non-converters and control subjects (p = 0.003). Conclusion: Our findings suggest that rs6277 could potentially constitute a genetic marker of transition to psychiatric disorders in subjects with at-risk mental states, warranting further investigation in larger samples. [ABSTRACT FROM AUTHOR]

Pre-scalers are widely used in phase-locked loops (PLL) which are vital components in communication systems. The Dual Modulus Pre-Scaler (DMPS) has dual division capability, to divide the clock by N/N+1 cycles, which can be controlled by the designer based on the control circuitry. Pre-scaler circuits are used to divide the received signal to obtain integer multiples of the received signal. This paper proposes a power efficient 32/33 pre-scaler for high-frequency operation. DMPS is composed of a series of D Flip-flops (D-FF) and logic gates along with feedback connection between the different stages. Clock skew is of major concern in the D-FFs, which can be reduced by realizing D-FFs using true single-phase clock (TSPC) logic. Furthermore, the incorporation of an Adaptive Voltage Level Source (AVLS) circuit decreases the power consumption of the circuits. By integrating the AVLS circuit to divide-by-32/33 DMPS, low power consumption is achieved. At different operating frequencies, both divide-by-32 and -33 modes of the proposed 32/33 DMPS with AVLS were analyzed. In comparison to the reference pre-scaler circuit, the proposed pre-scaler consumes 35.65% less power at 1GHz. CMOS 180nm technology in Cadence Virtuoso is used to realize circuits and Cadence Spectre is used to simulate circuits.

Flip-flops (FFs) are an essential component of digital circuits, yet they use a lot of power and energy. This paper introduces the VLFF, an extremely low-power flip-flop that operates with just two single-phase clock transistors. The extracted simulation results show that VLFF is the most power-efficient FF amongst all examined FFs for the data activity (DA) range of 0% to 45%. Test-chip measurement results for the test-chip designed in TSMC CMOS 65 nm gp PDK demonstrate that at VDD = 1 V, power consumption is reduced by 63% and 16% with 12.5% DA, and 52% and 6% with 25% DA in comparison to TGFF and 18TSPC, respectively. • This paper proposed a very low-power flip-flop with only two single-phase clock transistors. • Proposed flip-flop is the most power-efficient amongst all considered. state-of-the-art flip-flops for data activities in the range of 0 – 45%. • Test-chip implemented in TSMC 65nm GP PDK validates the power savings of the proposed flip-flop over 18TSPC, and TGFF. [ABSTRACT FROM AUTHOR]

As an alternative to nanoelectronic devices, the quantum‐dot cellular automata (QCA) offer new opportunities to design high‐level algorithms and architectures. Using parallel processing, high speed, and low energy consumption, this emerging technology is very suitable and efficient for operational needs that require a large amount of computing and are often time consuming. In this paper, a new and optimal T‐latch design is introduced. The proposed latch structure has less occupied area and energy consumption than the existing implementation methods. In the proposed T‐latch the cell, area and energy consumption are reduced by 9.52%, 6.45%, and 19.67% compared to the best previous designs, respectively. Also, in this article, the T‐latch with reset and T‐latch with set/reset terminals are designed. Then, using the proposed T‐latch, various other latches are designed to ensure the correct operation of the designed T‐latch. Finally, to show that the proposed latch works properly in more complex circuits, they are used in the design of 1‐bit, 4‐bit, and n‐bit counters and the results of the simulations show the proper operation of the circuit. The proposed methods are simulated using the QCADesigner software and compared with other designs in terms of cell number, area, and energy consumption. [ABSTRACT FROM AUTHOR]

One of the essential elements of computing is the memory element. Flip-flops form an integral part of a System-on-Chip (SoC) and consume most of the area on the die. Tomeet the high-speed performance demands by the data-intensive applications such as artificial intelligence, cloud computing, and machine learning, we propose to integrate memory with the logic to get built-in memory Logic circuits that operate based on the crosstalk computing logic. These circuits are called Crosstalk Built-in Memory Logic (CBML) circuits, which exploit the detrimental interconnect crosstalk and astutely turn this unwanted effect into a computing principle with embedded memory. By virtue of our novel CBML circuit technique, the logic is computed, and the result is stored intrinsically within these complex circuits. The stored values will be retained irrespective of the change in input until the next logic evaluation cycle. This neoteric embedding of memory in logic provides high-speed operation with a reduced number of transistors. In this article, we have manifested the built-in memory feature of the complex CBML circuits using 16 nanometer (nm) PTM models in HSPICE. Benchmarking is performed by comparing with the equivalent static CMOS circuits to compare the number of transistors, power, and performance. It is observed that the number of transistors consumed by CBML 4-bit Full-Adder (the key element prevalent in Arithmetic circuits, e.g., ALU, Counters) is up to 46% less, and performance is improved by 27% over the equivalent CMOS circuits. This circuit serves as an example of a large-scale CBML circuit. Also, the performance improvement achieved by other circuits such as 3-input AND and the CARRY logic is up to 60% along with a 40% reduction in the number of transistors. CBML circuits have the potential to pave the way for special high-speed macros with specifically engineered structures. [ABSTRACT FROM AUTHOR]

In this study, a self-shut-off pulsed latch (SSPL) is proposed as sequencing elements for reducing the hold time constraint. As SSPL captures the data input after the clock edge, the large setup-time problem that exists in the master–slave flip-flop (MSFF) is eliminated. In addition, the transparency windows are closed immediately after successfully capturing the data input (self-shut-off), and the proposed SSPL is devoid of the large hold-time problem existing in conventional pulsed latches. According to the 7-nm FinFET postlayout simulation results, the sequencing timing overheads improved by 40% and 36% in SSPL, in comparison with the conventional MSFF at $V_{\mathrm {DD}} =0.4$ and 1.0 V, respectively. Furthermore, the hold time reduced by 54% and 58% in SSPL and at $V_{\mathrm {DD}} =0.4$ and 1.0 V, respectively, in comparison with the conventional pulsed latch. [ABSTRACT FROM AUTHOR]

A low power flip-flop is demanding delay element in digital sigma delta modulator of DAC system. This paper highlights power optimisation of single-phase clocked feedback D flip-flop using various optimisation techniques like clock gating, MTCMOS etc. In this scenario, clock gating using GDI and single-phase clocked inverter is invented to avoid unwanted no data transitions of flip-flop, also proposed type is compared with existing techniques. In addition to this, full swing GDI (gate-Diffusion Input) cell itself is modified by single phase clocked inverter to minimise threshold voltage drop and unwanted spikes at the output. There is trade off in area, speed and power. This work is based on power optimisation with favourable speed and area. Flip-flop is verified for clock frequency of 50 MHz as well as CDMA (Code Division Multiple Access) frequency of 1.6 MHz. Analysis is carried out in SPECTRE simulator of CADENCE environment with 180 nm technology supplied by AMS. Not only power but delay is also measured to check the performance of flip-flop. Proposed circuit gives 92.8% power and power delay product improvement. [ABSTRACT FROM AUTHOR]

A low-voltage and low-power true single-phase flip-flop that minimum the total transistor count by using the pass transistor logic circuit scheme is proposed in this paper. Optimization measures lead to a new flip-flop design with better various performances such as speed, power, energy, and layout area. Based on post-layout simulation results using the TSMC CMOS 180 nm and 90 nm technologies, the proposed design achieves the conventional transmission-gate-based flip-flop design with a 53.6% reduction in power consumption and a 63.2% reduction in energy, with 12.5% input data switching activity. In order to further the performance parameters of the proposed design, a shift-register design has been realized. Experimental measurements at 0.5 V/0.5 MHz show that this proposed design reduces power consumption by 47.3% while achieving a layout area reduction of 30.5% compared to the conventional design. [ABSTRACT FROM AUTHOR]

Flip-flop research in recent years has been motivated by power- and/or energy-efficient designs. Flip-flop power is based on data activity (DA), which in many applications ranges from 5 to 15%. In such cases, a substantial amount of clock power and energy is wasted. In this paper, a power-efficient, contention-free flip-flop with only three single-phase clock transistors is proposed, which has low-power consumption and eliminates unnecessary internal transitions in the circuit. This flip-flop is referred as 3CTSPC. Test-chip measurement results show that at VDD = 1 V, CK = 25 MHz, and DA = 12.5%, 3CTSPC is 11% and 58% more power-efficient than 18TSPC and TGFF, respectively. [ABSTRACT FROM AUTHOR]

Soft errors induced by Single Event Transient (SET) or Single Event Upset (SEU) are a great threat to integrated circuits. To reduce the error rate and improve the reliability of the circuits, we proposed a radiation hardened flip-flop in this paper, namely, Soft Error Detection and Recovery flip-flop (SEDR-FF). Error detection is based on delayed sampling and redundant storage by a redundant latch. A pulsed clock is adopted to control the redundant latch to reduce the hold time constraint of the latch. To generate the pulsed clock, two efficient delay elements are presented in this paper. Error recovery is accomplished by reloading the previous data stored in a history latch. Transistor-level simulations and timing-annotated gate-level simulations under 65 nm technology show that the proposed flip-flop can efficiently detect and correct the soft errors caused by SET or SEU. It has low overhead of setup time, and is suitable for high-performance designs. In addition, compared with other radiation hardened cells, the proposed flip-flop has moderate power and area overhead, and has lower area cost for fixing hold time violations in circuits designs. [ABSTRACT FROM AUTHOR]

As the safety-critical applications (e.g., automotive and medical electronics) emerge, various techniques of radiation hardening by design (RHBD) are proposed to deal with soft errors. Among all RHBD techniques, Built-In Soft-Error Resilience (BISER) is the first one to apply the delayed latching to separate input signals on all flip-flops for error detection. However, the delay values induced by BISER extend the setup time of all flip-flops, and may fail to meet the timing specification of the design. For minimizing such delay impact on the setup time of each flip-flop, we propose the Automated Latching-Delay Assignment (ALDA) to transfer partial values to the CK-Q delay. Later, Time-Borrowable D-Flip-Flop (TBD-FF) as well as a modified design flow is also proposed to realize the delay assignment by ALDA and to complete the design hardening. Experiments show that ALDA together with TBD-FF effectively protects five benchmark circuits against soft errors, and optimally avoids the timing violations caused by the prior delayed-latching solutions. [ABSTRACT FROM AUTHOR]

Featured Application: The DICE flip-flops presented in this work show strong resistance to single event upsets making them attractive for use in space or in environments where high reliability is a concern. Fully Depleted Silicon on Insulator (FD SOI) technology nodes provide better resistance to single event upsets than comparable bulk technologies, but upsets are still likely to occur at nano-scale feature sizes, and additional hardening techniques should be explored. Three flip-flop designs were implemented using Dual Interlocked Cell (DICE) latches in a 22 m FD SOI technology node. Additional hardening was implemented in the layout of each design by using transistor spacing and interleaving. Comparisons were made between a standard DICE design and two other designs making use of the new Continuous Active (CnRx) Diffusion construct and guard-gate transistor stacking through alpha particle and heavy ion irradiation. Designs making use of the CnRx construct for performance improvements were more likely to experience upsets due to higher collected charges in the increased diffusion regions. Conversely, transistor stacking showed strong soft error rate resilience because of the natural isolation between transistors in the FD SOI technology. Overall, the efficacy of transistor interleaving in flip-flops using DICE latches was found to be extremely robust in the 22 nm FD SOI technology node. [ABSTRACT FROM AUTHOR]

This article presents a 9-bit 500-MS/s 2-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC) with an error-tolerant interpolation technique. The proposed interpolation technique uses flip-flops to implement a 2-bit/cycle operation in the SAR ADC. By taking advantage of the metastable region of the flip-flop, the proposed interpolator can defer the bit decision when a decision error occurs with a high probability. Because the SAR ADC approximates the signal range step by step, the deferred decisions proceed to the next conversion cycles without any increase in quantization noise. The deferring-decision characteristic increases the error tolerance in the presence of comparator mismatches and increases the inherent linearity of the interpolation technique compared to conventional latch interpolation. A prototype ADC was designed using the 28-nm CMOS technology to verify the effectiveness of the proposed interpolation technique. The measured signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) at the Nyquist rate are 50.6 and 61.4 dB, respectively. The power consumption is 1.87 mW at a sampling frequency of 500 MS/s. The proposed ADC achieves a Walden figure of merit (FoM) of 13.5 fJ/conversion-step. [ABSTRACT FROM AUTHOR]