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The coupling effect of negative bias temperature instability (NBTI) and total ionizing dose (TID) was investigated by simulation based on the fully depleted silicon on insulator (FDSOI) PMOS. After simulating the situation of irradiation after NBT stress, it was found that the NBTI effect weakens the threshold degradation of FDSOI PMOS under irradiation. Afterward, NBT stress was decomposed into high gate voltage stress and high-temperature stress, which was applied to the device simultaneously with irradiation. The devices under high gate voltage exhibited more severe threshold voltage degradation after irradiation compared to those under low gate voltage. Devices at high temperatures also exhibit more severe threshold degradation after irradiation compared to devices under low temperatures. Finally, the simultaneous effect of high gate voltage, high temperature, and irradiation on the device was investigated, which fully demonstrated the impact of the NBT stress on the TID effect, resulting in far more severe threshold voltage degradation. [ABSTRACT FROM AUTHOR]

After more than five decades, Moore's Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures. [ABSTRACT FROM AUTHOR]

A trajectory comparison method is proposed to study the impact of back-gate radiation on single-event effects (SEE) of ultrathin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FDSOI) MOSFETs using Synopsys Sentaurus technology computer-aided design (TCAD) tools. Based on the series coupling capacitance model of the threshold voltage, the influence of device parameters such as buried oxide (BOX) thickness, ground plane doping and back biasing on the back-gate radiation effect is analyzed. The electrostatic potential difference between the BOX/substrate interface and substrate region decreases due to the reduced width of the substrate depletion region caused by back-gate radiation, leading to a positive shift in the threshold voltage and a decrease in the transient leakage current. The back-gate radiation effect is enhanced with reduced BOX layer thickness and ground-plane doping. UTBB FDSOI devices under reverse back biasing from 0 V to −0.5 V, which expands the depletion region, show a more dramatic decrease in the transient leakage current than those under forward back biasing. The findings contribute to a better understanding of the SEE mechanism of UTBB FDSOI devices and are helpful in radiation hardness optimization. [ABSTRACT FROM AUTHOR]

Unprecedented growth in CMOS technology and demand of high-density integrated circuits (ICs) in semiconductor industry has motivated to research community towards the development of MOS technology from micrometre regime to nano-meter regime. This paper presents the development of MOS technology from classical MOS technology to non-classical MOS technology and their extensions of learning towards the machine. Firstly, the studies are analysed with the scaling and limitations of bulk MOSFET beyond 100 nm in terms of constant and voltage field scaling and various short channel effects. Then we investigated the non-classical device architecture beyond 32 nm such as multiple-gate field-effect transistors, SOI MOSFETS, FINFETs, and gate-all-around FETs for the replacement of traditional CMOS devices. Next, we discussed the different architectures in the sub nano-technology regime. These structures include Carbon Nano Transistors, Single Electron Transistors (SET), Graphene Nano Ribbon, Nano Wire, and Nano Sheet Transistors. It is very conceivable that these kinds of devices will be utilized in the construction of high-density integrated electronic computers in near future. Lastly, we extend our studies on different machine learning method like ANN, KNN, DNN and Random Forest for the optimization of MOSFET, SOI FET, TFET, FinFET and GAA FET. [ABSTRACT FROM AUTHOR]

The coupling effect of negative bias temperature instability (NBTI) and total ionizing dose (TID) was investigated by simulation based on the fully depleted silicon on insulator (FDSOI) PMOS. After simulating the situation of irradiation after NBT stress, it was found that the NBTI effect weakens the threshold degradation of FDSOI PMOS under irradiation. Afterward, NBT stress was decomposed into high gate voltage stress and high-temperature stress, which was applied to the device simultaneously with irradiation. The devices under high gate voltage exhibited more severe threshold voltage degradation after irradiation compared to those under low gate voltage. Devices at high temperatures also exhibit more severe threshold degradation after irradiation compared to devices under low temperatures. Finally, the simultaneous effect of high gate voltage, high temperature, and irradiation on the device was investigated, which fully demonstrated the impact of the NBT stress on the TID effect, resulting in far more severe threshold voltage degradation.

After more than five decades, Moore’s Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

This paper presents an experimental study on the high-dose-rate transient ionizing radiation response and influencing factors of a Nano-Scale Fully Depleted Silicon-On-Insulator (FDSOI) D flip-flops (DFFs) circuit. Results indicate that data errors occur in DFFs at the lowest dose rate of 4.70 × 1011 rad(Si)/s in experiments, and the number of data errors shows a nonlinear increasing trend with the increase in dose rate and supply voltage. Three-dimensional technology computer-aided design (TCAD) simulations were conducted to analyze the transient photocurrent and charge collection mechanism at advanced process. The simulation results indicated that the charge collection efficiency is heightened with an increase in supply voltage, resulting in the higher photocurrent. This plays a major role in the process of charge collection for Ultra-Thin Body and Buried oxide (UTBB) FDSOI technology. The investigation into the high-dose-rate transient ionizing radiation effect (HDR-TIRE) in Nano-Scale FDSOI DFFs will aid in the assessment and application of advanced integrated circuits in aerospace. [ABSTRACT FROM AUTHOR]

A leap towards deriving a robust-compact model for ferroelectric-FET (FeFET) oscillator based spiking neurons has been developed. The compact model can capture and emulate neurons that exhibit both excitatory and inhibitory coupled dynamical behaviour, native to cortical neurons. The proposed model can reliably mimic neuronal dynamics for a broad-spectrum of FeFETs when, factored with appropriate validation of numerical simulations and physics-based models. The emulation of neuronal attributes based on FDSOI FeFET having qualitative agreement with previously reported data. The robustness of this analytical model has been investigated by tuning with ferro-dielectric (Fe) materials i.e., zirconium-doped HfO2 (HZO) and silicon-doped HfO2 (HSO) for mimicking the neurons. In continuance, the model is examined for emulating the cortical neurons by altering the inhibition (high-VGF) and excitation (low-VGF) inputs with a suitable frequency of operation for spiking neurons. [ABSTRACT FROM AUTHOR]

We reported three temperature regimes in subthreshold characteristics of 22-nm FD-SOI p-MOSFETs at operation ${T}\,\,=$ 300 K – 4.5 K. Subthreshold swing (SS)-plateau at 125 K – 50 K in combination with SS-linearity at ${T}\,\,=$ 300 K – 125 K and 50 K – 4.5 K were observed in different types of FD-SOI p-MOSFETs with channel length $(L_{G}) \leq100$ nm, which is possibly attributed to temperature-dependent dopant ionization induced band-to-band and trap-assisted tunneling across the drain-body junction. The phenomenon of SS linearly decreasing with temperature at ${T}$ < 50 K is not observed in neither FD-SOI n-MOSFETs nor 28 nm bulk CMOSFETs.

The paper presents a novel approach to the modeling of the back-gate dependence of the threshold voltage of Fully Depleted Silicon-On-Insulator (FDSOI) MOSFETs down to cryogenic temperatures by using slope factors with a gate coupling effect. The FDSOI technology is well-known for its capability to modulate the threshold voltage efficiently by the back-gate voltage. The proposed model analytically demonstrates the threshold voltage as a function of the back-gate voltage without the pre-defined threshold condition, and it requires only a calibration point, i.e., a threshold voltage with the corresponding back-gate voltage, front- and back-gate slope factors, and work functions of front and back gates. The model has been validated over a wide range of the back-gate voltages at room temperature and down to 3 K. It is suitable for optimizing low-power circuits at cryogenic temperatures for quantum computing applications.

Recent years have seen an increasing popularity in the development of brain-inspired neuromorphic hardware for neural computing systems. However, implementing very large scale simulations of neural networks in hardware is still an open challenge in terms of power efficiency, compactness, and biophysical resemblance. In an effort to design biologically plausible spiking neuron circuits while restricting power consumption, we propose a new subthreshold Leaky Integrate-and-Fire (LIF) neuron circuit designed using 22 nm FDSOI technology. In this circuit, problems of large leakage currents and device mismatch are effectively reduced by deploying the back-gate terminal of FDSOI technology for a tunable design. The proposed neuron is able to operate in two spiking frequency modes with tunable bias parameter setting of key transistors, and it results in complex firing behaviors, such as adaptation, chattering, and bursting, through varying bias voltages. We present circuit post-layout simulation results and demonstrate the biologically plausible neural dynamics. Compared with published state-of-the-art neuron circuits, the circuit dissipates ultra-low energy per spike, on the order of femtojoules per spike, at firing rates ranging from 30 Hz to 1 kHz. Furthermore, the circuit is proven to maintain a good robustness over process variation and Monte Carlo analysis, with relative error 3.02% at a firing rate of approximately 67.1 Hz. [ABSTRACT FROM AUTHOR]

In this article, negative capacitance effect on metal-ferro-metal-insulator-semiconductor (MFMIS) type FDSOI negative-capacitance-FET (NCFET) has been investigated by considering two well known thin-film ferro-dielectric ($ Fe$) materials HZO (zirconium:HfO $_{2}$) and HSO (silicon:HfO $_{2}$). The investigations are carried out in a well calibrated TCAD environment, where the gate-charge ($ Q_{G}$) is extracted from the TCAD simulation. And, subsequently computing the ferro-voltage ($ V_{Fe}$) across $ Fe$ -capacitor to estimate the total effective gate voltage ($ V_{GS}$) on the gate-stack of FDSOI NCFET. The depicted values are subjected to increment in $ Fe$ -thickness ($ t_{Fe}$) to optimize HZO and HSO $ Fe$ -materials for FDSOI NCFET(s). The optimised NCFET(s) are later levied with back-gate bias (V $_{\mathrm{B}}$) variation with the motivation of utilizing the attributes of FDSOI MOSFETs of V $_{\text{TH}}$ shift can further enhance the device performance. Depicted results has shown the HZO- $ Fe$ offers superior improvement in sub-threshold slope (SS), peak-transconductance (g $ _{m}$) and off-current (I $_{\text{OFF}}$) at lower $ t_{Fe}$ with the expense of lower endurance to hysteresis. On the other hand, the HSO- $ Fe$ predicts improvement in SS, peak-g $ _{m}$ and I $_{\text{OFF}}$ with higher endurance towards hysteresis in-spite of $ t_{Fe}$ thickness under sub-10 nm regime. Similarly, the V $_{\mathrm{B}}$ variation have shown similar results where the HSO NCFET has predicted slightly higher enhancement in performance aspect than HZO NCFET owing to the V $_{\text{TH}}$ shift phenomena attributed to FDSOI architecture and HSO- $ Fe$ comprehensible polarization duality. [ABSTRACT FROM AUTHOR]

FDSOI (Fully Depleted Silicon On Insulator) devices have a good performance in anti-single-event circuits. However, the bipolar amplification effect becomes a severe problem due to the buried oxide. The previous models for Single Event Transient (SET) of FDSOI did not fully consider the current of all components. Most importantly, they did not take the influence of the back-gate voltage into account. Thus, this paper presents a modeling method for the SET current in FDSOI MOSFET where all three components are modeled individually. The prompt current and diffusion current are modeled with a current source respectively. The Berkeley Short-channel IGFET Model for Silicon-on-Insulator (BSIMSOI) model is integrated into this model to calculate the bipolar amplification current. Compared to using the bipolar transistor model, this method avoids additional current input from the base electrode. It is more consistent with the mechanism of bipolar amplification effect for FDSOI devices without body contact. Instantaneously, an improved model is proposed that considers the influence of the back-gate voltage on the SET of the FDSOI devices. All models are validated through Technology Computer Aided Design (TCAD)simulation results. [ABSTRACT FROM AUTHOR]

The performance of the ultra-thin body and buried oxide fully-depleted silicon-on-insulator metal-oxide-semiconductor field-effect-transistors based on a 22 nm technology node is investigated in this paper over an ultra-wide temperature range from 6 K to 550 K. The currentâ€"voltage (I â€" V) characteristics under wide temperature range conditions are shown, including the influence of the back-gate bias (V bg). The important electrical parameters, such as threshold voltage (V t), subthreshold swing, ON-state current (I on), and OFF-state current (I off), are extracted with temperature changes. From 550 K to 6 K, V t increased by 0.21 V, I off decreased nearly six orders of magnitude, and the gate-induced drain leakage current decreased by nearly eight orders of magnitude. The main physical mechanisms for the changing electrical performance with temperature are the variation of carrier concentration, mobility, and energy band. By utilizing a technology computer-aided design simulation, the temperature dependence of the device performance is discussed and analyzed. [ABSTRACT FROM AUTHOR]

This paper presents the open-source Python-based parameter extractor (SEKV-E) for the simplified EKV (sEKV) model, which enables the modern low-power circuit designs with the inversion coefficient design methodology. The tool extracts the essential sEKV parameters automatically from the given $I$ - $V$ curves using the direct extraction and the multi-stage optimization process. It also handles the overfitting issue because of non-linear least squares. Moreover, this work demonstrates the SEKV-E as a universal tool by widely applying it to different silicon technologies, temperatures, dimensions, and back-gate voltages.

This paper identifies vulnerabilities to recently proposed countermeasures to leakage power analysis attacks in FDSOI systems based on the application of a random body bias. The vulnerabilities are analyzed and the relative difficulty to obtain the secret key, once the vulnerabilities are taken into account, are compared to the original proposals. A new countermeasure, based on a new body bias scheme, is then proposed. The new countermeasure is based on the equalization of asymmetries in static power consumption dependent on data being stored in registers implemented in FDSOI technology. The countermeasure’s effectiveness is theoretically established through the development of a power model based on technological parameters, and further reinforced through numerical simulations of a dummy cryptosystem implementing part of an AES encrypting round.

In this paper, we present a temperature and variability-aware Verilog-A-based compact model for simulating Ferroelectric FET. The model captures the rich physics of ferroelectric materials and the important electrical characteristics, such as the history effect, the impact of pulse width and amplitude on threshold voltage, and temperature-dependent degradation of polarization. The impact of variability is also explored regarding reliable operation of the FeFET. The developed model is robust and can accurately capture the experimentally observed trends, such as the change in polarization due to temperature, increased memory window on reading from the back-gate, etc. Further, we discuss two applications of our developed model viz. (a) multi-level-cell storage and (b) FeFET-based array for MAC operations. The designs are tested using the proposed model in commercial SPICE simulator at different temperatures including the effect of variation. Analysis presented in this article reveals that variability and temperature can be detrimental for operation of FeFET-based systems. • We presented impact of temperature and variability on FeFET. • New compact model incorporating these effects • FeFET multi-level cell storage with 8 different states. • 8×8 FeFET crossbar for multiply-and-accumulate (MAC) operation. • Impact of temperature and variability on these applications [ABSTRACT FROM AUTHOR]

Herein, a method for the electrical characterization of a fully depleted silicon‐on‐insulator (FDSOI) high‐k dielectric‐metal‐gate stack is proposed. The method is based on assessing low‐field mobility in FDSOI field‐effect transistor (FET) from current–voltage measurements at various temperatures in the gate voltage range up to strong inversion. In addition to assessing the value of the low‐field mobility for the stack itself, it allows specifying the impact of various carrier‐scattering mechanisms on the total stack mobility. Further, the application of double‐gate operation in the optimal coupling mode for the FET allows analysis of the impact of the gate interfaces on mobility. The method can be used in the monitoring of stack quality and in the design and development of stack fabrication processes. [ABSTRACT FROM AUTHOR]

In this paper, the self-heating effect for multi-finger fully depleted SOI nMOSFETs is investigated. The layout parameters of the transistor are varied, and the conductance-based method is used for the extraction of the thermal resistance. An empirical-based scalable thermal resistance model that accounts for geometrical layout parameters is developed. Further, hot carrier stress degradation is examined, and a correlation between self-heating and hot carrier degradation is established. The associated self-heating with geometrical dimension influences the amount of hot carrier degradation and should be taken into account for accurate degradation modeling. It is found that with the increase of temperature, the contribution of the parasitic bias temperature instability effect increases the drift of the threshold voltage. Improved thermal and reliability performance is achieved for the device structures where a continuous active area is divided into multiple smaller active regions. [ABSTRACT FROM AUTHOR]

Ferroelectric field-effect transistor (FeFET)-based circuit implementation mimicking FitzHugh-Nagumo neuron is proposed in this work. The proposed circuit is shown to mimic biological neuron properties, such as excitation block and anodal break excitation which are not mimicked by an integrate and fire neuron model. We also show a winner-take-all circuit that can be used with this proposed neuron implementation. The neuron implementation requires just one FeFET, three baseline field-effect transistors, and one capacitor, making it area and energy-efficient. The neuron circuit, with minimum sized transistors, consumes approximately 10 pJ per spike. The neuron’s energy consumption per spike can be reduced to as low as 100 fJ by designing some of the transistors with aspect ratio less than one. [ABSTRACT FROM AUTHOR]

The flexibility of field-programmable gate arrays (FPGAs) is attributed to the reconfigurability of their basic logic elements (BLEs). Traditionally, the BLEs are comprised of one or more lookup tables (LUTs) of $n$ inputs, that are designed to implement Boolean functions of $n$ or fewer inputs. In an attempt to reduce the area and power consumption that comes from using LUTs, a number of complex LUT architectures have been reported. Although most of the proposed complex LUT architectures have resulted in reduced area and power, this has always been at cost of the decreased performance. This article proposes a new FPGA architecture, called threshold logic FPGA (TLFPGA), which results in significant improvement in performance, power, and area (PPA). TLFPGA is comprised of a combination of LUTs and a new type of BLE referred to as a threshold logic cell (TLC) (Muroga, 1987). Although TLCs implement a relatively small subset of Boolean functions known as threshold functions (Muroga, 1987), they require far fewer registers and multiplexers than an LUT, and are also significantly faster. This article describes the architecture of the TLFPGA and a technology mapping algorithm tailored for a TLFGA. On average, TLFPGA designs use 18% fewer registers and multiplexers, which improves the collective area of BLEs by approximately 16%, power by 14%, and performance by 5%. The improvements have been demonstrated in both 40 and 28 nm technologies for ISCAS-85 circuits as well as practical circuits, using industry-standard flows. The improvements were also demonstrated using a layout of the architecture. [ABSTRACT FROM AUTHOR]

This review paper assesses the main approaches in the electrical characterization of advanced MOSFETs towards their future analog and RF applications. Those approaches are shown to be different from the traditionally used ones for the assessment of the device perspectives for digital applications. Based on the original research realized by our group over the last years, advantages and necessity of those techniques will be demonstrated on different study cases of various advanced MOSFETs, such as Fully Depleted Silicon-on-Insulator (FDSOI), FinFETs and NanoWires (NW) in a wide temperature range (from cryogenic, 4 K up to 250°C). A wide frequency band characterization (from DC up to hundred GHz range) will be positioned as a key element enabling a fair device assessment towards analog and RF applications. Importance of the “extrinsic” parasitic elements in the advanced devices is enormous, sometimes even dominating the device performance. Therefrom arises the need for a proper separate extraction and discussion of “intrinsic” versus “extrinsic” parameters.

This paper analyses a novel countermeasure to Leakage Power Analysis Attacks based on the application of a random Body Bias voltage level at the beginning of the encryption process. The countermeasure effectiveness is established through the development of a theoretical model of the Pearson correlation coefficient in the presence of a varying body bias under both noiseless assumptions and in the presence of algorithmic noise, and through simulations on a partial cryptosystem implemented in 28 nm FDSOI technology. A study of the effect of averaging power measurements is also developed and contrasted against Monte Carlo simulations of the countermeasure scheme, effectively providing a floor for the increase in required measurements to identify the secret key.

This paper demonstrates the critical role that Ferroelectric (FE) layer thickness ( $t_{FE}$ ) plays in Negative Capacitance (NC) transistors connecting device and circuit levels together. The study is done through fully-calibrated TCAD simulations for a $14nm$ FDSOI technology node, exploring the impact of $t_{FE}$ on the figures of merit of n-type and p-type devices, voltage transfer characteristic (VTC) and noise margin of inverter as well as the speed of buffer circuits. First, we analyze the device electrical parameters (e.g., $I_{ON}$ , $SS$ , $I_{ON}/I_{OFF}$ and $C_{gg}$ ) by varying $t_{FE}$ up to the maximum level at which hysteresis in the I-V characteristic starts. Then, we analyze the deleterious impact of Negative Differential Resistance (NDR), due to the drain to gate coupling, demonstrating how it imposes an additional constraint limiting the maximum $t_{FE}$ . We show the consequences of NDR effects on the VTC and noise margin of inverter, which are essential components for constructing robust clock trees in any chip. We demonstrate how the considerable increase in the gate’s capacitance due to FE seriously degrades the circuit’s performance imposing further constraints limiting the maximum $t_{FE}$ . Further, we analyze the impact of $t_{FE}$ on the SRAM cell static performance metrics such hold noise margin (HNM), read noise margin (RNM) and write noise margin (WNM) at supply voltages of 0.7V and 0.4V. We demonstrate that the HNM and RNM in a NC-FDSOI FET based SRAM cell are higher then those of the baseline FDSOI FET based SRAM cell noise margin and further increase with $t_{FE}$ . However, the WNM in general follows a non monotonic trend w.r.t $t_{FE}$ , and the trend also depends on the supply voltage. Finally, we optimize the design of the SRAM cell considering overall performance metrics. All in all, our analysis provides guidance for device and circuit designers to select the optimal FE thickness for NCFETs in which hysteresis-free operations, reliability, and performance are optimized.

A frequency-reconfigurable SP4T switch is presented, in which ${R}_{\text {ON}} \times {C}_{\text {OFF}}$ characteristics of switch transistors are enhanced with plaid metal transistors and forward body biasing. Plaid metal transistors (PMT) with forward body bias (FBB) are used for all of the transistors to enhance the FoM. The plaid patterned metal accesses of a transistor for the source and drain decrease the extrinsic resistance and capacitance. FBB increases the overdrive voltage of a transistor and decreases the on-resistance. The SP4T switch includes main switch matrices that route an input signal to four-outputs, a switched inductor (SI) network, and a mode-selection switch. The SI network connected through the mode-selection switch resonates out the off-capacitances of the main switch matrices at RF in the RF mode. The SP4T switch operates without the SI network in DC mode. The SP4T switch is implemented in a 28-nm FDSOI CMOS process. The core area occupies 0.2 mm2. The switch shows less than 2 dB insertion loss from DC to 4.4 GHz in the DC mode and from 4.4 to 5.3 GHz in the RF mode, where isolations are more than 16.8 dB and 18 dB, respectively. [ABSTRACT FROM AUTHOR]

Industrial plants suffer from a high degree of complexity and incompatibility in their communication infrastructure, caused by a wild mix of proprietary technologies. This prevents transformation toward Industry 4.0 and the Industrial Internet of Things. Open platform communications unified architecture (OPC UA) is a standardized protocol that addresses these problems with uniform and semantic communication across all levels of the hierarchy. However, its adoption in embedded field devices, such as sensors and actuators, is still lacking due to prohibitive memory and power requirements of software implementations. We have developed a dedicated hardware engine that offloads processing of the OPC UA protocol and enables the realization of compact and low-power field devices with OPC UA support. As part of a proof-of-concept embedded system, we have implemented this engine in a 22-nm FDSOI technology, representing the first ASIC implementation of an OPC UA server. We measured performance, power consumption, and memory footprint of our test chip and compared it with a software implementation based on open62541 and a Raspberry Pi 2B. Our OPC UA hardware engine is 50 times more energy efficient and only requires 36 KiB of memory. The complete system consumes only 24 mW under full load, making it suitable for low-power embedded applications. [ABSTRACT FROM AUTHOR]

In this article, by using neural network, we proposed a method to optimize Fully-Depleted (FD) Silicon-on-Insulator (SOI) Field-Effect-Transistor (FET) structures to maximize the on/off current ratio for 14-nm node (70-nm Gate Pitch) System-on-Chip (SoC) and sequential 3-dimensional integrated circuit (3DIC). Using machine learning method, the neural network accurately predicted the electrical behaviors of 14-nm node FDSOI FETs. Also by using backpropagation and gradient descent method, the device structures were modified to improve on/off current ratios for high performance (HP), low operating power (LOP), and low stand-by power (LSTP) applications. These optimized structures were secured within the process range of conventional FDSOI FETs. Among the optimized parameters, drain-side spacer length (Lspd), source/drain junction gradient (Lsdj), and thickness of source/drain epi (Tsd) showed different behaviors for each application and thickness of buried oxide (Tbox) was maximal in optimization results. The detailed physical analysis was conducted to evaluate these parameters for each application. The neural network based optimization was powerful and efficient while saving time and cost in device design.

This work studies the self-heating (SH) effect in ultra-thin body ultra-thin buried oxide (UTBB) FDSOI MOSFETs at cryogenic temperatures down to 77 K. S-parameter measurements in a wide frequency range, with the so-called RF technique, are employed to assess SH parameters and related variation of analog figures of merit (FoMs) at different temperatures. Contrary to the expectations, the effect of self-heating on analog FoMs is slightly weaker at cryogenic temperatures with respect to room-temperature case. The extracted thermal resistance and channel temperature rise at 300 K and 77 K in short-channel devices are of the same order of magnitude. The observed increase in SH characteristic frequency with temperature reduction emphasizes the advantage of the RF technique for the fair analysis of SH-related features in advanced technologies at cryogenic temperatures.

In this work, we assess the applicability of the well-known split CV technique for mobility extraction in 28 nm FDSOI transistors with gate length down to 25 nm using TCAD simulations. We identify the significant bias dependence of the parasitic source/drain resistance and the contribution of the inner fringing capacitance as the main sources of error in the conventional split CV extraction. An improved split CV method, correcting for these parasitics, is demonstrated to accurately extract the effective mobility and its dependence on the gate voltage for devices down to 25 nm gate length. Measurements on 28 FDSOI transistors confirm the insights from the TCAD simulations. [ABSTRACT FROM AUTHOR]

A triple modular redundancy SRAM was designed as the embedded high-speed memory for a radiation-tolerant ARM processor with ST Microelectronics 28-nm FDSOI technology. The single event upset (SEU) cross-section of the SRAM was tested by using heavy ions with the linear energy transfer of 15.0 meV.cm2.mg−1 in both non-TMR and TMR modes with different accumulated fluence. The SRAM cell was also simulated by using Cogenda TCAD simulation suite and the cross section was calculated by using analytic method. The results showed the cross-section is around 2E-10 cm2/bit in non-TMR mode, and in TMR mode it varied from one to several orders lower than the non-TMR mode according to the specific accumulated fluence. As a scrubbing circuit was designed to reduce the accumulated number of SEUs in the SRAM, the Failure In Time (FIT) rate at sea level in New York City could be as low as 8E-11, which is robust enough for the whole circuit. [ABSTRACT FROM AUTHOR]

This paper presents a novel FDSOI FinFETs with SiGe channel/Si cap layer (35 nm/5 nm) formed on SOI wafers with 20 nm Si body. Electrical characterization result shows that JL FDSOI FinFETs with SiGe channel exhibited low subthreshold slope (SS) of 86 mV/decade and record high ON-OFF current ratio (I ON /I OFF = 2 × 106) at V D = -0.5V, respectively. Device performance improvement was mainly attributed to high-epitaxial quality compressive strained SiGe channel and novel device structure. The strain in the channel of the transistors was estimated locally in TEM using Nano beam diffraction (NBD) technique. The FDSOI FinFET with SiGe channel, lays the foundation for the further development of high speed, high density, low cost, and 3D monolithic integration circuits. [ABSTRACT FROM AUTHOR]

Gate configuration phase transition fully depleted silicon-on-insulator (FDSOI) metal- oxide-semiconductor field-effect transistor (MOSFET) without an external resistor is proposed using Pb(Zr0.52Ti0.48)O3 (PZT)-based threshold selector (TS). Under 1 μA compliance current condition, the PZT-based TS exhibits its threshold switching property at ~0.9 V (threshold voltage) and ~0.01 V (hold voltage) over 4 orders of current. And its off-resistance is measured as ~2.3 × 1011 Ω. The PZT-based gate configuration phase transition FDSOI MOSFET without an external resistor was fabricated by connecting the PZT-based TS to a baseline FDSOI MOSFET. It is confirmed that the fabricated external resistor-free phase transition FDSOI MOSFET can operate regardless of the aforementioned 1 μA of compliance current condition. This device has not only demonstrated the feature of ~4 mV/decade subthreshold slope at ~0.96 V of gate voltage, but it also has decreased the gate leakage current of the baseline FDSOI MOSFET by ~10 times at 0 V of gate voltage and ~320 times at 2 V of gate voltage.

This paper presents detailed RF characterization of 28-nm FDSOI nMOSFETs at cryogenic temperatures down to 77 K. Two main RF figures of merit (FoM), i.e., current gain cutoff frequency (fT) and maximum oscillation frequency (fmax), as well as elements of small-signal equivalent circuit are extracted from the measured S-parameters. Increases of fT and fmax by about 85 GHz and about 30 GHz, respectively, are demonstrated at 77 K. The observed behavior of RF FoMs versus temperature is discussed in terms of small-signal equivalent circuit elements, both intrinsic and extrinsic (parasitics). This paper suggests 28-nm FDSOI as a good candidate for future cryogenic applications.

Soft-error tolerance depending on threshold voltage of transistors was evaluated by α -particle, heavy-ion, and neutron irradiation. Three chips were fabricated, one embeds low-threshold general-purpose (GP) transistors and the others embed high-threshold low-power (LP) transistors in a 65 nm fully depleted silicon on insulator (FDSOI) process. There were a few errors on LPDFFs (DFFs with LP transistors). Error probability (EP) of LPDFFs was 99.88% smaller than that of GPDFFs (DFFs with GP transistors) by α particles. Average cross sections (CSs) of LPDFFs by heavy ions were 50% smaller than those of GPDFFs. Average soft-error rates (SERs) of LPDFFs by neutrons were 68% smaller than those of GPDFFs. 3-D device simulations revealed that CSs of the LP and GP transistors are changed by fitting methods using the work function of the gate material and doping concentration of the substrate under the BOX layer. The difference is due to the number of carriers in diffusion and silicon thickness of the raised layer above drain and source terminals.