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Vertical p-channel MOSFETs have been experimentally fabricated and characterized. Device characteristics of vertical p-channel MOSFETs are comparable to those of planar surface devices. Conduction current of a vertical transistor can be increased as much as four times that of a planar transistor for the same device area. The feature of large W/L ratio allows further increase in device density. Conduction current increases linearly with the channel width. No 3D current conduction degradation effect has been observed. It is found that the crystallographic orientation of the conduction channel has some effect on the threshold and sub-threshold characteristics, due to oxide thickness difference or fixed charges in the oxide interface. >

Single-ended complementary pass-transistor logic (CPL), also known as LEAP. has been a popular choice for implementing high-performance arithmetic operations due to its efficiency in device use. The circuit, however, is predicted to exhibit a large history effect when implemented in a partially depleted SOI (PD/SOI) technology. This paper presents direct measurement of its history effect in a 0.18/spl mu/m, 1.5V PD/SOI technology with L/sub eff/ = 0.08 /spl mu/m and t/sub ox/ = 2.3 nm.

Describes a 1-Mbit high-speed DRAM (HSDRAM), which has a nominal random access time of less than 27 ns and a column access time of 12 ns with address multiplexing. A double-polysilicon double-metal CMOS technology having PMOS arrays inside n-wells was developed with an average 1.3- mu m feature size. The chip has also been fabricated in a 0.9*shrunken version with an area of 67 mm/sup 2/, showing a 22-ns access time. The chip power consumption is lower than 500 mW at 60-ns cycle time. This HSDRAM, which provides SRAM-like speed while retaining DRAM-like density, allows DRAMs to be used in a broad new range of applications. >