Measurement of history effect in PD/SOI single-ended CPL circuit

Authors :: F.L. Pesavento
R. Puri
Ching-Te Chuang
K.A. Jenkins
Source :: 2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207).
Publication Year :: 2002
Publisher :: IEEE, 2002.
Abstract: Single-ended complementary pass-transistor logic (CPL), also known as LEAP. has been a popular choice for implementing high-performance arithmetic operations due to its efficiency in device use. The circuit, however, is predicted to exhibit a large history effect when implemented in a partially depleted SOI (PD/SOI) technology. This paper presents direct measurement of its history effect in a 0.18/spl mu/m, 1.5V PD/SOI technology with L/sub eff/ = 0.08 /spl mu/m and t/sub ox/ = 2.3 nm.

Subjects :: Engineering
CMOS
Pass transistor logic
business.industry
History effect
Hardware_INTEGRATEDCIRCUITS
Electrical engineering
Silicon on insulator
Hardware_PERFORMANCEANDRELIABILITY
Device use
business
Hardware_LOGICDESIGN

Database :: OpenAIRE
Journal :: 2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207)
Accession number :: edsair.doi...........d5dbcbbad451298f88acae7ab7e67529
Full Text :: https://doi.org/10.1109/soic.2001.957983