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Quantum-dot cellular automata (QCA) nanotechnology offers efficient design of digital circuits. High-speed, low-energy consumption, low-area requirement are the significant features of QCA nanotechnology. An exclusive-OR (EXOR) gate has been applied to design various digital applications. Hence, an efficient EXOR gate design needs to be implemented. This research work proposes a translation-based three input EXOR gate in QCA nanotechnology. The proposed EXOR gate is extensively explored for fault analysis. The power dissipation analysis is also given for the proposed EXOR gate. The proposed EXOR gate has only 10 cells and two clock latencies. For the performance evaluation of the proposed EXOR gate, a comparative analysis is provided for different parameters. The proposed EXOR gate outperforms in comparison to the existing EXOR gates in QCA nanotechnology. It improves the cell area by 25% and the layout cost by 23.08% in comparison with the best-reported three input EXOR gate in the literature. The efficacy of the proposed three input EXOR gate for the digital circuit implementation is noted by designing a 1-bit full subtractor, a 4-bit parity checker, and a 4-bit binary to gray (B2G) code converter. [ABSTRACT FROM AUTHOR]

Security, a fundamental concern in the design and implementation of industrial Internet‐of‐Things (IIoT) networks, can be addressed through an effective authentication mechanism. Because the devices' battery, CPU, and memory are finite resources, any method designed for the IIoT must be resource sensitive. Our paper discussed a mechanism for device mutual authentication in IIoT networks that is adaptable, lightweight, safe, and efficient. In the proposed mechanism, the devices receive a primary secret value and physical unclonable function‐challenge/response pair (PUF‐CRPs) from the server and employ these values to authenticate one another. Later, IIoT devices requests server to update PUF‐CRPs for future communication We employed one‐way hash function, concatenation operation, XOR operation, and PUF‐CRPs to take into account the resource constraints of the devices. It has been established that the proposed mechanism is immune to well‐known attacks after it has undergone a formal evaluation for safety through BAN logic, and automatic validation through AVISPA and ProVerif tools. Comparative evaluation of the existing mechanisms and the proposed mechanism demonstrated that our proposed mechanism is superior to existing mechanisms, and its experimental study revealed that it uses 28% less energy. Our proposed mechanism is more secure and effective in terms of computing, communication, and storage overheads. [ABSTRACT FROM AUTHOR]

The difficulty of manufacturing and noise sensitivity of quantum-dot cellular automata (QCA) make wire-crossings optimization increasingly important. Novel logic primitives such as majority-of-five (MAJ5) and XOR-of-three (XOR3) with efficient QCA realizations can alleviate the wire-crossings issue. In this paper, we aim at 13 standard three-input Boolean functions, the QCA layouts of which are designed by introducing MAJ5 (Method A) and its combinations with XOR3 (Method B). The proposed designs are verified by the QCADesigner tool. Experimental results show we can reduce the number of QCA cells and area. In terms of area, we can achieve 30.69% and 48.35% reduction by Method A and B, respectively, compared with the state-of-the-art approach. The proposed designs are further used as building blocks for large-scale circuit designs. In one implementation, the Peres reversible gate is implemented based on Method B to decrease the area by 33.3%. [ABSTRACT FROM AUTHOR]

In spatial domain image steganography, Least Significant Bits (LSB) of cover image pixels are used to embed a secret message due to minimal distortion and higher payload capacity. In this paper, we have introduced an exclusive-OR (XOR) based encoding of encrypted secret message bits using varying higher-order pixel intensity bits. Encoding and LSB embedding is done block-wise by dividing the cover image into a number of blocks. The secret message is first encrypted using symmetric key cryptography and then encoded those encrypted bits by XORing them with randomly selected higher-order pixel bis of the cover image to obscure the secret bits further. Next, an inversion technique is applied to the encoded bits block-wise to keep the LSB bit changes to a minimum. The stego-key consists of the symmetric encryption key and the encode-key containing parameter settings such as the number_of_blocks, starting_block, start_pixel_offset, block_selection_rule, etc. This stego-key is shared prior to the actual communication using public-key cryptography to ensure the key's authenticity and integrity. The extraction process does not require the cover image; the stego-image and the stego-key are sufficient. Experimental results show the visual imperceptibility along with improved image quality metrics such as Mean Square Error (MSE), Peak Signal to Noise Ratio (PSNR), Normalized Cross-Correlation (NCC), and Structural Similarity (SSIM) index in comparison to other well-known techniques. The average PSNR value remains above 51dB, even with 90% of the capacity utilized. The proposed scheme successfully eludes many standard steganalysis attacks such as histogram-based analysis (PDH), chi-square based embed probability test, Regular and Singular groups (RS) analysis, sample pair test, etc. on the tested stego-images. [ABSTRACT FROM AUTHOR]

A new technique for progressive visual secret sharing (PVSS) with adaptive priority weight is proposed in this paper. This approach employs the bitwise and eXclusive-OR (XOR) based approaches for generating a set of shared images from a single secret image. It effectively overcomes the former scheme limitation on dealing with an odd number of stacked or collected shared images in the recovery process. The presented technique works well when the number of stacked shared images is odd or even. As documented in experimental results, the proposed method offers good results over binary, grayscale, and color images with a perfectly reconstructed secret image. In addition, the performance of the proposed method is also supported with theoretical analysis showing its lossless ability to recover the secret image. However, it can be considered as a strong substitutive candidate for implementing a PVSS system. [ABSTRACT FROM AUTHOR]

In this presented work we designed CMOS exclusive-OR/exclusive-NOR gates with the increase in performance than the existing method. The main aim of our project is to reduce the power and increase the performance. Two new methods are proposed to implement the exclusive-OR and exclusive-NOR functions on the transistor level. The first method which consists of CMOS Based exclusive-OR/exclusive-NOR design. In this method we have less power dissipation and delay which leads to less PDP value. The other one is combined exclusive-OR/exclusive-NOR design which improves the performance of the prior method. It uses the same number of transistors as but with more driving capability additionally. Simulations are verified through 130nm mentor graphics tool. [ABSTRACT FROM AUTHOR]

This paper proposes a new simple image encryption technique using the Beta chaotic map for performing the confusion and diffusion of input plain image. This image encryption is further applied to the multiple secret sharing (MSS). The former existing scheme in MSS employs the Chinese remainder theorem (CRT) and eXclusive-OR (XOR) operations to convert the secret image to become a set of shared images. The former scheme yields a good result while the number of secret images is even. However, it has slight limitation while the number of secret images is odd. This paper aims to overcome this problem by utilizing the proposed image encryption along with three new MSS approaches: 1) incorporating an additional random images; 2) performing k image encryption; and 3) using two different masking coefficients. As documented in the experimental section, the proposed method performs well in the MSS task. It solves the problem in former scheme on dealing with odd number of secret images. In addition, the proposed method is superior compared with the other competing schemes. The proposed image encryption also improves the security level in the MSS system.

A new technique on progressive secret sharing is presented. The proposed method offers two different approaches on converting a secret image into a set of shared images. The first approach exploits the generalized random grids or bitwise level computation, whereas the second approach utilizes the eXclusive-OR (XOR) operation to generate a set of shared images. The proposed method has lossless ability in the recovery process of secret image. This scheme performs well not only for binary image, but it also gives satisfactory result for grayscale and color secret image. As results show that the proposed method yields better results compared to the former existing schemes under visual investigation and objective assessment on the recovered secret image. In addition, the proposed method does not require high computational burden in the shared image generation as well as in the secret image recovery process. Yet, it can be regarded as good candidate for applying the progressive secret sharing with lossless reconstruction constraint. [ABSTRACT FROM AUTHOR]

Xorshift128+ is a newly proposed pseudorandom number generator (PRNG), which is now the standard PRNG on a number of platforms. We demonstrate that three-dimensional plots of the random points generated by the generator have visible structures: they concentrate on particular planes in the cube. We provide a mathematical analysis of this phenomenon. [ABSTRACT FROM AUTHOR]

Synchronization among groups of neurons is an interesting yet mysterious mechanism in the brain. We propose and demonstrate that the adjustable timing of neural activities can produce profound effect on learning and task implementation. On one hand, learning of more complex patterns becomes possible because of the enhanced capability of classification. On the other hand, implementation of a complex task is aided through active maintenance and control of multiple rules and items. This sheds light on the development of new intelligent system, as well as the cause of impaired learning and task performance in patients. [ABSTRACT FROM AUTHOR]

This article presents a high-speed and high-performance Carbon Nanotube Field Effect Transistor (CNFET) based Full Adder cell for low-voltage applications. The proposed Full Adder cell is composed of two separate modules with identical hardware configurations which generate the Sum and C out signals in a parallel manner. The great advantage of the proposed structure is its very short critical path which is composed of only two carbon nanotube pass-transistors. This design also takes advantage of the unique properties of metal oxide semiconductor field effect transistor-like CNFETs such as the feasibility of adjusting the threshold voltage of a CNFET by adjusting the diameter of its nanotubes to correct the voltage levels as well as to achieve a high performance. Comprehensive experiments are performed in various situations to evaluate the performance of the proposed design. Simulations are carried out using Synopsys HSPICE with 32-nm Complementary Metal Oxide Semiconductor (CMOS) and 32-nm CNFET technologies. The simulation results demonstrate the superiority of the proposed design in terms of speed, power consumption, power delay product, and less susceptibility to process variations, compared to other classical and modern CMOS and CNFET-based Full Adder cells. [ABSTRACT FROM PUBLISHER]

We prove the following result regarding operations on a binary word whose length is a power of two: computing the exclusive-or of a number of rotated versions of the word is an invertible (one-to-one) operation if and only if the number of versions combined is odd. (This result is not new; there is at least one earlier proof, due to Thomsen [Cryptographic hash functions, PhD thesis, Technical University of Denmark, 28 November 2008]. Our proof may be new.) [ABSTRACT FROM AUTHOR]

This paper demonstrates the signal performance Fobtained by combining data from two 10 Gbps SiGe serializers using a very high-speed, low-jitter InP exclusive-OR gate. The technique has been used in the past for lower-speed (i.e. ≤12.8 Gbps) applications. However, success at higher speeds depends upon tight control of timing and signal integrity. Relatively low-cost (off-the-shelf) components are used so that the method can be applied to test scenarios requiring many high-speed channels. Analysis of the demonstration circuit performance reveals the challenges, capabilities, and limitations of the method. A Development Platform is also described that facilitates individual module characterization and integration of multiple modules to form customized test systems. [ABSTRACT FROM AUTHOR]

The design and wafer probe test results of a 5-bit SiGe Flash ADC are presented. The integrated circuit, fabricated in a 200/250 GHz fT /Fmax, SiGe BiCMOS technology, provides a 5-bit analog to digital conversion with dual Nyquist operation at sample frequencies up to 20 GHz. Sampling clock rates are demonstrated as high as 35 GS/s. The ADC makes use of a comparator with an integrated exclusive-or function to reduce power consumption. The device also generates two half-rate interleaved outputs to ease data capture with laboratory equipment. An effective number of bits (ENOB) of nearly 5.0 is achieved for low-frequency input tones, dropping to 4.0 at 10 GHz. [ABSTRACT FROM AUTHOR]

In secret image sharing, a polynomial interpolation technique heavy experiences a computation load when the secret image is retrieved later. To the contrary, fast approaches often need larger storage space due to pixel expansion property. This paper proposes a missing-allowable (k, n) scheme which is fast and with a reasonable pixel expansion rate (per). The scheme generates n extremely-noisy shadow images for the given secret color image A, and any k out of these n shadows can recover A loss-freely. In average, to decode a color pixel of A, the retrieval uses only three exclusion-OR operations among 24-bit numbers. Hence, the new method has very fast decoding speed, and its pixel expansion rate is always acceptable (0 < per < 2). [ABSTRACT FROM AUTHOR]

Abstract: We propose a new encryption scheme using modified exclusive-XOR rules and a phase-wrapping technique. For image encryption, a gray image is sliced into binary images, which have the same pixel number, and these images are encrypted by the modified XOR rules with bipolar random images. The XORed images and the bipolar random images are combined respectively and converted into full phase images, called an encrypted image and a key image, by a phase-wrapping technique and phase-encoding method. The phase-wrapping technique can not only reduce the ranges of phase components of the encrypted image and the key image but also maintain randomness of these images. The decryption process is simply implemented by a phase-visualization system. Numerical simulations are carried out to verify the validity of the proposed scheme. [Copyright &y& Elsevier]

This paper describes the use of an evolutionary design system known as GANNET to synthesize the structure of neural networks. Initial results are presented for two benchmark problems: the exclusive-or and the two-spirals. A variety of performance criteria and design components are used and comparisons are drawn between the performance of genetic algorithms and other related techniques on these problems. [ABSTRACT FROM AUTHOR]

Shift Register, which is a cascade of flip flops shares the same clock and the outputs are connected to the data input of the next one in the chain. Linear-feedback shift register or shortly LFSR is one such shift register whose input is a linear function of its previous state. Exclusive-OR (XOR) is the most commonly used linear function. LFSR's help in generating pseudo-random numbers, fast digital counters, pseudo-noise sequences and whitening sequences. LFSR's can be realised both using hardware and software. When it comes to hardware implementation, MOS current mode logic (MCML) method can be used for designing the LFSR. There are lots of drawbacks with the traditional MCML method including the static power dissipation, more power consumption at low frequencies as compared with CMOS circuits, inappropriate for large systems involving power-down modes and it's not a cost effective solution either. To overcome these issues and to achieve the high speed characteristics of MCML, we present the modified dynamic current mode logic and is a good solution for battery powered systems and portable solutions. Our simulation results also confirm the same where a 16 bit adder circuit fabricated using CMOS technology has only a delay of 1.22 ns and dissipates 19.0 mW at 400 MHz. [ABSTRACT FROM AUTHOR]

A new technique for progressive visual secret sharing (PVSS) with adaptive priority weight is proposed in this paper. This approach employs the bitwise and eXclusive-OR (XOR) based approaches for generating a set of shared images from a single secret image. It effectively overcomes the former scheme limitation on dealing with an odd number of stacked or collected shared images in the recovery process. The presented technique works well when the number of stacked shared images is odd or even. As documented in experimental results, the proposed method offers good results over binary, grayscale, and color images with a perfectly reconstructed secret image. In addition, the performance of the proposed method is also supported with theoretical analysis showing its lossless ability to recover the secret image. However, it can be considered as a strong substitutive candidate for implementing a PVSS system.