Asynchronous Single Flux Quantum Logic Gates Using Self-Clocking

We propose an asynchronous single flux quantum (SFQ) logic gate composed of a conventional clocked logic gate and an input signal merger that generates a self-clock for the clocked logic gate. By using this self-clocking, we can design any 0-preserving logic gate, including exclusive OR (XOR). The proposed asynchronous SFQ logic gates have adjustable allowable input skew by varying the delay between the merger and internal clock input for the clocked logic gate. We design and evaluate the asynchronous AND, OR, and XOR gates that have an allowable input skew of approximately 8 ps assuming the use of the 10 kA/cm 2 Nb fabrication process using the proposed design method. We experimentally confirm the correct operation of the asynchronous SFQ XOR gate. We design a completely asynchronous 4-bit-input carry-lookahead adder (CLA) using the designed asynchronous gates. We found that the circuit area and number of Josephson junctions required to design a 4-bit-input CLA can be reduced by > 50% compared to that of the synchronous concurrent-flow 4-bit-input CLA without deterioration of the throughput.