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Epitaxial and random-oriented Pb(Zr,Ti)O 3 (PZT) films were fabricated at 450-550°C on SrRuO 3 (SRO)/SrTiO 3 /Si and SRO/amorphous Ti-Al layer-Si substrates, respectively, using a modified sol-gel process. For comparison, polycrystalline PZT films were also prepared on Pt-Si substrates using the same method. Thermogravimetric and differential thermal analysis (TG-DTA) of the modified sol-gel solution indicated that the solution began crystallization below 400°C. Both SRO/epitaxial PZT/SRO and SRO/random-oriented PZT/SRO capacitors processed at the same temperature had similar polarization values, and all the SRO/PZT/SRO capacitors processed at 450-550°C exhibited the favorable electrical characteristics including high polarization, high resistivity, small pulse width dependence, and good fatigue endurance. While the Pt/PZT/Pt capacitors processed at 450°C showed considerably low polarization compared to the SRO/PZT/SRO capacitors processed at the same temperature. High-quality SRO/PZT/SRO capacitors processed at low temperature have a bright prospect of fabrication of potential Si devices integrated PZT capacitors without thermal degradation. [ABSTRACT FROM AUTHOR]

The thermal stability of amorphous LaScO3 thin films deposited by molecular-beam deposition directly on (001) Si was investigated by high-resolution transmission electron microscopy (HRTEM), transmission infrared absorption spectroscopy (IRAS), and x-ray diffraction (XRD). IRAS indicated that the as-deposited films contained <0.1 Å of SiO2 at the interface between LaScO3 and silicon. XRD studies showed that the films remained amorphous after annealing in N2 at 700 °C, although HRTEM showed structural order on an ∼1 nm length scale even in the as-deposited films. By 800 °C, the LaScO3 had started to crystallize and formed a ∼5 nm thick Sc-deficient interlayer between it and silicon. [ABSTRACT FROM AUTHOR]

BiFeO3 was studied as an alternative environmentally clean ferro/piezoelectric material. 200-nm-thick BiFeO3 films were grown on Si substrates with SrTiO3 as a template layer and SrRuO3 as bottom electrode. X-ray and transmission electron microscopy studies confirmed the epitaxial growth of the films. The spontaneous polarization of the films was ∼45 μC/cm2. Retention measurement up to several days showed no decay of polarization. A piezoelectric coefficient (d33) of ∼60 pm/V was observed, which is promising for applications in micro-electro-mechanical systems and actuators. [ABSTRACT FROM AUTHOR]

Single-walled carbon nanotubes (SWNTs) have been grown via chemical vapor deposition on high-κ dielectric SrTiO[sub 3]/Si substrates, and high-performance semiconducting SWNT field-effect transistors have been fabricated using the thin SrTiO[sub 3] as gate dielectric and Si as gate electrode. The transconductance per channel width is 8900 μS/μm. The high transconductance cannot be explained by the increased gate capacitance; it is proposed that the increased electric field at the nanotube–electrode interface due to the high-κ SrTiO[sub 3] decreases or eliminates the nanotube-electrode Schottky barrier. © 2004 American Institute of Physics. [ABSTRACT FROM AUTHOR]

We report on the sol-gel deposition and characterization of high-quality, epitaxial films of PbZr[sub .52]Ti[sub .48]O[sub 3] (PZT) on (001)Si substrates, with a thickness range of 400 Å to 1 µm. The epitaxial growth of PZT on (001)Si is achieved using a thin template layer of SrTiO[sub 3], grown by molecular-beam epitaxy. The sol-gel PZT films have a typical surface roughness of 5 Å and exhibit well defined reflective high-energy electron diffraction patterns characteristic of smooth, epitaxial films. Using high-resolution transmission electron microscopy and double-crystal x-ray diffraction, we find that the PZT films are oriented with the c axis normal to the (001)Si plane and with the a axis lying along 〈110〉Si direction. Finally, we measure the electromechanical coupling coefficients and the surface acoustic wave velocities for our films as a function of thickness and compare our experimental data to previously published theoretical values for this system. [ABSTRACT FROM AUTHOR]

In this letter, we report on the integration of epitaxial ferroelectric Pb(Zr, Ti)O[sub 3] (PZT) thin films on Si [100] substrates using a SrTiO[sub 3] (STO) template layer and a conducting perovskite (La[sub 0.5]Sr[sub 0.5])CoO[sub 3] electrode. X-ray diffraction studies reveal both in-plane and out-of-plane alignment of the heterostructure. The epitaxial films show extremely high remnant polarization as well as piezoelectric d[sub 33] coefficients compared to textured and untextured polycrystalline films. [ABSTRACT FROM AUTHOR]

A silicon surface covered with ∼150 Å of strontium titanium oxide was exposed to both atomic and molecular hydrogen at temperatures between 20 and 300 °C. A rf probe was used to continuously monitor changes in charge-carrier recombination centers at the SrTiO[sub 3]/Si interface by following the steady-state photogenerated carrier concentration in the silicon. Independent passivation of interfacial defects was observed by both atomic and molecular hydrogen. © 2002 American Institute of Physics. [ABSTRACT FROM AUTHOR]

We have used photoemission methods to directly measure the valence and conduction band offsets at SrTiO[sub 3]/Si(001) interfaces, as prepared by molecular-beam epitaxy. Within experimental error, the measured values are the same for growth on n- and p-Si, with the entire band discontinuity occurring at the valence band edge. In addition, band bending is much larger at the p-Si heterojunction than at the n-type heterojunction. Previously published threshold voltage behavior for these interfaces can now be understood in light of the present results. © 2000 American Institute of Physics. [ABSTRACT FROM AUTHOR]

SrTiO[sub 3] has been grown epitaxially by molecular beam epitaxy on Si. The capacitance of this 110 Å dielectric film is electrically equivalent to less than 10 Å of SiO[sub 2]. This structure has been used to make capacitors and metal oxide semiconductor field effect transistors. The interface trap density between the SrTiO[sub 3] and the Si is 6.4x10[sup 10] states/cm[sup 2] eV and the inversion layer mobility is 221 and 62 cm2/V s for n- and p-channel devices, respectively. The gate leakage in these devices is two orders of magnitude smaller than a similar SiO[sub 2] gate dielectric field effect transistor. © 2000 American Institute of Physics. [ABSTRACT FROM AUTHOR]