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This paper presents a new biophotonic application for large-area, high-resolution, flexible organic light-emitting diode (OLED) display technology currently used to manufacture low-cost color flexible displays on plastic substrates. The new concept uses a fully addressable high resolution flexible OLED pixel array on a thin, mechanically compliant biocompatible plastic substrate to selectively stimulate and/or silence small groups of neurons on either the cortical surface or, alternatively, within the deep brain. Optical measurements from a 455 nm blue flexible OLED test structure demonstrated the ability to emit 1 ${\hbox{mW/mm}}^{2}$ of instantaneous light intensity using a 13 V, 20 Hz pulse, which meets the minimum reported intensity at $\sim$ 450 nm to induce optical stimulation in genetically modified neural tissue. Biocompatibility was successfully demonstrated by the ability to grow human epithelial cells on the surface of a full TFT process flow plastic flexible display substrate. Additionally, a new active matrix array display architecture was designed to support pulsed mode OLED operation. These preliminary results demonstrate the initial viability of extending flexible plastic substrate OLED display technology to the development of large-area, high-resolution emissive active matrix arrays for chronic optogenetic applications.

In this paper we describe solutions to effectively address critical challenges in direct fabrication of amorphous silicon thin film transistor (TFTs) arrays for active matrix flexible displays. For both metal foil and plastic flexible substrates a manufacturable handling protocol in automated display-scale equipment is required. We have successfully demonstrated a temporary bonding protocol that required development of new enabling materials, tools and processes. For metal foil substrates, the principal challenges are planarization and electrical isolation, and management of stress (CTE mismatch) during TFT fabrication. For plastic substrates, the principal challenges are dimensional instability management in conjunction with manufacturing-ready temporary adhesives. Solutions required a systems-level approach to address the challenges of the substrates and their handling simultaneously.

This letter describes a method to identify the channel region of hydrogenated amorphous silicon thin film transistors (a-Si:H TFTs) in which threshold voltage(Vth) degradation occurs. The TFTs are subjected to gate bias stress under different operating conditions. Asymmetry in the measured TFT drain current in the forward direction (same source and drain during stress and measurement) and reverse direction (interchanging the source and drain terminals) shows localization of the gate-voltage dependent Vth shift mechanism. Based on the observations, a charge-based expression for Vth shift is derived.

A low temperature amorphous silicon (a-Si) thin film transistor (TFT) and amorphous silicon PIN photodiode technology for flexible passive pixel detector arrays has been developed using active matrix display technology. The flexible detector arrays can be conformed to non-planar surfaces with the potential to detect x-rays or other radiation with an appropriate conversion layer. The thin, lightweight, and robust backplanes may enable the use of highly portable x-ray detectors for use in the battlefield or in remote locations. We have fabricated detector arrays up to 200 millimeters along the diagonal on a Gen II (370 mm x 470 mm rectangular substrate) using plasma enhanced chemical vapor deposition (PECVD) a-Si as the active layer and PECVD silicon nitride (SiN) as the gate dielectric and passivation. The a-Si based TFTs exhibited an effective saturation mobility of 0.7 cm2/V-s, which is adequate for most sensing applications. The PIN diode material was fabricated using a low stress amorphous silicon (a-Si) PECVD process. The PIN diode dark current was 1.7 pA/mm2, the diode ideality factor was 1.36, and the diode fill factor was 0.73. We report on the critical steps in the evolution of the backplane process from qualification of the low temperature (180°C) TFT and PIN diode process on the 150 mm pilot line, the transfer of the process to flexible plastic substrates, and finally a discussion and demonstration of the scale-up to the Gen II (370 x 470 mm) panel scale pilot line.

A low temperature amorphous zinc indium oxide (ZIO) thin film transistor (TFT) backplane technology for high information content flexible organic light emitting diode (OLED) displays has been developed. We have fabricated 4.1-in. diagonal OLED backplanes on the Flexible Display Center’s six-inch wafer-scale pilot line using ZIO as the active layer. The ZIO based TFTs exhibited an effective saturation mobility of 18.6 cm2/V-s and a threshold voltage shift of 2.2 Volts or less under positive and negative gate bias DC stress for 10000 seconds. We report on the critical steps in the evolution of the backplane process: the qualification of the low temperature (200°C) ZIO process, the stability of the devices under forward and reverse bias stress, the transfer of the process to flexible plastic substrates, and the fabrication of white organic light emitting diode (OLED) displays.

This paper reviews amorphous silicon thin-film-transistor (TFT) degradation with electrical stress, examining the implications for various types of circuitry. Experimental measurements on active-matrix backplanes, integrated a-Si:H column drivers, and a-Si:H digital circuitry are performed. Circuit modeling that enables the prediction of complex-circuit degradation is described. The similarity of degradation in amorphous silicon to negative bias temperature instability in crystalline PMOS FETs is discussed as well as approaches in reducing the TFT degradation effects. Experimental electrical-stress-induced degradation results in controlled humidity environments are also presented.

Amorphous silicon thin film transistors degrade with electrical stress. In particular, the threshold voltage increases significantly with positive gate voltages. The characteristics and mechanisms of the degradation are reviewed. The implications for various types of circuitry including active matrix backplanes, integrated drivers and general purpose digital circuitry are examined. A circuit modeling tool that enables the prediction of complex circuit degradation is presented. Finally, the similarity of degradation in amorphous silicon to negative bias temperature instability in crystalline PMOS is discussed along with potential approaches to reducing the degradation effects.

Principal challenges to direct fabrication of high performance a-Si:H transistor arrays on flexible substrates include automated handling through bonding-debonding processes, substrate-compatible low temperature fabrication processes, management of dimensional instability of plastic substrates, and planarization and management of CTE mismatch for stainless steel foils. In collaboration with our industrial and academic partners, we have developed viable solutions to address these challenges, as described in this paper.

The U.S. Army, Arizona State University (ASU) and commercial industry have joined forces to create the Flexible Display Center (FDC) at Arizona State University, a large-scale collaborative venture designed to rapidly advance flexible display technology to the brink of commercialization. The Center has completed its startup phase and is now engaged in an intensive and aggressive applied research and development program that will produce high quality, high performance active matrix reflective and emissive flexible display technology demonstrators (TDs). Electrophoretic ink and cholesteric liquid crystals have been selected as Center reflective imaging layer technologies; these technologies are attractive because they are fully reflective and bistable (extremely low power) and because the materials are environmentally robust and intrinsically rugged. Organic light emitting devices (OLEDs) have been chosen as the emissive imaging layer technology. These three electro-optic subsystems will be integrated with a flexible a-Si thin film transistor active matrix backplane platform. We have created the integrated design, backplane fabrication, display assembly, test and evaluation capability to enable rapid cycles of learning and technology development. Backplane fabrication is currently accomplished on a 6” wafer scale pilot line linked to a Manufacturing Execution System and supported by a comprehensive suite of in-fab metrology tools. We are currently installing a GEN II pilot line, with qualified operation slated for 2006. This line will be used to demonstrate process and display form factor capability, while providing high yield low volume manufacturing of pilot-scale levels of technology demonstrators for the Army and our commercial partners.

The authors report on the angle resolved light scattering characteristics of individual polystyrene spheres on three silicon surfaces. A He-Ne laser (632.8 nm) focused to a 15 micrometers 1/e2 diameter was employed to illuminate 0.804 micrometers diameter spheres on optically smooth ((sigma) >= (lambda) ) silicon surfaces: monocrystalline silicon (bare silicon), polycrystalline silicon (polysilicon), and roughened silicon ('black silicon'). These surfaces provided a roughness spectrum ranging between the smooth, virtually featureless surface of the bare silicon to one of dense, very coarse needle- like features on the black silicon. Scattering was measured as a function of incident beam polarization for incident angles of 30, 45, and 75.3 degrees (Brewster's angle). Experimental measurements show that the beam incident angle and polarization are important factors controlling substrate background scatter. The substrate influences sphere detectability in two ways: first, by directly scattering incident radiation into the detector and second, by reflecting a portion of the forward scattered light originating from the sphere. The results obtained are qualitatively explained with reference to the silicon surface reflectance which varies significantly as beam incident angle and polarization are changed. As surface roughness approached a value comparable to the sphere size, detectability diminished; that is, the measured cross sections were lower under these conditions. Surface roughness not only added to the background signal, but also reduced the amount of energy scattered by the sphere reaching the detector. A modification to Lorenz-Mie theory is introduced to explain the experimental findings. The approach taken is to calculate the scattering components for a sphere in free space, then attenuate those components which are reflected from the substrate into the detector. The computation includes the variation in substrate reflectivity as the ray incident angle and polarization change. The assumptions and validity of this approach are discussed, as well as future possible improvements to the model.

In this work we report on the angle resolved light scattering characteristics of individual polystyrene spheres on silicon surfaces. A He-Ne laser (632.8 nm) focused to a 15 μm 1/e2 diameter was employed to illuminate 4.10 and 0.804 μm. diameter spheres on optically smooth (σ«λ) silicon. Scattering was measured as a function of incident beam polarization for incident angles of 30, 45, and 75.3 degrees (Brewster’s Angle). A ring/wedge photodetector array centered on the specular beam was employed for the scattering measurements. The detector intercepted light scattered up to 45 degrees from the specular beam. The results obtained are qualitatively explained with reference to the silicon surface reflectance which varies significantly as beam incident angle and polarization are changed. Conditions associated with high surface reflectance result in larger values for sphere scattering cross section. We propose that the scattering measurements can be modeled in terms of a first order theoretical model developed previously by one of the authors (Hirleman). Initial results show that the theory is useful for understanding trends and predicts the correct order of magnitude for the scattering cross section. Possible improvements to the model are discussed.

— A novel approach of modeling a-Si:H TFTs with the industry-standard BSIM3 compact model is presented. The described approach defines the a-Si:H TFT drain current and terminal charges as explicit functions of terminal voltages using a minimum set of BSIM3 parameters. The set of BSIM3 parameters is chosen based on the electrical and physical characteristics of the a-Si:H TFT and their values extracted from measured data. By using the selected BSIM3 model parameters, the a-Si:H TFT is simulated inside SPICE to fit the simulated I-V and C-V curves with the measured results. Finally, the extracted BSIM3 model is validated by simulating the kickback voltage effect in an AMLCD pixel array.

A low temperature, 180 °C, amorphous Si (a-Si:H) process on bonded stainless steel substrates is discussed and a 3.8-inch QVGA active matrix (AM) electrophoretic display as well as a 64×64 electrophoretic display with integrated column drivers are demonstrated. The n-channel thin-film transistors (TFTs) exhibited saturation mobilities of 0.7 cm2/V-sec, median drive currents of 26.2 μA and low defectivity.

— A low-temperature amorphous-silicon (a-Si:H) thin-film-transistor (TFT) backplane technology for high-information-content flexible displays has been developed. Backplanes were integrated with frontplane technologies to produce high-performance active-matrix reflective electrophoretic ink, reflective cholesteric liquid crystal and emissive OLED flexible-display technology demonstrators (TDs). Backplanes up to 4 in. on the diagonal have been fabricated on a 6-in. wafer-scale pilot line. The critical steps in the evolution of backplane technology, from qualification of baseline low-temperature (180°C) a-Si:H process on the 6-in. line with rigid substrates, to transferring the process to flexible plastic and flexible stainless-steel substrates, to form factor scale-up of the TFT arrays, and finally manufacturing scale-up to a Gen 2 (370 × 470 mm) display-scale pilot line, will be reviewed.

We report angle resolved scattering characteristics of individual submicrometer polystyrene spheres on silicon and on a 91.5 nm thick film of oxide on silicon. Both these surfaces are considered optically smooth because the root mean square (rms) vertical roughness ? is much less than the wavelength ? (???). Scattering was measured as a function of polarization using a He-Ne and argon laser at varying degrees of incident angle. The experimental results are compared with a semi-analytical model of sphere/surface light scattering and a finiteelement time-domain electromagnetics code used in conjunction with a far-field extrapolator called EXTRMAP. The scattering measurements showed good to excellent agreement with both models. The semianalytical model could be improved by fully accounting for standing wave effects, a phenomenon the finite-element time-domain model inherently includes. The results are qualitatively explained with reference to both standing wave phenomena and the silicon surface reflectance, which varies significantly as the beam incident angle and polarization are changed.

Optical-scatter measurements from polysilicon and aluminum surfaces were performed by using 632.8-nm illumination at 45 deg and 488-nm illumination at 76.8 deg. Scatter was recorded up to 60 deg from the specular beam by using a concentric ring photodetector. The results are compared with surface statistics derived from atomic force microscopy. Quantitative predictions of the scatter were derived from power spectral density curves and angle-resolved-scattering theory. The agreement was fair for polysilicon samples with rms surface roughnesses of ~18 and 42 nm and aluminum with 17-nm rms roughness but poor for other samples. The discrepancy is attributed primarily to internal scatter within the measuring instrument.

Properties of deep levels in vapor-deposited ZnSe on GaAs have been investigated using transient photocurrent and steady state photocapacitance measurements. A metal/insulator/semiconductor structure was used in the study in which ZnSe formed the insulator. A single dominant deep level in the ZnSe having an energy of E c − 1.2 eV was observed over the spectral region 0.5–3.0 eV. The photoionization cross section of the trap at 1.5 eV and 295 K is 7 x 10 16 cm 2 . Trap concentrations in the range 10 16 −10 17 cm −3 were measured in the as-grown material.

ZnSe/GaAs n-n heterojunctions were prepared by heteroepitaxial growth of ZnSe on GaAs from the vapor phase. The electrical properties of the heterojunctions were found to be strongly dependent on the ZnSe resistivity. Heterojunctions with semi-insulating (10 9 –10 11 Ω cm) ZnSe showed symmetric current density versus voltage ( J-V ) characteristics and a voltage-independent capacitance. Rectification was shown by n-n heterojunctions prepared with conductive (5–25 Ω cm) ZnSe. J-V and capacitance versus voltage measurements indicated that the n-n structure behaves like a lattice-matched Schottky barrier with a barrier height of 0.7 eV. These findings were compared with recent theoretical models of the electronic structure of the ZnSe/GaAs interface.