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Abstract In this work, we developed a novel inorganic-organic hybrid gate dielectric by combining zirconium and hafnium components to form zirconium hafnium oxide strongly linked with polymethyl methacrylate (ZrHfO 2 -PMMA) and deposited at low temperature (200 °C) by sol-gel method. The obtained 108 nm thick, high-quality hybrid gate dielectric showed an exceptionally low surface roughness (0.9-nm), a low leakage current density (7.7 × 10−6 A/cm2) and reasonable dielectric properties such as gate capacitance along with dielectric constant (77 nF/cm2 & 9.4 @1 kHz) respectively. To examine the ZrHfO 2 -PMMA hybrid dielectric electrical properties we constructed thin-film transistors (TFTs) with room temperature r.f sputtered n-type metal oxide semiconductors, a-IGZO and ZnO, as active channels. The bottom gate fabricated a-IGZO TFTs driving at as low as below 6 V, with extracted field effect mobility of 2.45 cm2/V. s, a low threshold voltage of 1.2 V with large ON/OFF current ratio 107 respectively. On the other hand, for comparison we employed ZnO TFTs by applying same hybrid dielectric system, the obtained parameters of bottom gate ZnO TFTs were good field effect saturation mobility of 12.8 cm2/V. s, threshold voltage of 1.8 V and ON/OFF current ratio of 103. Highlights • Novel ZrHfO 2 -PMMA hybrid gate dielectric layer by sol-gel process at low temperature (200 °C). • Cross-linked, homogeneous and highly transparent hybrid dielectric layers with amorphous nature and very low surface roughness. • Hybrid dielectric layers with low leakage current density (10−6 A/cm2), good capacitance (77 nF/cm2) and high dielectric constant (9.4). • IGZO-based TFTs with hybrid dielectric gate with mobility of 2.45 cm2/Vs, low threshold voltage of 1.2 V and large current ON/OFF ratio of 107. [ABSTRACT FROM AUTHOR]

Bottom-gated pentacene organic thin-film transistors with LaTiON gate dielectrics annealed at two different temperatures are fabricated on n+Si wafers. Although atomic-force microscopyresults indicate a smoother dielectric surface and larger pentacene grains for the sample annealed at 400 °C, this sample shows lower carrier mobility than the one annealed at 200 °C. Moreover, the crystallinity of the gate dielectrics is not a key factor in the degradation of the carrier mobility because both dielectrics remain amorphous according to TEM. However, the TEM results show that the sample annealed at 400 °C has a thicker dielectric/Si-gate interlayer. The resultant increase in gate electrode-to-dielectric distance weakens the gate screening of the remote phonon scattering, thereby degrading the mobility of the carriers in the pentacene channel. This effect can be further supported by two similar samples fabricated on n-Si wafers, in which the gate electrode with lower electron concentration has a reduced screening effect on the remote phonon scattering and results in a larger reduction in mobility for the 400 °C-annealed sample with thicker interlayer. [ABSTRACT FROM AUTHOR]

The electrical characteristics of amorphous indium-gallium-zinc oxide (a-IGZO) thin film transistors (TFTs) with an ultrathin nitrogenated a-IGZO (a-IGZO:N) layer embedded at the channel/gate dielectric interface are investigated under positive gate-bias stress temperature (PBST) and negative bias illumination stress (NBIS). The devices with a-IGZO:N layer show enhanced electrical stability, with significantly reduced threshold voltage shift. Meanwhile, it is found that the average effective energy barrier for the positive gate-bias stress process in the TFTs with a-IGZO:N layer increases, which causes fewer channel carriers trapped in the channel/gate dielectric interface or insulator. According to x-ray photoelectron spectroscopy analyses, the concentration of oxygen vacancies (OV) is reduced when nitrogen is incorporated into the a-IGZO films. Therefore, the improved electrical stability of the a-IGZO TFTs upon PBST and NBIS is attributed to the reduction of interface OV-related defects by nitrogen doping. [ABSTRACT FROM AUTHOR]

The channel temperature (Tch) of solution‐processed 6,13‐bis(triisopropylsilylethynyl)‐pentacene (TIPS pentacene) thin film transistors (TFTs) is closely monitored in real time during current–voltage (I–V) measurements carried out in a He exchange gas cryostat at various base temperatures (Tb) between 300 K and 20 K. This is done using a platinum (Pt) resistance temperature sensor embedded within the transistor channel. Under large gate (Vg) and source‐drain (Vds) voltage biases, an increase in Tch is observed, the magnitude of which depends on the thermal conductivity of the substrate. The increase in Tch is associated with a simultaneous increase in the transistor drain current (Id) and becomes particularly pronounced at cryogenic Tb. These experimental observations are rationalized using a 1D theoretical model and are attributed to current‐induced Joule heating. However, even though the heating of the channel unquestionably plays an important role, the corresponding amount of increase in Id at cryogenic Tb and large voltage biases cannot be fully accounted for unless at low temperatures μTIPS is enhanced in the presence of strong electrical fields. Therefore it is concluded that the I–V characteristics of TIPS pentacene TFTs at low Tb and large voltage biases are a result of a complex interplay between current‐induced Joule heating and electrical field effects. [ABSTRACT FROM AUTHOR]

The temperature dependence in the typical temperature operating range from 300 K up to 370 K of the electrical characteristics of IGZO TFTs fabricated at temperatures not exceeding 200 °C is presented and modeled. It is seen that up to T = 330 K, the transfer curves show a parallel shift toward more negative voltages. In both subthreshold and above threshold regimes, the drain current shows Arrhenius-type dependence. In the latter case, for low temperatures, the activation energy is around 0.35 eV for V GS = 10 V, reducing as V GS is increased. The observed behavior is consistent with having the VRH transport mechanism as the predominant one in conduction. [ABSTRACT FROM AUTHOR]

In this paper, the electrical properties of top-gated thin-film transistors with low-cost chemical bath deposition (CBD) of ZnO as active material and a high- k rare-earth oxide La2O3 as gate dielectric have been reported. The source-drain and gate electrodes and dielectric layers are fabricated by thermal evaporation techniques in high vacuum of the order of 10−6 Torr in a coplanar electrode structure. The channel length of the TFT is of 50 μm. The fabricated TFTs are annealed at 500 °C in air. The TFTs exhibit a field effect mobility 0.58 (cm2 V−1 s−1). Use of a high dielectric constant (high- k) gate insulator reduces the threshold voltage and subthreshold swing of the TFTs. The TFTs exhibit a low threshold voltage of 4 V. The calculated values of gain-bandwidth product and subthreshold swing are also evaluated and presented. The ON/OFF ratio of the TFT is found to be 106. [ABSTRACT FROM AUTHOR]

Hf–Sn–Zn–O (HTZO) thin films were prepared on SiO 2 /SiN x substrates at room temperature by the direct current (DC) magnetron sputtering of Hf-doped Sn–Zn–O targets. The characteristics of films with different amounts of Hf were analyzed. Amorphous HTZO films were obtained by increasing the Hf content, while polycrystalline films have not shown with Hf doping. With the proper Hf concentration in the HTZO films (∼2.0 atomic % Hf/(Hf + Sn + Zn + O)), HTZO films demonstrated good performance as an oxide semiconductor channel material in thin film transistors (TFTs) with a field effect mobility (μ FE ) of 10.9 cm 2 V −1 s −1 , an on/off current ratio of 10 9 , and a subthreshold voltage swing of 0.71 V/decade. [ABSTRACT FROM AUTHOR]

In this paper, NH3 plasma directly applied to the surface of poly-Si channel is studied for the development of high-performance low-temperature polycrystalline-silicon thin-film transistors (LTPS-TFTs) with HfO2 high- \kappa gate dielectric. The reduction of threshold voltage from 1.52 to 0.62 V, the decrease of subthreshold swing from 227 to 151 mV/decade, and the enhancement of field effect mobility \mu _{\mathrm {FE}} from 31 to 65 cm ^{\mathrm {\mathbf {2}}}$ /Vs are observed after NH3 plasma surface treatment. It can be attributed to the NH3 plasma surface treatment enabling defect passivation and plasma-induced interfacial layer (PIL) growth. To decouple the impacts of defect passivation and PIL growth, the device without PIL is also fabricated. This paper demonstrates the important impacts of NH3 plasma surface treatment on the improvement of electrical characteristics of LTPS-TFTs. [ABSTRACT FROM PUBLISHER]

In this study, we evaluated the effects of microwave irradiation (MWI) post-deposition-annealing (PDA) treatment on the gate bias stress instability of amorphous indium-gallium-zinc oxide thinfilm transistors (a-IGZO TFTs) and compared the results with a conventional thermal annealing PDA treatment. The MWI-PDA-treated a-IGZO TFTs exhibited enhanced electrical performance as well as improved long-term stability with increasing microwave power. The positive turn-on voltage shift (ΔVON) as a function of stress time with positive bias and varying temperature was precisely modeled on a stretched-exponential equation, suggesting that charge trapping is a dominant mechanism in the instability of MWI-PDA-treated a-IGZO TFTs. The characteristic trapping time and average effective barrier height for electron transport indicate that the MWI-PDA treatment effectively reduces the defects in a-IGZO TFTs, resulting in a superior resistance against gate bias stress. [ABSTRACT FROM AUTHOR]

In this work, top-gate thin film transistor (TFT) with ZnO doped nitrogen (ZnO:N) channel fabricated by room temperature rf magnetron sputtering is demonstrated. ZnO:N film is obtained by introducing N2 ambient when sputtering ZnO. The crystallization of ZnO:N is better compared to ZnO film. The test results indicate that the ZnO:N could improve the electrical characteristics as an active channel layer for a TFT device. This in-process doping method may be a valuable technique for the fabrication of the practical and stable TFT devices. [ABSTRACT FROM AUTHOR]

This letter investigates the degradation behavior under hot-carrier stress in InGaZnO thin film transistors with I- and U-shaped asymmetric electrodes. After hot-carrier stress, a serious Vt shift, as well as on-current and subthreshold swing degradations are observed in Id-Vg transfer curve under reverse mode. Moreover, it is found that the Vt instability is caused by hot-electron injection near the drain side, and this phenomenon which is verified by C-V measurement. Furthermore, the location of trapped hot-electron is estimated from the two-stage rise in the gate-to-drain/gate-to-source capacitance curves and then verified by the simulation tool. [ABSTRACT FROM AUTHOR]

Indium nitride (InN) is potentially suitable for the fabrication of high performance thin-film transistors (TFTs) because of its high electron mobility and peak electron velocity. However, InN is usually grown using a high temperature growth process, which is incompatible with large-area and lightweight TFT substrates. In this study, we report on the room temperature growth of InN films on flexible polyimide sheets using pulsed sputtering deposition. In addition, we report on the fabrication of InN-based TFTs on flexible polyimide sheets and the operation of these devices. [ABSTRACT FROM AUTHOR]

The effect of lightly doped drain (LDD) doping concentration on the capacitance of a low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) is investigated. An anomalous gate-to-source capacitance phenomenon is observed: first, the capacitance decreases, and then it increases according to the gate voltage in the saturation region. This phenomenon is not affected by the subgap density-of-states and arises as the doping concentration of the LDD region is reduced. To investigate the effects of each source and the drain LDD dose on the gate-to-source capacitance, two-dimensional device simulations were conducted in which each dose of the source and drain LDD was changed individually. The reduced controllability of the source voltage to the gate charge in the saturation region due to the increased resistance of the source LDD region with low LDD dose is identified as the reason for this anomalous capacitance phenomenon. [ABSTRACT FROM AUTHOR]