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This paper presents a general methodology for compensating LDO regulators which exploits a current amplifier to effectively multiply the Miller capacitor. After a general theoretical analysis that takes into account both the external and internal loop stability, it is examined the feasibility of applying this kind of compensation in different LDO applications, showing the role of the design parameters and proposing a specific design procedure for each practical cases which differ in terms of load capacitance and the adoption of a decoupling voltage buffer. Simulations and experimental results which validate the methodology are also included.

In this communication, we propose a Miller compensation technique for low voltage LDO regulators which makes use of a current amplifier. The analysis shows how to design the compensation network when no voltage buffer is placed between the LDO error amplifier and power device and suggests a low supply voltage circuit topology that allows to compensate with a reasonably low integrated capacitance, to avoid oscillations due to the complex-conjugate poles at high output currents and to obtain acceptable under/overshoots during fast transient load variations. The designed LDO regulator can work with a supply voltage down to 1.2 V with a drop-out voltage of 200 mV at maximum load current of 100 mA; the integrated compensation capacitance is 25 pF, the load capacitor being equal to 1 muF. Simulations in good agreement with the theoretical results are also shown.

In this communication, we propose a compensation procedure for LDO regulators which exploits both a current/buffer amplifier Miller compensation and a standard Miller compensation. The analysis shows how to design the compensation network in order to guarantee the stability for all the loading conditions. The results are then used to design a LDO regulator which is stable for a load current range of 4 orders of magnitude (from 10 muA to 100 mA) without requiring an external off-chip capacitor with ESR. Simulations in good agreement with the theoretical results are also shown.

In this paper we studied program/erase characteristics by FN tunneling in Si nanocrystal memories. Starting from a very good agreement between experimental data and simulations in the case of a memory cell with a thin tunnel oxide, Silicon dots as medium for charge storage, and a CVD silicon dioxide used as control dielectric, we present estimated values of the charge trapping when a high-k material is present in the control dielectric. We then show preliminary results of nanocrystal memories with control dielectric containing high-k materials. ©2004 IEEE.