Search

Source degenerative feedback is extensively applied in the low-noise amplifier design. The beneficial effects of this technique are well established in the open literature. However, the designer is often left to trial-and-error or optimization procedures to identify the adequate amount of feedback when other linear requirements, such as signal matching, come into play. This issue is even more relevant in multistage designs. In this article, we present a synthesis procedure and the relevant design chart to identify the optimum feedback inductor value on all transistors of an $N$ -stage amplifier to obtain a perfect match at its external ports in conjunction with amplifier noise figure minimization and a specified gain requirement. It is shown that the method is applicable to arbitrary $N$ values although it becomes more elaborate for $N$ greater than 6. The method is deterministic as opposed to optimization or trial-and-error-based procedures. The design flow is illustrated at first through a four-stage design with ideal matching elements and subsequently validated by an monolithic microwave integrated circuit (MMIC) test vehicle designed and realized in the WIN foundry’s Gallium Arsenide PIH1-10 process. The measured performance of the test vehicle is NF = 1.9 dB, 26 dB gain, typical I/O return loss of 15 dB in the 26.5–29.5-GHz bandwidth, and practically ideal behavior at the design frequency of 28 GHz.

A comparative evaluation is provided in this paper regarding two design approaches for Ka-band Gallium Nitride Power Amplifiers. The first approach uses the standard electrical models provided by the foundry, while the alternative approach uses a custom model derived from in-house load-pull characterization. Both Power Amplifiers are designed to provide 30 dBm output power and 30% efficiency in the 31 - 35 GHz bandwidth. It is shown that the PA based on the custom model has a better PAE performance by about 4% and higher output power by 0.3 dB.

This work presents the design and characterization of an ultralow-power core chip for electronically scanned arrays at X-band, implemented in 0.25-/0.5-μm E-/D-mode gallium arsenide (GaAs) pHEMT technology. In particular, design details are given about the two core functional blocks embedded in the microwave monolithic integrated circuit (MMIC): a 12-bit phase and amplitude control circuit and an 18-bit serial-to-parallel (S2P) interface. The S2P interface was designed resorting to a custom symmetric device model, expressly conceived for the time-domain simulations required for digital circuits. Due to the adoption of a differential structure with resistive pull-ups, it achieves a state-of-the-art power consumption of 2.2 mW/bit and nearly 87% yield. The analog circuit includes a 6-bit phase shifter (PS) and a 6-bit attenuator. To mitigate risks, two different PS architectures have been developed and are compared in this work, discussing advantages and drawbacks of the different solutions. Since the two designs share the same target specifications, a truly fair comparison can be made not only in terms of performance but also concerning robustness and repeatability, thus providing useful guidelines for the selection of the most appropriate strategy. In particular, it is shown that one architecture outperforms the other by about 2 dB and 1.5° in terms of insertion loss and rms phase error, respectively.

This article addresses the classical problem of determining the extrinsic resistances ( $R_{G}$ , $R_{S}$ , and $R_{D}$ ) of field-effect transistors (FETs) and, in particular, of high-electron-mobility transistors (HEMTs). The presented approach relies on small-signal measurements of open-channel transistors, as often proposed both for traditional metal–semiconductor FETs (MESFETs) and HEMTs. Unlike what is common practice with HEMTs, the method proposed here does not oversimplify the model of the active channel. On the contrary, we retrieve from the literature a possible analytical model for the open-channel HEMT and use it to determine the triplet of extrinsic resistances without the need of stressing the gate junction with too high currents. Another result of the approach, valid both for MESFETs and HEMTs, is a deterministic way to remove the contribution of the gate junction from the small-signal parameters of the measured devices. All extractions process data that are available on suitable ranges in frequency or in bias voltage, without taking to the limit the sweep parameters or seeking specific resonances. Also, optimizations are only allowed to refine the nominal values, not as the main technique of extraction. These goals are achieved by setting up different subproblems in the form of overdetermined linear systems and then solving by pseudoinversion. The validity of the approach is demonstrated on the measurements of devices from advanced HEMT technologies realized by OMMIC, both GaAs-based (40-nm gate length) and GaN-based (100 and 60 nm).

In this letter, we present the design of a V- band low-noise amplifier for intersatellite crosslink receivers. The test vehicle, realized on industrial metamorphic gallium arsenide technology, operates from 57 to 66 GHz exhibiting 23-dB gain and an average 1.8-dB noise figure. Particular attention was devoted to the analysis and synthesis of an alternative bias injection topology to obtain a sharp gain roll-off at lower frequencies, thus avoiding the insertion, at system level, of an image-reject filter.

Here we report the case of successful immune tolerance induction in a living‐donor kidney transplant recipient remotely treated with autologous bone marrow‐derived mesenchymal stromal cells (MSC). This case report, which to the best of our knowledge is the first in the world in this setting, provides evidence that the modulation of the host immune system with MSC can enable the safe withdrawal of maintenance immunosuppressive drugs while preserving optimal long‐term kidney allograft function., This report provides the evidence that autologous BM‐MSC infusion induces a pro‐tolerogenic immune environment, thus allowing complete discontinuation of antirejection drugs in kidney transplantation

This paper is focused on the extraction of the noise parameters of a linear active device by exploiting both forward and reverse noise power measurements associated with different terminations. In order for load-pull measurements to yield a significant marginal improvement (as compared to forward measurements only) it is expected that the device under test should appreciably deviate from unidirectionality. For this reason, the source/load-pull technique is applied to frequencies at which the considered devices are still usable but their reverse noise factor exhibits a measurable dependence on the output terminations. Details on the test bench set up to the purpose, covering the 20–40 GHz frequency range, are provided. A characterization campaign on a 60 nm gate length, 4×35 µm GaN-on-Si HEMT fabricated by OMMIC is illustrated.

This letter presents an improved circuit topology to minimize the number of external control voltages that are required to set the state of an N-bit microwave digital attenuator. An alternative method to connect the control signal is proposed. Typically, the control signal is connected to the gate terminal of the field effect transistor while the source terminal is DC grounded. Here, the control signal is applied to the source terminal of the field effect transistor while the gate is connected to a fixed reference voltage. In this way, only one control voltage is necessary to set the state of single attenuator cell vs two control voltages required in the typical case. The proposed method becomes particularly beneficial as the number of bits increases (ie, >4). The topology has been validated through design, realization, and testing of a 5-bit Monolithic Microwave Integrated Circuit (MMIC) attenuator operating over the full C-band (4-8 GHz).

Motivated by the growing interest towards low-cost, restriction-free MMIC processes suitable for multi-function, possibly space-qualified applications, this contribution reports the extraction of reliable linear models for two advanced GaN-on-Si HEMT technologies, namely OMMIC&rsquo, s D01GH (100 nm gate length) and D006GH (60 nm gate length). This objective is pursued by means of both classical and more novel approaches. In particular, the latter include a nondestructive method for determining the extrinsic resistances and an optimizaion-based approach to extracting the remaining parasitic elements: these support standard DC and RF measurements in order to obtain a scalable, bias-dependent equivalent-circuit model capturing the small-signal behavior of the two processes. As to the noise model, this is extracted by applying the well known noise-temperature approach to noise figure measurements performed in two different frequency ranges: a lower band, where a standard Y-factor test bench is used, and an upper band, where a custom cold-source test bench is set up and described in great detail. At 5 V drain-source voltage, minimum noise figures as low as 1.5 dB and 1.1 dB at 40 GHz have been extracted for the considered 100 nm and 60 nm HEMTs, respectively: this testifies the maturity of both processes and the effectiveness of the gate length reduction. The characterization and modeling campaign, here presented for the first time, has been repeatedly validated by published designs, a couple of which are reviewed for the Reader&rsquo, s convenience.

The HLA-DPB1 locus has been demonstrated to have a significant role on patients' outcome after allogeneic HSCT, and the so-called T-cell epitope (TCE) algorithm has been incorporated in international guidelines for the selection of unrelated donors. The purpose of the present study is to measure, through a national survey conducted on behalf of the Associazione Italiana di Immunogenetica e Biologia dei Trapianti (AIBT), the extent of awareness and use of HLA-DPB1 TCE-based algorithms during the donor search. 89% of the HLA laboratories answered to a short questionnaire and the results showed a progressive increase of the laboratories typing DPB1 in patients and their potential donors during the search (from 44% to 79% during the 2010-2019 period) as well as the application of a TCE-based algorithm for the donor choice whenever possible (from 24% to 65% during the same period). The DP-permissiveness status is detailed in the official HLA typing report by 12%, 32% and 50% of laboratories in 2010, 2015 and 2019, respectively. The present data indicate an encouraging raise in the awareness of the HLA-DPB1 role in unrelated donor selection; noteworthy, mentioning the TCE-based permissiveness status in the HLA typing report of each potential unrelated donor represents a notable mean to raise awareness among transplant physicians and to support them in their task of choosing the best donor. Nonetheless, despite the compelling evidence of the predictive ability of TCE-based algorithms, further efforts are still needed to extend its application to all transplant centers in Italy.

In this work, a Ka-Band MMIC LNA designed with two different gate length GaN-on-Si devices is shown. Measurements show a gain higher than 29dB, 2.1dB average NF in the 34÷37.5GHz design band and a 1dBcp around 23-24dBm in the 35÷36.5GHz target band, showing a good suitability to highgain, low-noise and medium-power requests. Comparison with GaN-on-SiC-based similar works confirms the feasibility of the adoption of GaN-on-Si technology for space-borne applications.

The stability analysis of nonlinear circuits is a central problem in the framework of microwave design, as applied to high-power amplifiers, oscillators, frequency dividers, and multipliers. However, reliable, user-friendly tools for the stability analysis of such components seem to be quite scarce, even within the very commercial suites for high-frequency circuit simulation. This contribution addresses the problem by generalizing Ohtomo’s test—a popular tool born in the context of linear circuits—to the nonlinear case. Specifically, the new technique allows to analyze the characteristic zeros of a linearized large-signal solution resulting from a harmonic-balance (HB) simulation. As well known, the location of these zeros with respect to the imaginary axis of the complex plane is critical in relation to the qualitative nature of the solution, i.e., to its stability. To the best of the authors’ knowledge, for the first time, a large-signal stability test based on the system determinant but not requiring direct access to the nonlinear elements is implemented completely within a commercial circuit simulator (i.e., without requiring an external mathematical environment for data postprocessing). Some limitations still present are discussed. The generalized Ohtomo test was validated against other methods and circuits from the literature.

This work is focused on the design of broadband amplifiers by exploiting dissipative reciprocal matching networks. Unlike the classical approach, which makes use of lossless reciprocal matching networks, there is no need to trade-off the gain flatness with the input/output matching levels. In this contribution the flat gain condition is obtained partially by exploiting the mismatch loss at a certain section and partially by leveraging on ohmic losses. In particular, two different matching schemes have been analytically studied. Taking advantage of the more promising scheme of the two presented, the design of a linear power amplifier operating over the 4–40 GHz decade, is illustrated. The amplifier showed measured input/output return loss better than 9/10 dB respectively, a gain of 8 ± 0.6 dB and an output power level of 25.5 ± 0.5 dBm at 1 dB compression point. Incidentally, unconditional stability is obtained without considering additional stabilization networks or components devoted to the purpose.

The first realizations of S-band hybrid amplifiers based on hydrogenated-diamond (H-diamond) FETs are reported. As test vehicles of the adopted H-diamond technology at microwave frequencies, two designs are proposed: one, oriented to low-noise amplification, the other, oriented to high-power operation. The two amplifying stages are so devised as to be cascaded into a two-stage amplifier. The activities performed, from the technological steps to characterization, modelling, design and realization are illustrated. Measured performance demonstrates, for the low-noise stage, a noise figure between 7 and 8 dB in the 2–2.5 GHz bandwidth, associated with a transducer gain between 5 and 8 dB. The OIP3 at 2 GHz is 21 dBm. As to the power-oriented stage, its transducer gain is 5–6 dB in the 2–2.5 GHz bandwidth. The 1-dB output compression point at 2 GHz is 20 dBm whereas the OIP3 is 33 dBm. Cascading the measured S-parameters of the two stages yields a transducer gain of 15 ± 1.2 dB in the 2–3 GHz bandwidth.

Design solutions and technology considerations of a 6–52 GHz cascode distributed amplifier are presented in this paper. The amplifier is designed in a Gallium Nitride on Silicon process with two different gate length transistors, namely 60 nm and 100 nm, connected in cascode configuration. The test vehicle, whose additional aim is to show the possibility to integrate transistors with different gate lengths onto the same chip, demonstrates 9 dB gain, 28 dBm saturated output power, 20% PAE and 37 dBm IP3, on average. Comparison with Gallium Nitride on Silicon Carbide based similar works reveals satisfactory performance obtained however on a cost effective and high volume production substrate.

In this paper, a Single-Chip Front-End (SCFE) operating in Ka-Band (35–36.5 GHz) is presented. Chip is designed exploiting a GaN-on-Si technology featured by 100nm gate length provided by OMMIC foundry. This MMIC integrates high-power, low-noise amplification functionalities enabled by a couple of synchronous Single-Pole Double-Throw (SPDT) switches, occupying a total surface of 4.7×3 mm2. Transmit-mode (Tx) performance present a 36 dBm output power, a Power Added Efficiency (PAE) higher than 25% and a 20dB power gain at 2 dB compression. Regarding the receiving-mode (Rx) performance, a sub-3.2 dB Noise Figure (NF) and a linear gain just below the 32 dB level is obtained, with a I/O matching better than 20 dB, as well.

In this paper a GaN-on-Si MMIC Low-Noise Amplifier (LNA) working in the Ka-band is shown. The chosen technology for the design is a 100 nm gate length HEMT provided by OMMIC foundry. Both small-signal and noise models had been previously extracted by the means of an extensive measurement campaign, and were then employed in the design of the presented LNA. The amplifier presents an average noise figure of 2.4 dB, a 30 dB average gain value, and input/output matching higher than 10 dB in the whole 34&ndash, 37.5 Ghz design band, while non-linear measurements testify a minimum output 1 dB compression point of 23 dBm in the specific 35&ndash, 36.5 GHz target band. This shows the suitability of the chosen technology for low-noise applications.

A MMIC demonstrator for RF phase and amplitude control with on board 18-bit serial to parallel conversion (Multi-Functional Chip) is presented. Thanks to an alternative digital building block topology, the DC power consumption of the digital serial to parallel converter is noteworthy: less than 43 mW (2 mW/bit). The main RF performances are 0° – 360° phase coverage and 0 dB – 31.5 dB attenuation setting, in the 7.6 GHz – 9.1 GHz operating bandwidth. The circuit, whose area is 6 mm2, is realised in an industrial and commercially available GaAs technology. This component can be used in active electronically scanned arrays for beam steering.

A theoretical analysis is carried out of the problem of checking the unconditional stability of a linear $N$ -port with arbitrary $N$ , explaining at length its inherent difficulties. To overcome the algebraic roadblock, an optimization-based method is proposed; the main novelty is that notwithstanding the use of optimization, the problem formulation is specifically chosen so as to guarantee convergence to the global minimum. In particular, recent advancements in the field of convex optimization, mostly unknown to the high-frequency engineering community, are exploited to that end. The result is a method suitable for checking the unconditional stability of linear $N$ -ports with $N$ up to 4. Higher numbers of ports, although allowed in principle, are not viable with the current combination of hardware resources and software implementation. Several examples of applications are provided, both purely illustrative and from actual circuit designs.

The feasibility of a W-band (81-86 GHz) downconverter for space-borne communications is verified in this paper through the design of a custom MMIC chip-set. The latter is composed of three functionalities: a low-noise amplifier (LNA), a sub-harmonically pumped mixer (SHM), and an active frequency doubler that provides the local oscillator (LO) pump to the mixer. The MMICs have been designed with OMMIC’s 70 nm and UMS’s 100nm GaAs technologies, in order to exploit the best-of-both technologies (low-noise and power-handling at millimetre-wave). The LNA features 23 dB gain and sub-2.5 dB Noise Figure in the whole operating band, while the mixer shows 13 dB conversion loss (CL). Finally, the active doubler provides > +10dBm pump at the necessary LO frequency.

In this paper, the feasibility of a V-band MMIC chipset is tested by the design of a Low-Noise Amplifier (LNA) operating in the 59-66 GHz frequency band and two Mixers exploiting two different topologies that convert signals from the 60-60.4 GHz band to 8-8.4 GHz band and vice versa. The MMICs have been designed exploiting OMMIC’s 70 nm and 130 nm GaAs technologies. LNA shows a 23 dB gain and a sub-2 dB Noise Figure in the whole operating band, while the two Mixers show a 11-12 dB conversion loss, along with LO isolation towards RF and IF port higher than 22 dB and a simulated Input 1 dB Compression Point of 10 dBm.

Design and performance of a gallium nitride (GaN)-on-Si mixer for the Ka -band satellite telecom applications are presented in this letter. GaN-on-Si offers the advantage of high-volume production even for millimeter-wave applications. A single-balanced architecture is selected as an optimum tradeoff between circuit complexity and rejection of local oscillator (LO) harmonics. An alternative circuit topology is adopted where the in-phase combiner and hybrid quadrature couplers, used to obtain the desired signal phasing at mixer output, are also employed as circuit elements to inject external bias voltages so to optimize the mixer’s conversions loss (CL). The mixer features 11-dB CL, 11- and 22-dBm P1dB and IIP3 respectively, in the 26–31-GHz bandwidth when driven by a 10-dBm LO level. Monolithic microwave integrated circuit area is less than 6 mm2.

This paper provides an assessment between two MMIC foundry processes for millimetre-wave high-performance receiver applications, namely, OMMIC’s 70 nm GaAs and 60 nm GaN-on-Si processes. To do so, a characterization and modelling campaign was carried out on transistors provided by OMMIC for the two processes, whose commercial names are D007IH (70 nm GaAs) and D006GH (60 nm GaN). The resulting models were employed to design several test vehicle Low-Noise Amplifiers (LNA) operating above 30 GHz. The GaAs LNAs have been manufactured and characterized, while the GaN-on-Si LNAs are being manufactured. The initial outcome of the assessment is that GaAs is still ahead if Noise Figure is the crucial and mandatory requirement. GaN-on-Si, on the other hand, proves to be a viable solution if a – slightly – higher Noise Figure is acceptable. Moreover, the benefits of GaN-on-Si, with respect to GaAs, are higher robustness, output power, linearity, and higher integration capability with CMOS technologies.

In this paper a MMIC Low-Noise Amplifier operating in Ka-band is presented. The chosen technology is a 100 nm GaN HEMT on a High Resistivity Silicon substrate. A fully deterministic approach based on constant mismatch circles has been used for the preliminary synthesis of matching networks. The designed four-stages LNA presents a 33 dB gain, Input/Output matching better than 21 dB and a Noise Figure of no more than 2.3 dB in the whole operating band, showing the suitability of the chosen technology to low-noise, high gain and linearity applications.

In this paper, a times four K- to W-Band frequency multiplier involved in the generation of a Local Oscillator signal is presented. The chosen technology for this design is the D01MH, a metamorphic GaAs mHEMT with a 0.13 µm channel length. The designed MMIC is expected to convert a 5 dBm, 23–24 GHz input signal into a 11 dBm, 92–96 GHz output signal. Simulations show an output power harmonic suppression over 50 dBc between the desired and unwanted ones. Input and Output matching respectively better than 13 and 16 dB is expected. The MMIC occupies an area of 3 × 2 mm2, and is currently being manufactured.

This paper presents the design and initial tests of a Gallium Nitride on Silicon (GaN/Si) Single-Pole Double-Throw (SPDT) switch for space-borne satellite observation payloads operating at Ka-band and more precisely around 36GHz. The SPDT is synthesized through a series FET configuration, with inductive resonators, and exhibits (typically) 1.1dB measured insertion loss and 22dB isolation over the 33–39GHz bandwidth. Expected non-linear performance is +39dBm IP1dB. Results and performance are in line with previously published results in open literature but are obtained on a relatively inexpensive and most of all easily accessible Silicon substrate that is known for its higher RF losses with respect to its Silicon-Carbide (SiC) counterpart. To the best of the Authors' knowledge this is one of the first GaN on Silicon SPDTs published in this operating frequency.

A novel technique for characterizing reciprocal three-port networks is proposed. The approach is an extension of the conventional unterminating method for characterizing two-port networks: on the one hand, the latter extracts the parameters of a (reciprocal) two-port network from one-port measurements, and on the other hand, the presented generalization extracts the parameters of a (reciprocal) three-port network from two-port measurements. The technique is believed of interest particularly for those which occasionally need to perform three-port vector-corrected measurements of three-port test-bench components such as baluns and directional couplers but do not have access to multiport equipment and software.

Low-noise amplifier (LNA) designers often struggle to simultaneously satisfy gain, noise, stability, and I/O matching requirements. In this article, a novel design technique, tailored for two-stage low-noise amplifiers, is presented. The proposed design method is completely deterministic and exploits inductive source degeneration to obtain a two-stage LNA featuring perfect input and output match together with low noise figure (NF) and a pre-determined gain, including stability analysis. A novel flowchart is provided together with the corresponding design chart that contains gain, matching, and stability information, therefore addressing all key figures-of-merit of a linear amplifier. The design chart is easily implementable in commercial Electronic Design Automation software, to aid designers in the difficult task of selecting the appropriate source degeneration inductor value. The noise performance, on the other hand, is the best possible since the matching networks are designed to provide the input of the two Field Effect Transistors with the optimum termination for noise. The design method is validated with two separate test vehicles operating respectively at Ka-band (26.5-31.5 GHz) and K-band (20.0-24.0 GHz). The realized Monolithic Microwave Integrated Circuits exhibit 18 dB gain for both versions, NF of 1.5 and 1.2 dB, respectively for the Ka-band and K-band version. Input and output matching are typically better than 12 and 15 dB.

A novel result is presented concerning the locus, on the source reflection coefficient plane, of the optimum tradeoff between noise factor and available gain. Although this locus has been discussed and exploited in previous contributions, here, it is shown in a simple manner that it must be an arc of a circumference with center $C_{\mathrm{ tc}}$ and radius $\rho _{\mathrm{ tc}}$ (tangency circle). A handy transformation (a reversible, conformal one) of two-port networks is adopted to study the problem in a simplified, yet general, representation. Properties of the tangency circle are observed in this “noise-centered” representation which are preserved under the conformal transformation, thus providing two equivalent, closed-form approaches to computing $C_{\mathrm{ tc}}$ and $\rho _{\mathrm{ tc}}$ . The second method presented lends itself to being easily implemented in commercial circuit simulators, thus serving as the basis of a simple design method for single-stage low-noise amplifiers.

In this contribution an integrated Single Chip Front-End (SCFE) for next generation Electronic Warfare T/R modules is presented. The proposed circuit relies on a concurrent design technique merging switches and HPA matching network. Realized MMIC features a 6.3×4.3mm2 outline operating in the 5.5-18 GHz band with a typical output power of 6W, an associated PAE of 10% and 3dB insertion loss in Rx mode.