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24 results on '"E. G. Ioannidis"'

1. Low frequency noise variability in ultra scaled FD-SOI n-MOSFETs: Dependence on gate bias, frequency and temperature

Author

Emmanuel Josse, Sebastien Haendler, Gerard Ghibaudo, C.A. Dimitriadis, Christoforos G. Theodorou, E. G. Ioannidis, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), STMicroelectronics [Crolles] (ST-CROLLES), Aristotle University of Thessaloniki, Department of Physics, and European Project: 325633,EC:FP7:SP1-JTI,ENIAC-2012-2,PLACES2BE(2012)

Subjects
Materials science, Noise variability, Infrasound, Gate dielectric, RTN, Silicon on insulator, 02 engineering and technology, Trapping, 01 natural sciences, Noise (electronics), Standard deviation, Low-frequency noise, 0103 physical sciences, Materials Chemistry, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Parametric statistics, 010302 applied physics, business.industry, Noise spectral density, Electrical engineering, 021001 nanoscience & nanotechnology, Condensed Matter Physics, Electronic, Optical and Magnetic Materials, FD-SOI MOSFETs, Optoelectronics, 0210 nano-technology, business
Abstract

International audience; In this paper, a parametric statistical analysis of the low-frequency noise (LFN) in very small area (W·L ≈ 10−3 μm2) 14 nm fully depleted silicon-on-insulator (FD-SOI) n-MOS devices is presented. It has been demonstrated that the LFN origin is due to carrier trapping/detrapping into gate dielectric traps near the interface and the mean noise level in such small area MOSFETs is well approached by the carrier number fluctuations model in all measurement conditions. The impact of gate voltage bias and temperature on the LFN variability, as well as the standard deviation dependence on frequency have been studied for the first time, focusing on their relation to the Random Telegraph Noise (RTN) effect and its characteristics.

Published
2016
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2. Improved analysis and modeling of low-frequency noise in nanoscale MOSFETs

Author

Gerard Ghibaudo, Charalabos A. Dimitriadis, J. Jomaah, R.A. Bianchi, E. G. Ioannidis, and Sebastien Haendler

Subjects
Electron mobility, Materials science, Scattering, Infrasound, Transistor, Shot noise, Condensed Matter Physics, Electronic, Optical and Magnetic Materials, law.invention, Computational physics, Square root, law, Materials Chemistry, Surface roughness, Electronic engineering, Flicker noise, Electrical and Electronic Engineering
Abstract

Extensive investigation of the low-frequency noise in n-channel and p-channel MOSFETs, with high-k gate stack and channel length varying from 1.8 μm down to 26.4 nm, has been carried out. The results demonstrate that the carrier number fluctuation with correlated mobility fluctuations describes accurately and continuously the 1/f noise for all operation regions, i.e. from weak to strong inversion and from linear to saturation. It has been found that the product of the Coulomb scattering coefficient and the effective carrier mobility α sc μ eff is constant over a wide range of the drain current due to the interplay of the Coulomb scattering coefficient αsc and the effective carrier mobility μeff variations. In addition, a non-linear increase in the square root of the input gate voltage noise with the gate voltage overdrive was observed explained by the surface roughness scattering. The overall results lead to an analytical expression for the 1/f noise model, enabling to predict the noise level of a transistor with any channel dimensions using its transfer characteristic. This finding makes the noise model suitable for circuit simulation tools.

Published
2012
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3. Impact of low‐frequency noise variability on statistical parameter extraction in ultra‐scaled CMOS devices

Author

Charalabos A. Dimitriadis, Christoforos G. Theodorou, E. G. Ioannidis, Gerard Ghibaudo, Sebastien Haendler, Aristotle University of Thessaloniki, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), STMicroelectronics [Crolles] (ST-CROLLES), European Project: 325633,EC:FP7:SP1-JTI,ENIAC-2012-2,PLACES2BE(2012), and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)

Subjects
010302 applied physics, Computer science, Infrasound, 020208 electrical & electronic engineering, Monte Carlo method, Statistical parameter, 02 engineering and technology, 01 natural sciences, Noise (electronics), symbols.namesake, CMOS, Gaussian noise, 0103 physical sciences, Log-normal distribution, Dispersion (optics), 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, symbols, Statistical dispersion, Statistical physics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Electrical and Electronic Engineering
Abstract

International audience; The impact on the extracted low-frequency noise (LFN) parameter values due to LFN variability in CMOS devices is investigated. First, it is demonstrated that the noise level dispersion follows a log normal statistical distribution. Then, based on this feature, it is explained why the mean values from the linear data are different from the mean values (or median values) calculated from the log noise data. Finally, the consequence of this finding in terms of LFN characterisation issues and Monte Carlo LFN variability circuit simulation is discussed.

Published
2014
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4. Analytical Compact Model for Lightly Doped Nanoscale Ultrathin-Body and Box SOI MOSFETs With Back-Gate Control

Author

Nicolas Planes, Christoforos G. Theodorou, T.A. Karatsori, Charalabos A. Dimitriadis, A. Tsormpatzoglou, Sebastien Haendler, Gerard Ghibaudo, E. G. Ioannidis, Aristotle University of Thessaloniki, Department of Physics, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), STMicroelectronics [Crolles] (ST-CROLLES), ARISTEIA II project, and Centre National de la Recherche Scientifique (CNRS)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Université Grenoble Alpes (UGA)

Subjects
Materials science, fully depleted silicon-on-insulator (FD-SOI) ultrathin-body and box (UTBB) MOSFETs, Channel length modulation, business.industry, Semiconductor device modeling, Silicon on insulator, Saturation velocity, Electronic, Optical and Magnetic Materials, Threshold voltage, Velocity overshoot, Logic gate, compact model, MOSFET, Electronic engineering, Optoelectronics, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, Back-gate control
Abstract

International audience; An analytical drain-current compact model for lightly doped short-channel ultrathin-body and box fully depleted silicon-on-insulator MOSFETs with back-gate control is presented. The model includes the effects of drain-induced barrier lowering, channel-length modulation, saturation velocity, mobility degradation, quantum confinement, velocity overshoot, and self-heating. The proposed model has been validated by comparing with the experimental transfer and output characteristics of devices with the channel lengths of 30 and 240 nm and with back bias varying from -3 to +3 V. The good accuracy of the model makes it suitable for implementation in circuit simulation tools.

Published
2015
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5. Full gate voltage range Lambert-function based methodology for FDSOI MOSFET parameter extraction

Author

T.A. Karatsori, Gerard Ghibaudo, Sebastien Haendler, E. G. Ioannidis, Charalabos A. Dimitriadis, Christoforos G. Theodorou, Emmanuel Josse, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), Aristotle University of Thessaloniki, Department of Physics, STMicroelectronics [Crolles] (ST-CROLLES), ARISTEIA II(Project 4154 of the GreekGeneral Secretariat for Research and Technology, co-funded by theEuropean Social Fund and national funds), European Project: 325633,EC:FP7:SP1-JTI,ENIAC-2012-2,PLACES2BE(2012), and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)

Subjects
Linear region, Engineering, Hardware_PERFORMANCEANDRELIABILITY, symbols.namesake, MOSFET, Robustness (computer science), Hardware_GENERAL, Lambert W function, Materials Chemistry, Electronic engineering, Hardware_INTEGRATEDCIRCUITS, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Drain current, Electrical parameter extraction, business.industry, Attenuation, Condensed Matter Physics, Gate voltage, Condensed Matter::Mesoscopic Systems and Quantum Hall Effect, FDSOI, Electronic, Optical and Magnetic Materials, Threshold voltage, symbols, Optoelectronics, business
Abstract

International audience; A new full gate voltage range methodology using a Lambert W function based inversion charge model, for extracting the electrical parameters in FDSOI nano-MOSFET devices, has been developed. Split capacitance–voltage measurements carried out on 14 nm technology FDSOI devices show that the inversion charge variation with gate voltage can be well described by a Lambert W function. Based on the drain current equation in the linear region including the inversion charge described by the Lambert function of gate voltage and the standard mobility equation enables five electrical MOSFET parameters to be extracted from experimental Id–Vg measurements (ideality factor, threshold voltage, low field mobility, first and second order mobility attenuation factors). The extracted parameters were compared with those extracted by the well-known Y-function in strong inversion region. The present methodology for extracting the electrical MOSFET parameters was verified over a wide range of channel lengths on nano-scale FDSOI devices, demonstrating its simplicity, accuracy and robustness.

Published
2015
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6. Dynamic variability in 14nm FD-SOI MOSFETs and transient simulation methodology

Author

Sebastien Haendler, Christoforos G. Theodorou, E. G. Ioannidis, Charalabos A. Dimitriadis, Gerard Ghibaudo, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), STMicroelectronics, Aristotle University of Thessaloniki, Department of Physics, Nano 2017, European Project: 325633,EC:FP7:SP1-JTI,ENIAC-2012-2,PLACES2BE(2012), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), and Centre National de la Recherche Scientifique (CNRS)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Université Grenoble Alpes (UGA)

Subjects
Engineering, business.industry, Cadence design suite, CMOS, Silicon on insulator, Low frequency, Condensed Matter Physics, Electronic, Optical and Magnetic Materials, Transient noise, Low-frequency noise, Rise time, MOSFET, Materials Chemistry, Electronic engineering, Hardware_INTEGRATEDCIRCUITS, Transient (oscillation), Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, Cadence, Simulation, Dynamic variability
Abstract

International audience; The impact of the dynamic variability due to low frequency and RTN fluctuations on single MOSFET operation from 14 nm FD-SOI technology is investigated for the first time. It is shown that the dynamic variability is enhanced as the rise time and the device area are reduced. Different simulation approaches were investigated to determine the best methodology for simulating the dynamic variability in Cadence circuit simulation tool. It is demonstrated that Monte-Carlo and periodic transient noise simulations are methodologies capable to reproduce accurately dynamic variability in Cadence.

Published
2015
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7. Full front and back gate voltage range method for the parameter extraction of advanced FDSOI CMOS devices

Author

Gerard Ghibaudo, E. G. Ioannidis, Emmanuel Josse, Sebastien Haendler, C.A. Dimitriadis, Christoforos G. Theodorou, T.A. Karatsori, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), Aristotle University of Thessaloniki, Department of Physics, STMicroelectronics [Crolles] (ST-CROLLES), ARISTEIA II(Project 4154 of the GreekGeneral Secretariat for Research and Technology, co-funded by theEuropean Social Fund and national funds), European Project: 325633,EC:FP7:SP1-JTI,ENIAC-2012-2,PLACES2BE(2012), and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)

Subjects
Materials science, business.industry, Extraction (chemistry), Electrical engineering, Hardware_PERFORMANCEANDRELIABILITY, Condensed Matter::Mesoscopic Systems and Quantum Hall Effect, Gate voltage, [SPI.TRON]Engineering Sciences [physics]/Electronics, Computer Science::Hardware Architecture, Computer Science::Emerging Technologies, CMOS, Gate oxide, Hardware_GENERAL, Range (statistics), Hardware_INTEGRATEDCIRCUITS, Optoelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, Communication channel, Front (military), Voltage, Hardware_LOGICDESIGN
Abstract

session poster; International audience; A full front gate voltage range parameter extraction technique is developed taking into account both the back gate voltages and the channel length. The method is easily applicable to extract precisely all electrical parameters of advanced nano-scale FDSOI MOSFETs.

Published
2015
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8. Impact of Source–Drain Series Resistance on Drain Current Mismatch in Advanced Fully Depleted SOI n-MOSFETs

Author

Gerard Ghibaudo, Emmanuel Josse, E. G. Ioannidis, Charalabos A. Dimitriadis, Sebastien Haendler, Christoforos G. Theodorou, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), STMicroelectronics [Crolles] (ST-CROLLES), Aristotle University of Thessaloniki, Department of Physics, NANO2017, European Project: 325633,EC:FP7:SP1-JTI,ENIAC-2012-2,PLACES2BE(2012), and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)

Subjects
Materials science, Silicon on insulator, 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, 01 natural sciences, 0103 physical sciences, MOSFET, 0202 electrical engineering, electronic engineering, information engineering, Hardware_INTEGRATEDCIRCUITS, characterization, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Drain current, 010302 applied physics, Equivalent series resistance, business.industry, matching, 020208 electrical & electronic engineering, Electrical engineering, Y function, Electronic, Optical and Magnetic Materials, CMOS, Logic gate, Optoelectronics, business, Static mismatch variability
Abstract

International audience; In this letter, we demonstrate the existence of the source-drain series resistance mismatch and its impact on drain current variability with regard to the other mismatch parameters. To this end, we propose a new methodology for the drain current mismatch study based on Y-function, enabling a precise determination of the various variability sources in advanced fully depleted silicon on insulator (SOI) MOS devices.

Published
2015
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9. Drain-Current Flicker Noise Modeling in nMOSFETs From a 14-nm FDSOI Technology

Author

Christoforos G. Theodorou, Charalabos A. Dimitriadis, Gerard Ghibaudo, T.A. Karatsori, Sebastien Haendler, E. G. Ioannidis, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), STMicroelectronics, Aristotle University of Thessaloniki, Department of Physics, ARISTEIA II, NANO2017, European Project: 325633,EC:FP7:SP1-JTI,ENIAC-2012-2,PLACES2BE(2012), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), and Centre National de la Recherche Scientifique (CNRS)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Université Grenoble Alpes (UGA)

Subjects
Physics, Noise temperature, Low-frequency noise (LFN), business.industry, Electrical engineering, Semiconductor device modeling, Shot noise, Spectral density, UTBB fully depleted silicon-on-insulator (FDSOI) MOSFETs, Y-factor, Electronic, Optical and Magnetic Materials, Computational physics, Noise generator, MOSFET, Flicker noise, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business
Abstract

Extensive investigation of the drain-current low-frequency noise in n-channel MOSFETs issued from a 14-nm fully depleted silicon-on-insulator technology node has been carried out. The results demonstrate that the carrier number fluctuation (CNF) with correlated mobility fluctuations (CMFs) model accurately and continuously describes the $1/f$ noise from weak to strong inversion, from linear to saturation, and for all the back-bias conditions. It is shown that using only two parameters, i.e., the effective flat-band voltage spectral density $S_{{\text {Vfb,eff}}}$ and CMF factor $\Omega _{{\text {eff}}}$ , the CNF/CMF noise model can predict the transistor $1/f$ noise level of all channel dimensions and under any bias conditions. Thus, it can be easily used in SPICE noise modeling for circuit simulations.

Published
2015
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10. New LFN and RTN analysis methodology in 28 and 14nm FD-SOI MOSFETs

Author

E. G. Ioannidis, Sebastien Haendler, Gerard Ghibaudo, Charalabos A. Dimitriadis, Christoforos G. Theodorou, Emmanuel Josse, Nicolas Planes, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), STMicroelectronics [Crolles] (ST-CROLLES), Aristotle University of Thessaloniki, Department of Physics, NANO2017, and European Project: 325633,EC:FP7:SP1-JTI,ENIAC-2012-2,PLACES2BE(2012)

Subjects
010302 applied physics, Engineering, business.industry, Transistor, Electrical engineering, Silicon on insulator, 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, 021001 nanoscience & nanotechnology, 01 natural sciences, Noise (electronics), Threshold voltage, law.invention, [SPI.TRON]Engineering Sciences [physics]/Electronics, CMOS, law, Logic gate, 0103 physical sciences, Electronic engineering, Hardware_INTEGRATEDCIRCUITS, Node (circuits), [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, business, Cadence
Abstract

session poster; International audience; A thorough investigation and statistical analysis of the low-frequency (LFN) and random telegraph noise (RTN) in 28 and 14nm FD-SOI CMOS transistors is presented, for the first time. It is shown that the 14nm technology node is improved in terms of threshold voltage fluctuations when compared to the 28nm one. A new analysis method that directly probes the RTN presence is also proposed. Finally, the LFN/RTN impact on the device dynamic variability is presented through CADENCE design suite circuit simulations.

Published
2015
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11. Low frequency noise statistical characterization of 14nm FDSOI technology node

Author

Sebastien Haendler, E. G. Ioannidis, Charalabos A. Dimitriadis, Gerard Ghibaudo, Min-Kyu Joo, Emmanuel Josse, Christoforos G. Theodorou, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), STMicroelectronics [Crolles] (ST-CROLLES), School of Electrical Engineering [Korea University], Korea University [Seoul], Aristotle University of Thessaloniki, Department of Physics, NANO2017, European Project: 325633,EC:FP7:SP1-JTI,ENIAC-2012-2,PLACES2BE(2012), and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)

Subjects
010302 applied physics, Computer science, business.industry, Infrasound, 020208 electrical & electronic engineering, CMOS, Electrical engineering, 02 engineering and technology, 01 natural sciences, Characterization (materials science), [SPI.TRON]Engineering Sciences [physics]/Electronics, Noise, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Low-frequency Noise, Node (circuits), Statistical analysis, characterization, Noise level, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business
Abstract

session 10: Advanced characterization techniques; International audience; In this paper, we performed a statistical analysis of the low-frequency noise (LFN) in 14nm FDSOI n-MOS devices. Front and back gate interfaces were characterized, revealing an equal contribution to the total noise level. Finally, the LFN variability is analyzed and a comparison to previous CMOS technologies is presented.

Published
2015
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12. Statistical analysis of dynamic variability in 28nm FD-SOI MOSFETs

Author

Nicolas Planes, E. G. Ioannidis, Charalabos A. Dimitriadis, Christoforos G. Theodorou, Sebastien Haendler, Gerard Ghibaudo, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), Aristotle University of Thessaloniki, STMicroelectronics [Crolles] (ST-CROLLES), European Project: 325633,EC:FP7:SP1-JTI,ENIAC-2012-2,PLACES2BE(2012), and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)

Subjects
010302 applied physics, Physics, Infrasound, 020208 electrical & electronic engineering, Silicon on insulator, 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, Low frequency, 01 natural sciences, Computational physics, [SPI.TRON]Engineering Sciences [physics]/Electronics, Square root, Rise time, 0103 physical sciences, MOSFET, Dispersion (optics), 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Hardware_INTEGRATEDCIRCUITS, Statistical analysis, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

session B8L-E: Variability and Reliability in advanced MOSFETs; International audience; The impact of the dynamic variability due to low frequency and RTS fluctuations on single MOSFET operation from 28nm FD-SOI technology is investigated for the first time. It is shown that, for small rise time of ramp gate voltage, the drain current characteristics I d (V g ) exhibit a huge sweep-to-sweep dispersion due to the low frequency noise. Such a single device dynamic variability, which scales as the reciprocal square root of device area, is added to the static mismatch contribution and could amount up to ≈30% of static variability sources.

Published
2014
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13. Evolution of low frequency noise and noise variability through CMOS bulk technology nodes from 0.5μm down to 20nm

Author

Charalabos A. Dimitriadis, Gerard Ghibaudo, Christoforos G. Theodorou, S. Lasserre, E. G. Ioannidis, Sebastien Haendler, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), STMicroelectronics [Crolles] (ST-CROLLES), Aristotle University of Thessaloniki, Department of Physics, IBM France (IBM), IBM, European Project: 325633,EC:FP7:SP1-JTI,ENIAC-2012-2,PLACES2BE(2012), and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)

Subjects
Materials science, Statistical noise, business.industry, variability, Infrasound, Noise spectral density, CMOS, Electrical engineering, Equivalent oxide thickness, Condensed Matter Physics, Noise (electronics), Electronic, Optical and Magnetic Materials, Low-frequency noise, Materials Chemistry, Miniaturization, Optoelectronics, Node (circuits), Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business
Abstract

International audience; In this paper, we present a thorough investigation of low frequency noise (LFN) and statistical noise variability through CMOS planar bulk technologies manufactured along the past 12 years and, for the first time, from the most recent 20 nm CMOS bulk technology node. The experimental results are well interpreted by the carrier number with correlated mobility fluctuation model. This enabled us to plot the evolution with time and technology generation of the oxide trap density Nt as a function of equivalent oxide thickness (EOT). It appears that, with the device miniaturization, Nt overall increases almost by two decades with decreasing the EOT thickness from 12 nm for the 0.5 μm node to 1.3 nm for the 20 nm node for n- and p-MOS. Despite this increase of the mean trap density Nt, the LFN statistical variability has surprisingly been well controlled with the decrease of EOT and the increase of Nt and even improved in 28 and 20 nm node.

Published
2014
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14. Low-Frequency Noise Sources in Advanced UTBB FD-SOI MOSFETs

Author

Francois Andrieu, Olivier Faynot, Christoforos G. Theodorou, Charalabos A. Dimitriadis, Thierry Poiroux, E. G. Ioannidis, Gerard Ghibaudo, Aristotle University of Thessaloniki, Department of Physics, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), HERACLEITUS II, Centre National de la Recherche Scientifique (CNRS)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Université Grenoble Alpes (UGA), Laboratoire d'Electronique et des Technologies de l'Information (CEA-LETI), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Grenoble Alpes (UGA), and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)

Subjects
Materials science, Silicon, Infrasound, ultrathin body and buried oxide fully depleted silicon-on-insulator (UTBB FDSOI MOSFETs), Silicon on insulator, chemistry.chemical_element, 02 engineering and technology, 01 natural sciences, Generation-recombination (g-r) noise, 0103 physical sciences, MOSFET, Flicker noise, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 010302 applied physics, Thin layers, business.industry, Flicker, low-frequency noise (LFN), 021001 nanoscience & nanotechnology, Electronic, Optical and Magnetic Materials, chemistry, Optoelectronics, 0210 nano-technology, business, Noise (radio)
Abstract

International audience; The low-frequency noise (LFN) sources in ultrathin body (8.7 nm) and buried oxide (10 nm) fully depleted silicon-on-insulator (UTBB FD-SOI) n- and p-channel MOSFETs are analyzed. Both flicker and Lorentzian-type noise were observed, showing a dependence on the channel dimensions and the front/back gate bias conditions. The flicker noise component can be described by the carrier number with correlated mobility fluctuations model considering contribution from both interfaces. The Lorentzian-type noise originates mainly from generation-recombination (g-r) traps in the Si film, uniformly distributed in thin layers next to the drain and source contacts, and in some cases from g-r traps located at the front Si/oxide interface. No different noise behavior was observed between n- and p-channel devices operating in front-gate mode. Finally, LFN comparison between FD-SOI devices of different technologies is presented for the first time, demonstrating the impact of the UTBB technology on the LFN properties.

Published
2014
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15. Impact of dynamic variability on the operation of CMOS inverter

Author

Charalabos A. Dimitriadis, J. P. Manceau, E. G. Ioannidis, Sebastien Haendler, Gerard Ghibaudo, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)

Subjects
010302 applied physics, Engineering, business.industry, Infrasound, 020208 electrical & electronic engineering, 02 engineering and technology, 01 natural sciences, Noise (electronics), Reduction (complexity), Noise margin, CMOS, 0103 physical sciences, Dispersion (optics), 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Inverter, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, ComputingMilieux_MISCELLANEOUS, Voltage
Abstract

The impact of dynamic variability due to low-frequency fluctuations on the operation of CMOS inverters, which constitute the basic component of SRAM cell, is investigated. The experimental methodology to characterise the effect of dynamic variability in a CMOS inverter is first established based on fast I–V measurements of the load current following the application of a ramp input voltage V in(t). It is shown that, for small ramp rise times, the load current characteristics I DD(V in) exhibit a huge sweep-to-sweep dispersion due to low-frequency noise. The impact of such dynamic variability sources on the inverter's output characteristics V out(V in) is finally demonstrated, revealing a 20% noise margin reduction for the smallest inverter cell.

Published
2013
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16. Evolution of low frequency noise and noise variability through CMOS bulk technology nodes

Author

E. G. Ioannidis, Charalabos A. Dimitriadis, Julien Rosa, Sebastien Haendler, Gerard Ghibaudo, A. Bajolet, J. P. Manceau, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), and STMicroelectronics [Crolles] (ST-CROLLES)

Subjects
Electron mobility, low-freqency noise, Statistical noise, Infrasound, fluctuations, Equivalent oxide thickness, 02 engineering and technology, 01 natural sciences, Noise (electronics), statistical analysis, 0103 physical sciences, Miniaturization, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, carrier mobility, 010302 applied physics, Physics, business.industry, Electrical engineering, 021001 nanoscience & nanotechnology, CMOS integrated circuits, CMOS technology, dielectrics, CMOS, Optoelectronics, Node (circuits), 0210 nano-technology, business
Abstract

In this paper, we present a thorough investigation of low frequency noise (LFN) and statistical noise variability through CMOS bulk technologies manufactured in STMicroelectronics along the past 12 years. The experimental results are well interpreted by the carrier number (CNF) with correlated mobility (CMF) fluctuation model. This enabled us to plot the evolution with time and technology generation of the oxide trap density Nt, as a function of equivalent oxide thickness EOT. It appears that, with the device miniaturization, Nt, has increased from 2×1016/eV/cm3 up to 5-7×1017/eV/cm3 when passing from EOT=12nm for 250nm node to EOT=1.4nm for 28nm node for n-MOS. Despite this increase of the mean trap density Nt, the LFN statistical variability has surprisingly been well controlled and even improved in 28nm node, emphasizing the progress in process control in such advanced technologies.

Published
2013
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17. Low-Frequency noise behavior of n-channel UTBB FD-SOI MOSFETs

Author

Gerard Ghibaudo, Thierry Poiroux, Olivier Faynot, Charalabos A. Dimitriadis, Christoforos G. Theodorou, E. G. Ioannidis, Francois Andrieu, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Research Funding Program HERACLEITUS II, co-financed by the European Union (European Social Fund-ESF) and Greek national funds through the Operational Program 'Education and Lifelong Learning' of the National Strategic Reference Framework (NSRF)., and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)

Subjects
semiconductor device noise, Y-factor, 02 engineering and technology, fluctations, 01 natural sciences, Noise (electronics), MOSFET, Noise generator, 0103 physical sciences, Flicker noise, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, carrier mobility, 010302 applied physics, Physics, business.industry, low-frequency noise, Shot noise, electron-hole recombiantion, Biasing, 021001 nanoscience & nanotechnology, silicon-on-insulator, Burst noise, Optoelectronics, 1f noise, 0210 nano-technology, business
Abstract

The low-frequency noise (LFN) behavior of ultra thin body and buried oxide (UTBB) fully-depleted (FD) silicon-on-insulator (SOI) n-channel MOSFETs has been explored, emphasizing on the contribution of the buried-oxide (BOX) and the Si-BOX interface to the total drain current noise level. In order to successfully distinguish the different noise sources, measurements under different front and back gate voltages were performed. The noise spectra for all bias conditions consist of both flicker and Lorentzian-type noise components. A fitting method was used to extract the parameters of the LFN. It is shown that the flicker noise follows the carrier number with correlated mobility fluctuations model at both interfaces and the Si/BOX interface contributes to the total LFN level, even without back gate bias voltage. The front and back gate voltage dependence of the Lorentzian time constants indicates a uniform distribution of generation-recombination (g-r) centers within the silicon film. In addition, when the Si/BOX interface is accumulated, interface traps at the front gate are activated due to higher front gate voltages, giving rise to a different type of g-r noise.

Published
2013
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18. Characterization and modeling of low frequency noise in CMOS inverters

Author

Charalabos A. Dimitriadis, E. G. Ioannidis, Gerard Ghibaudo, Sebastien Haendler, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), and Centre National de la Recherche Scientifique (CNRS)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Joseph Fourier - Grenoble 1 (UJF)

Subjects
Engineering, Infrasound, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, 01 natural sciences, Noise (electronics), Computer Science::Hardware Architecture, Computer Science::Emerging Technologies, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, Materials Chemistry, Electronic engineering, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS, Electronic circuit, 010302 applied physics, FO4, business.industry, Electrical engineering, 021001 nanoscience & nanotechnology, Condensed Matter Physics, Electronic, Optical and Magnetic Materials, Characterization (materials science), CMOS, Inverter, 0210 nano-technology, business, Voltage
Abstract

A detailed characterization and modeling of the low frequency noise in a CMOS inverter is presented for the first time. A low frequency noise model for the load current and the output voltage is developed based on the carrier number fluctuations scheme. This model allows obtaining a consistent description of the noise characteristics of CMOS inverters issued from a 45 nm bulk CMOS technology. It should constitute a reliable theoretical framework for further analysis of the impact of time fluctuations on the static and dynamic operation of CMOS inverter based circuits.

Published
2013
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19. Front-back gate coupling effect on 1/f noise in ultra-thin Si film FDSOI MOSFETs

Author

Francois Andrieu, Gerard Ghibaudo, Nicolas Planes, Olivier Faynot, Christoforos G. Theodorou, J. Jomaah, Charalabos A. Dimitriadis, Sebastien Haendler, E. G. Ioannidis, Franck Arnaud, Thierry Poiroux, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), Aristotle University of Thessaloniki, STMicroelectronics [Crolles] (ST-CROLLES), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), HERACLEITUS IIco-financed by the European Union (European Social Fund – ESF) and Greeknational funds through the Operational Program ‘‘Education andLifelong Learning’’ of the National Strategic Reference Framework(NSRF), European Project: CT208,Catrene, and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)

Subjects
010302 applied physics, Materials science, business.industry, Semiconductor device modeling, Silicon on insulator, Charge density, Biasing, 02 engineering and technology, 021001 nanoscience & nanotechnology, 01 natural sciences, Noise (electronics), [SPI.TRON]Engineering Sciences [physics]/Electronics, CMOS, 0103 physical sciences, MOSFET, Optoelectronics, Flicker noise, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, business
Abstract

International audience; Low-frequency (LF) noise was studied on 28 nm CMOS technology FDSOI devices with ultra-thin silicon film (7 nm) and thin buried oxide (25 nm). The noise level was observed to be strongly dependent on the combination of the front and back gate biasing voltages. This was explained by the coupling effect of both Si/High-K dielectric and Si/SiO 2 interface noise sources (channel/front oxide and channel/buried oxide), in combination with the variation of the Remote Coulomb scattering coefficient α. From comparison of the experimental and simulation results, it is illustrated that the main reason of this dependence is the distance between the charge distribution centroid and the interfaces, which is also controlled by both front and back-gate bias voltages, and the way this distance affects the Remote Coulomb scattering coefficient α. A new LF noise model approach is suggested to include the impact of all these parameters, and also allows us to extract the oxide trap density values for both interfaces.

Published
2012
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20. Impact of front-back gate coupling on low frequency noise in 28 nm FDSOI MOSFETs

Author

Charalabos A. Dimitriadis, Christoforos G. Theodorou, Sebastien Haendler, Nicolas Planes, Gerard Ghibaudo, E. G. Ioannidis, Franck Arnaud, J. Jomaah, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), STMicroelectronics [Crolles] (ST-CROLLES), Aristotle University of Thessaloniki, HERACLEITUS IIco-financed by the European Union (European Social Fund – ESF) and Greeknational funds through the Operational Program ‘‘Education andLifelong Learning’’ of the National Strategic Reference Framework(NSRF), European Project: CT208,Catrene, and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)

Subjects
010302 applied physics, Materials science, business.industry, Infrasound, Oxide, Electrical engineering, Charge density, Silicon on insulator, Biasing, 02 engineering and technology, 021001 nanoscience & nanotechnology, 01 natural sciences, Noise (electronics), [SPI.TRON]Engineering Sciences [physics]/Electronics, chemistry.chemical_compound, chemistry, Gate oxide, 0103 physical sciences, MOSFET, Optoelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, business
Abstract

International audience; Low-frequency (LF) noise has been studied on 28 nm FDSOI devices with ultra-thin silicon film (7 nm) and thin buried oxide (25 nm). A strong dependence of the noise level on the combination of the front and back biasing voltages was observed, and justified by the coupling effect of both Si/High-K dielectric and Si/SiO2 interface noise sources (channel/front oxide and channel/buried oxide), combined with the change of the Remote Coulomb scattering. From comparisons of the experimental and simulation results, it is shown that the main reason of this dependence is the distance of the charge distribution centroid from the interfaces, which is controlled by both front and back-gate bias voltages, and the way this distance affects the Remote Coulomb scattering coefficient a. A new LF noise model approach is proposed to include all these effects. This also allows us to assess the oxide trap density values for both interfaces.

Published
2012
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21. Bladder wall thickness and urodynamic correlation in children with primary nocturnal enuresis

Author

Nikoleta Printza, E. G. Ioannidis, Fotios Papacristou, Hashim Hashim, Vassilios Rompis, Maria Bantouraki, and Stavros Charalampous

Subjects
Male, medicine.medical_specialty, Adolescent, Primary nocturnal enuresis, business.industry, Urology, Ultrasound, Urinary Bladder, Urodynamic studies, Surgery, Correlation, Urodynamics, Pediatrics, Perinatology and Child Health, medicine, Humans, Screening tool, Female, business, Wall thickness, Child, Nocturnal Enuresis
Abstract

To investigate the correlations between ultrasonographic bladder wall thickness (BWTh) and urodynamic study (UDS) findings and estimate the diagnostic value of BWTh for prediction of DO in children with monosymptomatic and non-monosymptomatic primary nocturnal enuresis (PNE).Ultrasound measurements (US) and UDS were performed on a total of 100 children, 50 consecutive boys and 50 consecutive girls, 6-14 years old, with monosymptomatic PNE (group 1, n = 75), and non-monosymptomatic PNE (group 2, n = 25). The US Protocol was specially designed for the evaluation of BWTh. All children underwent urodynamic studies for detailed assessment of any underlying bladder overactivity. Findings were compared between the two groups of patients.The mean BWTh was increased in the group 2 compared to the group 1 (mean ± SD = 2.4 ± 0.41 mm, mean ± SD = 1.52 ± 0.18 mm respectively, p 0.05). Detrusor overactivity (DO) occurred in 23/75 (30.5%) children of the group 1 and in 17/25 (68%) children of the group 2 (p 0.05). Comparing the BWTh between the two groups of patients and the UDS findings, it was found that BWTh was significantly correlated with DO(r = 0.92 and p 0.001), children with DO presented significantly increased BWTh compared to those without (mean ± SD = 2.1 ± 0.4 mm, mean ± SD = 1.5 ± 0.4 mm respectively, p 0.05) and the maximum amplitude of DO occurred in 20 children who had non-monosymptomatic PNE.We suggest that BWTh could be applied as a screening tool to identify the cases of DO between the children with PNE. Children with non-monosymptomatic PNE presented increased BWTh and higher percentages of DO.

Published
2011

22. Low frequency noise variability in high-k/metal gate stack 28nm bulk and FD-SOI CMOS transistors

Author

Michel Haond, Claire Fenouillet-Beranger, Charalabos A. Dimitriadis, Julien Rosa, E. G. Ioannidis, Pierre Perreau, T. Pahron, Dominique Golanski, A. Bajolet, Franck Arnaud, R.A. Bianchi, Sebastien Haendler, Nicolas Planes, and Gerard Ghibaudo

Subjects
Materials science, business.industry, Transistor, Gate dielectric, Silicon on insulator, law.invention, CMOS, Stack (abstract data type), law, MOSFET, Optoelectronics, business, Metal gate, High-κ dielectric
Abstract

In this paper, we present, for the first time, a thorough investigation of low frequency noise (LFN) and statistical noise variability in high-k/metal gate stack 28nm bulk and FD-SOI CMOS transistors. The experimental results are well interpreted by Monte-Carlo LFN simulations based on the random spatial and energy distribution of discrete traps in the gate dielectric. Our results clearly indicate that the LFN variability of 28nm FD-SOI CMOS technology is improved as compared to previous 45nm and 32nm bulk CMOS technologies.

Published
2011
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23. Characterization of traps in the gate dielectric of amorphous and nanocrystalline silicon thin-film transistors by 1/f noise

Author

D. H. Tassis, G. Kamarinos, Charalabos A. Dimitriadis, E. G. Ioannidis, François Templier, and A. Tsormpatzoglou

Subjects
Amorphous silicon, Materials science, Silicon, business.industry, Gate dielectric, Nanocrystalline silicon, General Physics and Astronomy, chemistry.chemical_element, Noise (electronics), Amorphous solid, chemistry.chemical_compound, chemistry, Thin-film transistor, Gate oxide, Optoelectronics, business
Abstract

The low frequency noise technique is used to obtain the volume profile of traps in the SiNx gate dielectric of hydrogenated amorphous silicon (a-Si:H) and nanocrystalline silicon (nc-Si:H) thin film transistors (TFTs). In both a-Si:H and nc-Si:H TFTs, within the range of probing depth in the gate dielectric, the traps have a uniform spatial distribution which is consistent with the observed pure 1/f noise. The experimental results show that the gate dielectric trap properties near the interface are dependent on the channel material with the trap density in nc-Si:H TFTs being much smaller in comparison with the a-Si:H TFTs.

Published
2010
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24. Analytical low-frequency noise model in the linear region of lightly doped nanoscale double-gate metal-oxide-semiconductor field-effect transistors

Author

Gerard Ghibaudo, A. Tsormpatzoglou, J. Jomaah, Christoforos G. Theodorou, Charalabos A. Dimitriadis, K. A. Papathanasiou, D. H. Tassis, E. G. Ioannidis, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), and Cooperation (General Secreteriat for Research andTechnology, Ministry of Education, Greece)

Subjects
010302 applied physics, Materials science, Equivalent series resistance, business.industry, Scattering, Infrasound, Transconductance, Transistor, General Physics and Astronomy, Saturation velocity, 02 engineering and technology, Condensed Matter::Mesoscopic Systems and Quantum Hall Effect, 021001 nanoscience & nanotechnology, 01 natural sciences, law.invention, Computer Science::Hardware Architecture, law, [PHYS.COND.CM-GEN]Physics [physics]/Condensed Matter [cond-mat]/Other [cond-mat.other], 0103 physical sciences, MOSFET, Optoelectronics, Field-effect transistor, 0210 nano-technology, business
Abstract

International audience; An analytical model for the transconductance to drain current ratio (gm/Id) of lightly doped nanoscale double-gate metal-oxide-semiconductor field-effect transistors (DG MOSFETs) has been developed in the weak inversion and from linear to saturation region, using the conductive path potential approach. The obtained analytical model for gm/Id in the weak inversion has been extended in the strong inversion and in the linear region including the short-channel effects, as well as the surface roughness scattering, series resistance, and saturation velocity effects. The obtained gm/Id model from weak to strong inversion has been verified by comparing simulation and experimental results of DG MOSFET with gate length 50 nm and it has been implemented in modeling the 1/f low-frequency noise. The introduced noise model has been validated by developing a Verilog-A transistor noise model, which is in good agreement with the experimental noise results of DG MOSFET with gate length 50 nm in the linear region from weak to strong inversion.

Published
2010
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