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This work presents a single event double node upset (SEDNU) self-healing (DNUSH) latch to meet the high-robustness requirement of the applications used in a harsh radiation environment. The DNUSH latch is based on dual modular redundancy and mainly employs C-elements and inverters, forming multi-feedback interlocked loops to retain the correct data even after the radiation event. The self-healing capability of the proposed latch is successfully shown by the fault injection simulation using Synopsys HSPICE. Simulation results show that the proposed latch can self-heal from all SEDNUs, consumes low power even for high-speed operations, and has the least power-delay-area product (PDAP) compared to the existing SEDNU resilient latches. The proposed latch offers on average 51.25% improvement in speed, 22.67% saving in power consumption, and 59.74% lower PDAP compared to the existing SEDNU resilient latches. In addition, the sensitivity assessment of the proposed latch against the process, voltage, and temperature (PVT) variations are found to be either low or equivalent to the reference latches.

Dual modular redundancy (DMR) is not only an established solution for systems with high reliability demands, it is even required in aviation certification standards such as DO-254 [5, Clause 2.3.1]. A safety critical avionic application such as the flight control system is designed with up to 6-fold redundancy and the Avionics Full-Duplex Ethernet (AFDX) communication network is also based on the DMR. Even in the automotive domain, DMR is a well known solution. ISO26262 [3, Part 6, Clause 7.4.13] also suggests heterogeneous or diverse redundancy for safety-critical applications including software which must be redundantly executed on independent hardware components to avoid failure due to hardware errors. We exploit this mandatory software redundancy to master timing errors of critical software with minimum additional overhead.

The recent emergence of 5G network enables mass wireless sensors deployment for internet-of-things (IoT) applications. In many cases, IoT sensors in monitoring and data collection applications are required to operate continuously and active at all time (24/7) to ensure all data are sampled without loss. Field-programmable gate array (FPGA)-based systems exhibit a balanced processing throughput and datapath flexibility. Specifically, datapath flexibility is acquired from the FPGA-based system architecture that supports dynamic partial reconfiguration feature. However, device functional update can cause interruption to the application servicing, especially in an FPGA-based system. This paper presents a standalone FPGA-based system architecture that allows remote functional update without causing service interruption by adopting a redundancy mechanism in the application datapath. By utilizing dynamic partial reconfiguration, only the updating datapath is temporarily inactive while the rest of the circuitry, including the redundant datapath, remain active. Hence, there is no service interruption and downtime when a remote functional update takes place due to the existence of redundant application datapath, which is critical for network and communication systems. The proposed architecture has a significant impact for application in FPGA-based systems that have little or no tolerance in service interruption.

The rate of transient faults has increased significantly as the technology scales up. The tolerance of transient faults has become an important issue in the system design. Dual modular redundancy (DMR) and triple modular redundancy (TMR) are two commonly used techniques that can achieve fault detection and masking through executing redundant tasks. As DMR and TMR have different time and cost overheads, we must carefully determine which one should be used for each task (i.e., task hardening) to achieve the optimal system design. Furthermore, for multi-core systems, the system-level design includes the allocation of cores for the tasks (i.e., task mapping) as well. This paper aims at task hardening and mapping simultaneously for independent tasks on multi-cores with heterogeneous performances, in order to minimize the maximum completion time of all tasks (i.e., makespan). We demonstrate that once task hardening is given, task mapping of independent tasks can be achieved by employing min–max-weight perfect matching with a polynomial time complexity. Besides, as there is a trade-off between cost and time performance, we propose a multi-objective memetic algorithm (MOMA)-based task hardening method to obtain a set of solutions with different numbers of cores (i.e., costs), so the designer can choose different solutions according to different requirements. The key idea of the MOMA is to incorporate problem-specific knowledge into the global search of evolutionary algorithms. Our experimental studies have demonstrated the effectiveness of the proposed method and have shown that by combining the results of MOMA and MOEA we can provide a designer with a highly accurate set of solutions within a reasonable amount of time.

International audience; This paper presents a dual-modular-redundancy and dual-level error-interception based triple-node-upset (TNU) tolerant latch design (namely DDETT) for safety-critical applications. The DDETT latch comprises two parallel single-node-upset self-recoverable cells to store values and three C-elements to intercept errors. Both of the two cells are constructed from triple mutually-feeding-back 2-input C-elements, and the cells feed two internal C-elements for first-level error-interception. Moreover, the two internal C-elements feed an output-stage C-element for second-level error-interception, making the DDETT latch TNU-tolerant in that it can tolerate any possible TNU. This paper further presents a low-cost version of the DDETT latch, namely LCDDETT. The LCDDETT latch uses two dual-interlocked-storage-cells (DICEs) to store values and uses dual-level error-interception to tolerate any possible TNU with cost-effectiveness. Simulation results not only confirm the TNU-tolerance of the proposed latches but also demonstrate that the delay-power-area products of the DDETT and LCDDETT latches are reduced by approximately 34% and 58%, respectively.

Basic Linear Algebra Subprograms (BLAS) is a core library in scientific computing and machine learning. This paper presents FT-BLAS, a new implementation of BLAS routines that not only tolerates soft errors on the fly, but also provides comparable performance to modern state-of-the-art BLAS libraries on widely-used processors such as Intel Skylake and Cascade Lake. To accommodate the features of BLAS, which contains both memory-bound and computing-bound routines, we propose a hybrid strategy to incorporate fault tolerance into our brand-new BLAS implementation: duplicating computing instructions for memory-bound Level-1 and Level-2 BLAS routines and incorporating an Algorithm-Based Fault Tolerance mechanism for computing-bound Level-3 BLAS routines. Our high performance and low overhead are obtained from delicate assembly-level optimization and a kernel-fusion approach to the computing kernels. Experimental results demonstrate that FT-BLAS offers high reliability and high performance -- faster than Intel MKL, OpenBLAS, and BLIS by up to 3.50%, 22.14% and 21.70%, respectively, for routines spanning all three levels of BLAS we benchmarked, even under hundreds of errors injected per minute., camera-ready version at ICS'21: International Conference on Supercomputing 2021 with ISBN updated

Persistence is an intrinsic nature of many errors yet has not been caught enough attractions for years. In this chapter, the feature of persistence is applied to fault attacks (FAs), and the persistent FA is proposed. Different from traditional FAs, adversaries can prepare the fault injection stage before the encryption stage, which relaxes the constraint of the tight-coupled time synchronization. The persistent fault analysis (PFA) is elaborated on different implementations of AES-128, specially fault-hardened implementations based on dual modular redundancy (DMR). Our experimental results show that PFA is quite simple and efficient in breaking these typical implementations. To show the feasibility and practicability of our attack, a case study is illustrated on a few countermeasures of masking. This work puts forward a new direction of FAs and can be extended to attack other implementations under more interesting scenarios.

This paper describes the failure detection system of an electro-hydraulic actuator with dual modular redundancy based on a hybrid twin TM concept. Hybrid twin TM is a combination of virtual twin that operates in parallel with the actuator and represents its ideal behaviour, and a digital twin that identifies possible failures using the sensor readings residuals. Simulation-based system reliability analysis helps to generate a dataset for training the digital twin using machine learning algorithms. A systematic failure detection approach based on decision trees and the process of analysing the quality of the result is described.

Autonomous driving (AD) imposes the need for safe computations in high-performance computing (HPC) components such as GPUs, thus with capabilities to detect and recover from errors since a safe state may not exist anymore. This can be achieved with Triple Modular Redundancy (TMR) for computation components. Furthermore, error detection capabilities need to provide some form of diversity to avoid the case where a single fault leads all redundant executions lead to the same error, which would go undetected. In our past work, we assessed GPUs against dual modular redundancy (DMR) with diversity, showing their potential and limitations to provide diverse redundancy building on reset and restart for recovery. However, such recovery scheme may be too slow for some applications. This paper proposes a software-only solution to deliver diverse TMR on commercial off-the-shelf (COTS) GPUs. Our work details how staggered execution can be achieved and assesses the performance of TMR on COTS GPUs. Moreover, we identify those elements where diversity cannot be guaranteed and provide some discussion comparing the case of DMR and TMR for those elements. This project has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No 871467 (SELENE). Leonidas Kosmidis has been partially supported by the Spanish Ministry of Economy and Competitiveness (MINECO) under a Juan de la Cierva Formacion postdoctoral fellowship with number FJCI-2017-34095.

SRAM-based field-programmable gate arrays (FPGAs) are widely deployed in space and high-radiation environments, but they exhibit vulnerability to radiation effects. Designs can be hardened against radiation effects with design-side countermeasures such as redundancy, scrubbing, and partitioning. Through neutron tests, we investigate the impact of these design-side countermeasures on 28-nm FPGAs. We specifically address not only the provided radiation hardness but also the resource utilization and performance overheads. In addition, we evaluate the efficacy of repeating the operation after error detection. The results show that using coarse-grained and fine-grained triple modular redundancy (TMR) over dual modular redundancy (DMR) improves the failure cross section by $3.29\times $ and $11.49\times $ , respectively. The partitioning scheme that we used does not show a significant effect on radiation hardness. Using an internal scrubber and repeating the operation after a failure further decreases DMR, coarse-grained TMR, and fine-grained TMR cross sections by $5.10\times $ , $1.85\times $ , and $1.18\times $ , respectively.

This paper presents a practical view of how to implement a dual modular redundancy (DMR) scheme in a central processing unit–field-programmable gate array (CPU–FPGA) heterogeneous platform-based system, which is also described. FPGAs can be valuable resources when determinism and fast response/acquisition rates are required, while processing large volumes of data. On the other side, CPUs are affordable options for most other processing tasks, especially less frequent tasks, such as data recording. A heterogeneous platform is herein proposed and aims to achieve a reliable, however cost-effective solution. Subsequently, this paper proposes a method to implement a DMR scheme for monitoring systems by means of self-monitoring schemes, health indicators, and a voter that is not a physical switch connected to the monitoring devices, but is software-implemented within the interface system after the data storage system. This proved to be an effective way to deal with disagreements between units when an even number of units are being used, thus not being possible to use a majority-based voting system. The implemented design was thoroughly tested, showing effectiveness in terms of redundancy with improved reliability.

Triple-modular redundancy (TMR), which consists of three identical modules and a voting circuit, is a common architecture for soft-error tolerance. However, the original TMR suffers from two major drawbacks: the large area overhead and the vulnerability of the voter. In order to overcome these drawbacks, we propose a new complementary dual-modular redundancy (CDMR) scheme for mitigating the effect of soft errors. Inspired by the Markov random field (MRF) theory, a two-stage voting system is implemented in CDMR, including a first-stage optimal MRF structure and a second-stage high-performance merging unit. The CDMR scheme can reduce the voting circuit area by 20% while saving the area of one redundant module, achieving at least 26% error-rate reduction at an ultralow supply voltage of 0.25 V with 8.33% faster timing compared to previous voter designs.

Compared with application specific integrated circuits (ASICs), static random access memory (SRAM)-based field programmable gate arrays (FPGAs) respond differently to radiation due to the configuration memory vulnerability. In this brief, the differences between the permanent error model for SRAM-based FPGAs due to configuration memory single event upsets (SEUs), and the ASIC SEU error model are put into perspective for error detection schemes. In particular, a concurrent error detection (CED) technique for finite impulse response filters in ASICs is implemented and evaluated in an SRAM-based FPGA through fault injection emulation. This method is compared with a dual modular redundancy (DMR) scheme in order to obtain a common behavior. The analysis of experimental data indicates that the CED technique has less undetected errors than DMR. However, our exhaustive fault injection tests reveal that false positive detections are more likely to occur in CED, since the error detection branch uses more FPGA resources than the DMR comparator. This phenomenon, which is negligible in ASICs, implies a partial or complete unnecessary reconfiguration, so it should be considered in SRAM-based FPGAs.

We analyze the availability of the Safety Programmable Logic Controller (SPLC) having multiple redundant architectures. In the SPLC, input/output and processor module are configured as triple modular redundancy (TMR), and backplane bus, power and communication modules are configured as dual modular redundancy (DMR). The voting logics for redundant architectures are based on the forwarding error detection. It means that the receivers perform the voting logics based on the status information of transmitters. To analyze the availability of SPLC, we construct the Markov model and simplify the model adopting the system unavailability rate. The results show that the fault coverage factor should be ≥0.8 and Mean Time To Repair (MTTR) should be ≤100 h in order to satisfy the requirement that the availability of the safety grade PLC should be ≥0.995. Also we evaluate the availability of SPLC comparing to other PLCs such as simplex, processor DMR (pDMR) and independent TMR (iTMR) PLCs used in the existing nuclear safety systems. The availability of SPLC is higher than those of the simplex, pDMR but is lower than that of iTMR for one month which is the periodic off-line test and inspection. That’s why the number of redundant modules used in PLC is more dominant to increasing the availability than the number of fault masking methods such as voting logics used in PLC on the assumption that operation time is in the early stage. But the availability of iTMR, which has many redundant modules but has only a voting logic fast decrease and eventually is the lowest after 8000 h. Also if the MTTR of each module in PLC is required to be increased to 200 h, the availability of SPLC would be better than iTMR.

This study presents new reliability models for k -out-of- n systems using a structured continuous-time Markov chain. The approach makes it comfortable to identify the characteristics of the lifetime of the system, such as reliability and expected lifetime. To demonstrate the advantage, the analysis results of them for the multi-spectral camera system, which is the only payload of Korea multi-purpose satellite-2 as an example of a real system. Furthermore, existing studies on a k -out-of- n system with standby redundancy has provided the approximated reliability for it. In this paper, it is confirmed that the approximation error could have an effect on the reliability design for a system. Moreover, new versions of reliability optimization problems, redundancy allocation problem (RAP) and reliability-redundancy allocation problem(RRAP), are proposed. In order to maximize system reliability, they further determine the redundancy strategy, either active or standby redundancy for each k -out-of- n subsystem from the traditional problems. A parallel genetic algorithm is proposed for an RRAP modeled by nonlinear mixed integer programming.

We propose fully programmable redundancy schemes for spin-transfer-torque magnetic random access memories (STT-MRAMs). To store redundancy information, these schemes use magnetic tunnel junctions (MTJs), which are core memory elements of STT-MRAMs. This can greatly simplify the fabrication process of STT-MRAMs. Furthermore, it also allows reprogramming of the redundancy information after packaging or even during normal use by end-users without requiring any special high-voltage setup. We propose two redundancy schemes. First, we propose an address comparator, which uses MTJs and is a direct replacement of a conventional address comparator. Second, we propose a scheme in which the redundancy circuits share the storage cells and read–write peripheral circuits with the normal data array structure.

Reliability issues are more severe in multi/many-core systems because of the integration of more devices in advanced technology nodes. To achieve robust computing in nanoscale designs, many circuit-level and architecture-level redundancy techniques had been proposed, which pose large fixed silicon area overhead and a lack of flexibility. In recent years, some methods have exploited the “inherent core redundancy” of many-core systems to implicitly implement N-modular redundant (NMR) subsystems to achieve area-efficient fault-tolerant computing. However, while facing the different levels of soft error rate, task vulnerability, and task significance in the many-core system, existing core-level redundancy methods become ineffective. To achieve robust computation in many-core systems with intercore variations and mixed workloads, we propose a variation-aware core-level redundancy scheme. Two novel approaches are presented in this scheme: 1) we construct NMR tables that store the degree of redundancy using mathematical models for systems affected by these variations and 2) we dynamically allocate each replicated task to a proper core with variation-aware mapping algorithms to achieve high reliability. Based on a modified multicore simulator, Sniper-Transient Error Process Variation (TEVR), the experimental results show that the proposed scheme can increase the reliability by 47.92% and achieve the energy saving of 39% compared with conventional core-level redundancy methods.

This paper develops a new model for redundancy allocation problem. In this paper, like many recent papers, the choice of the redundancy strategy is considered as a decision variable. But, in our model each subsystem can exploit both active and cold-standby strategies simultaneously. Moreover, the model allows for component mixing such that components of different types may be used in each subsystem. The problem, therefore, boils down to determining the types of components, redundancy levels, and number of active and cold-standby units of each type for each subsystem to maximize system reliability by considering such constraints as available budget, weight, and space. Since RAP belongs to the NP-hard class of optimization problems, a genetic algorithm (GA) is developed for solving the problem. Finally, the performance of the proposed algorithm is evaluated by applying it to a well-known test problem from the literature with relatively satisfactory results.

The paper presents a fault-tolerant digital system design and development strategy for high reliability hardware architectures implementation. Starting from the general consideration that digital hardware systems play a key role in a large scale of control systems implementation, a triple modular redundancy (TMR) solution it is proposed for development. For this reason, the well-known 1 bit majority voter configuration has been extended and generalized to the full control bus of a digital control system. Computer simulations show that the proposed hardware solution fulfills in all the theoretical expectations and it can be used for experimental tests and implementation. The presented design solution and conclusions are well suited to generalization for a wide range of fault-tolerant digital systems development ranging from reliable and safety servo control applications up to high reliability parallel and distributed computing hardware architectures.

Single event transients (SETs) in combinational logic remain an important topic in the reliability domain. SETs were traditionally relatively short in comparison to the clock period. The majority of the countermeasures utilizes this property. However, advances in technology scaling will reverse the ratio for complementary metal-oxide semiconductor devices. Investigations show that SETs may last up to multiple clock cycles in the future. So-called long duration transients (LDTs) corrupt almost all available countermeasures. This paper presents a new methodology to tackle LDTs. Dual modular redundancy (DMR) is used to detect any corruption of the application logic. A new micro-rollback scheme expands the DMR architecture with fault correction capabilities. The concept is also capable of handling single event upsets and timing violations. The correction penalty is two clock cycles. The approach was implemented and verified in a Viterbi decoder architecture. The scheme utilizes a newly designed History Cell. The History Cell introduces an area overhead of 97% and a power overhead of 110%, compared to a standard cell DFF.

This research paper presents practical stochastic models for designing and analyzing the time-dependent reliability of nonrepairable systems. The models are formulated for nonrepairable systems with heterogeneous components having phase-type time-to-failure distributions by a structured continuous time Markov chain (CTMC). The versatility of the phase-type distributions enhances the flexibility and practicality of the systems. By virtue of these benefits, studies in reliability engineering can be more advanced than the previous studies. This study attempts to solve a redundancy allocation problem (RAP) by using these new models. The implications of mixing components, redundancy levels, and redundancy strategies are simultaneously considered to maximize the reliability of a system. An imperfect switching case in a standby redundant system is also considered. Furthermore, the experimental results for a well-known RAP benchmark problem are presented to demonstrate the approximating error of the previous reliability function for a standby redundant system and the usefulness of the current research.

A Fault-Tolerant System is necessary to improve the reliability of digital circuits with the presence of Fault Injection and also improves the system performance with better Fault Coverage. In this work, an efficient Transient Fault-Injection system (FIS) and Fault-Tolerant System (FTS) are designed for digital circuits. The FIS includes Berlekamp Massey Algorithm (BMA) based LFSRs, with fault logic followed by one – hot-encoder register, which generates the faults. The FTS is designed using Triple-Modular-Redundancy (TMR) and Dual Modular- Redundancy (DMR). The TMR module is designed using the Majority Voter Logic (MVL), and DMR is designed using Self-Voter Logic (SVL) for digital circuits such as synchronous and asynchronous circuits. The four different MVL approaches are designed in the TMR module for digital circuits. The FIS-FTS module is designed on Xilinx-ISE 14.7 environment and implemented on Artix-7 FPGA. The synthesis results include chip area, gate count, delay, and power are analyzed along with fault tolerance, and coverage for given digital circuits. The fault tolerance is analyzed using Modelsim-simulator. The FIS-FTS module covers an average of 99.17% fault coverage for both synchronous and asynchronous circuits.

Deep Neural Networks (DNNs) have attracted mainstream adoption in various application domains. Their reliability and security are therefore serious concerns in those safety-critical applications such as surveillance and medical systems. In this paper, we propose a novel dual modular redundancy framework for DNNs, namely D2NN, which is able to tradeoff the system robustness with overhead in a fine-grained manner. We evaluate D2NN framework with DNN models trained on MNIST and CIFAR10 datasets under fault injection attacks, and experimental results demonstrate the efficacy of our proposed solution.

The feasibility of persistent fault analysis relies on special faults which can persist in all the rounds of block ciphers. This prerequisite can be positioned as a good fit into the FPGA scenario, which however has not been carefully exploited ever before. In this paper, we propose the persistent fault attack on the block cipher AES-128 implemented in FPGA where a new type of persistent fault is induced with the technique of Block RAM (BRAM) modification. The details of persistent fault injection are elaborated, especially on how the target bits of AES in BRAM can be identified and how they can be altered. Our experimental results show that: with the proposed attack, a simple statistical analysis can extract the secret key of AES-128 with S-Box implemented in BRAMs and protected by the countermeasure of inversive decryption based dual modular redundancy.

We evaluated soft-error tolerance by heavy ions on several types of flip flops (FFs) called transmission-gate FF (TGFF), Dual Interlocked Storage Cell FF (DICEFF), Bistable Cross-coupled Dual Modular Redundancy FF (BCDMRFF) and BCDMRFF with Set and Reset (BCDMRFFSR) in a 65 nm bulk process. Radiation-hardened FFs are stronger against soft errors than a standard TGFF by two or three order of magnitude. DICEFF has higher soft-error tolerance than BCDMRFF by low-LET heavy ions less than 40 MeV-cm2/mg, while BCDMRFF is stronger against soft error than DICEFF by high-LET ions over 40 MeV-cm2/mg. DICEFF becomes weaker by lowering supply voltage, while BCDMRFF has higher soft-error tolerance than DICEFF when supply voltages is less than 1.0 V.

High-performance superscalar processors have been adopted to satisfy the rising demand for processing applications of ever-growing complexity. This extra complexity, added to the increasing vulnerability of transistors due to technology scaling, poses a great challenge since these effects have also been proven to affect ground-level safety-critical applications. To increase microarchitectural resilience, designers may adopt Dual Modular Redundancy (DMR), which offers full fault detection. However, given that DMR incurs in high area and energy overheads, we propose a design-time methodology aiming to achieve the best tradeoff between resilience and area overhead, decreasing DMR costs and maintaining acceptable detection levels for such a complex design. This is done by adopting the Knapsack Problem (KSP) as a heuristic to identify the optimal micro-architectural structures that should be duplicated to achieve target resilience with the smallest possible area overhead. By injecting over 800k faults in 12 significant micro-architectural structures of different versions of the complex Berkeley Out-of-Order Machine (BOOM) superscalar processor modeled with RTL accuracy, we compare this optimal strategy against a greedy one, showing that 90% of vulnerability reduction may be achieved with 50.6% and 107.8% area overheads for the optimal and greedy strategies, respectively.

Spin transfer torque (STT-RAM) is a fast, scalable and non-volatile memory technology. These characteristics make STT-RAM one of the best candidates among memories that can be used for space applications. Although STT-RAM cell itself is immune to high energy particles, its sensing circuit might be severely affected by radiation. In this work, we first extensively analyze the effect of radiation on the STT-RAM sense circuit and then propose a radiation hardened circuit. Using a dual modular redundancy and a voting scheme, radiation susceptibility of the sense circuit is eliminated. The sense circuit is implemented in 45 nm CMOS technology. Simulation results show that the proposed circuit is immune to radiation pulses up to 400 Krad.

Cascaded Integrator-Comb filters are a popular choice of filter for use as an interpolator in FPGAs due to their efficient multiplierless design, such as within an on-board satellite communication module. Electronics in space have the problem of being highly susceptible to cosmic radiation, due to the lack of magnetosphere and therefore require some form of protection from Single Event Upsets (SEUs). General techniques exist such as Dual Modular Redundancy (DMR) and Triple Modular Redundancy (TMR), but these may not be desirable due to their large area overhead and power consumption cost. Proposed is a reduced length redundancy technique that offers variable protection for varying power and area resources that could be used with partial reconfiguration to provide dynamically adaptive SEU protection depending on the current environment.

This article presents Clover, a compiler-directed soft error detection and recovery scheme for lightweight soft error resilience. The compiler carefully generates soft-error-tolerant code based on idempotent processing without explicit checkpoints. During program execution, Clover relies on a small number of acoustic wave detectors deployed in the processor to identify soft errors by sensing the wave made by a particle strike. To cope with DUEs (detected unrecoverable errors) caused by the sensing latency of error detection, Clover leverages a novel selective instruction duplication technique called tail-DMR (dual modular redundancy) that provides a region-level error containment. Once a soft error is detected by either the sensors or the tail-DMR, Clover takes care of the error as in the case of exception handling. To recover from the error, Clover simply redirects program control to the beginning of the code region where the error is detected. The experimental results demonstrate that the average runtime overhead is only 26%, which is a 75% reduction compared to that of the state-of-the-art soft error resilience technique. In addition, this article evaluates an alternative technique called tail-wait, comparing it to Clover. According to the evaluation with the different processor configurations and the various error detection latencies, Clover turns out to be a superior technique, achieving 1.06 to 3.49 × speedup over the tail-wait.

To increase the reliability of a specific system, using redundant components is a common method which is called redundancy allocation problem (RAP). Some of the RAP studies have focused on k-out-of-n systems. However, all of these studies assumed predetermined active or standby strategies for each subsystem. In this paper, for the first time, we propose a k-out-of-n system with a choice of redundancy strategies. Therefore, a k-out-of-n series-parallel system is considered when the redundancy strategy can be chosen for each subsystem. In other words, in the proposed model, the redundancy strategy is considered as an additional decision variable and an exact method based on integer programming is used to obtain the optimal solution of the problem. As the optimization of RAP belongs to the NP-hard class of problems, a modified version of genetic algorithm (GA) is also developed. The exact method and the proposed GA are implemented on a well-known test problem and the results demonstrate the efficiency of the new approach compared with the previous studies.

Mixed redundancy strategies are generally used in cloud-based systems, with different node switch mechanisms from traditional fault-tolerant strategies. Existing studies often concentrate on optimizing a single strategy in cloud computing environment and ignore the impact of mixed redundancy strategies. Therefore, a model is proposed to evaluate and optimize the reliability and performance of cloud-based degraded systems subject to a mixed active and cold standby redundancy strategy. In this strategy, node switching is triggered by a continual monitoring and detection mechanism when active nodes fail. To evaluate the transient availability and the expected job completion rate of systems with such kind of strategy, a continuous-time Markov chain model is built on the state transition process and a numerical method is used to solve the model. To choose the optimal redundancy for the mixed strategy under system constraints, a greedy search algorithm is proposed after sensitivity analysis. Illustrative examples were presented to explain the process of calculating the transient probability of each system state and in turn, the availability and performance of the whole system. It was shown that the near-optimal redundancy solution could be obtained using the optimization method. The comparison with optimization of the traditional mixed redundancy strategy proved that the system behavior was different using different kinds of mixed strategies and less redundancy was assigned for the new type of mixed strategy under the same system constraint.

The present paper solves a redundancy allocation problem under reliability constraint. To improve the system reliability, use of redundancy, i.e., use of additional components above the minimum number of components required for the system to operate, is a common practice. But it increases the total cost of the system as well. Thus the problem of allocating redundancy to coherent systems with competing choices of system-components needs to be optimally resolved so that the cost of adding redundancy is minimized. In this paper the problem of redundancy allocation is solved by minimizing the total cost subject to meeting a pre-assigned reliability target. The decision variables here are the number of redundancies. The methodology developed here can be applied to any coherent system, simple or complex. The computational complexity increases with the increase in complexity of the system design. The methodology of solving the redundancy allocation problem developed here yields a deterministic optimal solution, which is a polynomial time solution of an established NP-hard problem. Numerical examples have been included to illustrate the method developed here. The sensitivity of the optimal solution, augmented system reliability and related cost of using redundancy has been studied with respect to the specified reliability targets. No assumption about the form of the component life distribution has been made in the study.

The present article models and examines k˅n systems, in particular Triple modular redundancy (2˅3) and 3˅5. The aim of the study is to derive mathematical models, which are used for determining the impact of structural redundancy (the number of channels n and the threshold of the quorum function k) on the reliability of the system. The probability of failure-free operation p and the Mean Time Between Failures (MTBF) are used as reliability indicators.

Radiation induced faults in digital systems have started gathering major attention in recent years due to increasing reliability concern for future technologies. For future technologies, multiple transient faults (MTF) originating from a single radiation hit are expected to occur more frequently. Further, due to continuous massive scaling in device geometry, a particle with moderate linear energy transfer (LET) values is expected to affect more than one module/device during striking. Additionally, incessant escalation in operating speed with evolution of technology has increased likelihood of multi-cycle transient (MCT) faults in digital circuits. This calls for novel solutions for concurrently tackling multi-cycle transient and multi-transient fault resiliency at a higher design abstraction level such as behavioral level. This paper proposes a novel approach for generating simultaneous multi-cycle transient and multiple transient fault resilient designs during high level synthesis (HLS) of application specific datapath processors using the framework of dual modular redundancy. Results of the proposed approach on benchmarks indicated generation of low cost MCT–MFT resilient designs during HLS within acceptable runtime.

WSN consists of a large number of sensor nodes randomly deployed, and, in many cases, it is impossible to replace sensors when a node failure occurs. Thus, applications tend to deploy more nodes than necessary to cope with possible node failures and to increase the network lifetime, which leads to create some sensing and communication redundancy. However, sensors in the same region, may collect and forward the same information, which will waste more energy. In this paper, we propose a distributed Lightweight Redundancy aware Topology Control Protocol (LRTCP) for wireless sensor networks. It exploits the sensor redundancy in the same region by dividing the network into groups so that a connected backbone can be maintained by keeping a minimum of working nodes and turning off the redundant ones. LRTCP identifies equivalent nodes in terms of communication based on their redundancy degrees with respect of some eligibility rules. Simulation results indicate that, compared with existing distributed topology control algorithms, LRTCP improves network capacity and energy efficiency.

Modularity in design for most mechanical systems can lead to higher reliability and reduction in cost for the design and build of the system. In this paper, the modular design of a new class of reconfigurable parallel robots is discussed. These robots can attain static redundancy without actuation redundancy and are ideal for applications that require fault tolerance and enhanced stiffness but may not necessarily require redundant actuation. Such applications can be found in the area of wing morphing for performance improvement. It is shown that a universal modular limb connectivity type exists that can be adopted for modular design of statically redundant parallel robots, regardless of the degree of static redundancy of the system. Additionally, the modular design approach is demonstrated through a case study for a morphing wing application.

As the demand for low-power and high-speed logic circuits increases, the design of differential flip-flops based on sense-amplifier (SAFF), which have excellent power and speed characteristics, has become more and more popular. Conventional SAFF (Con SAFF) and improved SAFF designs focus more on the improvement of speed and power consumption, but ignore their Single-Event-Upset (SEU) sensitivity. In fact, SAFF is more susceptible to particle impacts due to the small voltage swing required for differential input in the master stage. Based on the SEU vulnerability of SAFF, this paper proposes a novel scheme, namely cross-layer Dual Modular Redundancy (DMR), to improve the robustness of SAFF. That is, unit-level DMR technology is performed in the master stage, while transistor-level stacking technology is used in the slave stage. This scheme can be applied to some current typical SAFF designs, such as Con SAFF, Strollo SAFF, Ahmadi SAFF, Jeong SAFF, etc. Detailed HSPICE simulation results demonstrate that hardened SAFF designs can not only fully tolerate the Single Node Upset of sensitive nodes, but also partially tolerate the Double Node Upset caused by charge sharing. Besides, compared with the conventional DMR hardened scheme, the proposed cross-layer DMR hardened scheme not only has the same fault-tolerant characteristics, but also greatly reduces the delay, area and power consumption.

We will begin by a quick but thorough look at the effects of faults, errors and failures, caused by terrestrial neutrons originating from cosmic rays, on the terrestrial electronic systems in the variety of industries. Mitigation measures, taken at various levels of design hierarchy from physical to systems level against neutron-induced adverse effects, are then introduced. Challenges for retaining robustness under future technology development are also discussed. Such challenges in mitigation approaches are featured for SRAMs (Static Random Access Memories), FFs (Flip-Flops), FPGAs (Field Programmable Gate Arrays) and computer systems as exemplified in the following articles: (i) Layout aware neutron-induced soft-error simulation and fault tolerant design techniques are introduced for 6T SRAMs. The PNP layout instead of conventional NPN layout is proposed and its robustness is demonstrated by using the MONTE CARLO simulator PHITS. (ii) RHBD (Radiation-Hardened By Design) FFs hardened by using specially designed redundant techniques are extensively evaluated. BCDMR (Bistable Cross-Coupled Dual Modular Redundancy) FFs is proposed in order to avoid MCU (Multi-Cell Upset) impacts on FF reliability. Its robustness is demonstrated thorough a set of neutron irradiation tests. (iii) CGRA (Coarse-Grained Reconfigurable Architecture) is proposed for an FPGA-chip-level tolerance. Prototype CGRA-FPGA chips are manufactured and their robustness is demonstrated under alpha particle/neutron irradiation tests. (iv) Simulation techniques for failures in heterogeneous computer system with memory hierarchy consisting of a register file, an L1 cache, an L2 cache and a main memory are also proposed in conjunction with masking effects of faults/errors.

This paper presents a practical view of how to implement a Dual Modular Redundancy (DMR) scheme in a CPU-FPGA (Central Processing Unit — Field-Programmable Gate Array) heterogeneous platform-based monitoring system, which is also described. FPGAs in a monitoring system can be valuable resources when it is important to either have a reprogrammable system or fast response/acquisition rates when processing large volumes of data. On the other side, CPUs are affordable options for most other processing tasks. A heterogeneous platform is proposed and aims to achieve a reliable, however cost-effective solution. After this, the paper will focus on matters such as synchronization between units, data redundancy and self-monitoring schemes. The implemented design was thoroughly tested, showing effectiveness in terms of redundancy with improved reliability.