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Dynamic random access memory (DRAM) serves as a critical component in medical equipment. Given the exacting standards demanded by medical equipment products, manufacturers face pressure to improve their product quality. The electrical characteristics of these products are based on the resistance value of the DRAM components. Hence, the purpose of this study is to optimize the resistance value of DRAM components in medical equipment. We proposed a novel FMEA-TSTM-NNGA framework that integrates failure mode and effect analysis (FMEA), the two-stage Taguchi method (TSTM), neural networks (NN), and genetic algorithms (GA) to optimize the manufacturing process. Moreover, the proposed FMEA-TSTM-NNGA framework achieved a substantial reduction in experimental trials, cutting the required number by a factor of 85.3 when compared to the grid search method. Our framework successfully identified optimal manufacturing condition settings for the resistance values of DRAM components: Depo time = 27 s, Depo O2 flow = 151 sccm, ARC-LTO etch time = 43 s, ARC-LTO etch pressure = 97 mTorr, Ox-SiCO etch time = 91 s, Ox-SiCO gas ratio = 22%, and Polish time = 84 s. The results helped the case company improve the resistance value of DRAM components from 191.1 × 10−3 Ohm to 176.84 × 10−3 Ohm, which is closer to the target value of 176.5 × 10−3 Ohm. The proposed FMEA-TSTM-NNGA framework is designed to operate efficiently on resource-constrained, facilitating real-time adjustments to production attributes. This capability enables DRAM manufacturers to swiftly optimize product quality. [ABSTRACT FROM AUTHOR]

Many dynamic random-access memory (DRAM) manufacturing companies encounter significant resistance value deviations during the PVD sputtering process for manufacturing Ti thin films. These resistance values are influenced by the thickness of the thin films. Current mitigation strategies focus on adjusting film thickness to reduce resistance deviations, but this approach affects product structure profile and performance. Additionally, varying Ti thin film thicknesses across different product structures increase manufacturing complexity. This study aims to minimize resistance value deviations across multiple film thicknesses with minimal resource utilization. To achieve this goal, we propose the TSDTM-ANN-GA framework, which integrates the two-stage dynamic Taguchi method (TSDTM), artificial neural networks (ANN), and genetic algorithms (GA). The proposed framework requires significantly fewer experimental resources than traditional full factorial design and grid search method, making it suitable for resource-constrained and low-power computing environments. Our TSDTM-ANN-GA framework successfully identified an optimal production condition configuration for five different Ti thin film thicknesses: Degas temperature = 245 °C, Ar flow = 55 sccm, DC power = 5911 W, and DC power ramp rate = 4009 W/s. The results indicate that the deviation between the resistance values and their design values for the five Ti thin film thicknesses decreased by 86.8%, 94.1%, 95.9%, 98.2%, and 98.8%, respectively. The proposed method effectively reduced resistance deviations for the five Ti thin film thicknesses and simplified manufacturing management, allowing the required design values to be achieved under the same manufacturing conditions. This framework can efficiently operate on resource-limited and low-power computers, achieving the goal of real-time dynamic production parameter adjustments and enabling DRAM manufacturing companies to improve product quality promptly. [ABSTRACT FROM AUTHOR]

Using DNA as the next-generation medium for data storage offers unparalleled advantages in terms of data density, storage duration, and power consumption as compared to existing data storage technologies. To meet the high-speed data writing requirements in DNA data storage, this paper proposes a novel design for an ultra-high-density and high-throughput DNA synthesis platform. The presented design mainly leverages two functional modules: a dynamic random-access memory (DRAM)-like integrated circuit (IC) responsible for electrode addressing and voltage supply, and the static droplet array (SDA)-based microfluidic structure to eliminate any reaction species diffusion concern in electrochemical DNA synthesis. Through theoretical analysis and simulation studies, we validate the effective addressing of 10 million electrodes and stable, adjustable voltage supply by the integrated circuit. We also demonstrate a reaction unit size down to 3.16 × 3.16 μm2, equivalent to 10 million/cm2, that can rapidly and stably generate static droplets at each site, effectively constraining proton diffusion. Finally, we conducted a synthesis cycle experiment by incorporating fluorescent beacons on a microfabricated electrode array to examine the feasibility of our design. [ABSTRACT FROM AUTHOR]

The challenges associated with semiconductor are increasing because of the rapid changes in the semiconductor market and the extreme scaling of semiconductors, with some processes reaching their technological limits. In the case of gate dielectrics, these limitations can be overcome by adopting high-k metal gate (HKMG) architecture instead of the previously used poly silicon/silicon oxy-nitride (PSION) structure. However, implementing the HKMG in a conventional DRAM process degrades the gate oxide. Therefore, in this study, a shallow trench isolation (STI) technology was developed to improve the gate oxide reliability in gate first HKMG DRAM structures. A novel STI process was developed to prevent the reduction in the oxide growth that occurs when the STI seam (or void) generated during the STI gap fill process meets the low temperature gate oxide process of the HKMG with SiGe. With the spacer STI (S-STI) structure, the ALD spacer was formed in the STI space region before the STI gap fill process to control the position of the STI seam (or void). Thus, a favorable environment for the growth of the gate oxide was established under the reduced effect of STI seam, and the oxide reliability was improved while maintaining the original structure and processes of the HKMG DRAM. Various analyses confirmed that the reliability was enhanced without the inherent characteristics of the HKMG being affected. These results revealed that the STI integration technology introduced herein improves the oxide reliability of HKMG DRAM products and maintains their technological excellence for the various complex needs of a rapidly changing market.

RowHammer is a DRAM vulnerability that can cause bit errors in a victim DRAM row solely by accessing its neighboring DRAM rows at a high-enough rate. Recent studies demonstrate that new DRAM devices are becoming increasingly vulnerable to RowHammer, and many works demonstrate system-level attacks for privilege escalation or information leakage. In this work, we perform the first rigorous fine-grained characterization and analysis of the correlation between RowHammer and temperature. We show that RowHammer is very sensitive to temperature variations, even if the variations are very small (e.g., ±1 °C). We leverage two key observations from our analysis to spy on DRAM temperature: 1) RowHammer-induced bit error rate consistently increases (or decreases) as the temperature increases, and 2) some DRAM cells that are vulnerable to RowHammer exhibit bit errors only at a particular temperature. Based on these observations, we propose a new RowHammer attack, called SpyHammer, that spies on the temperature of DRAM on critical systems such as industrial production lines, vehicles, and medical systems. SpyHammer is the first practical attack that can spy on DRAM temperature. Our evaluation in a controlled environment shows that SpyHammer can infer the temperature of the victim DRAM modules with an error of less than ±2.5 °C at the 90th percentile of all tested temperatures, for 12 real DRAM modules (120 DRAM chips) from four main manufacturers.

Capacitorless DRAM architectures based on Back-End-of-Line (BEOL)-transistors are promising for long-retention, high-density and low-power 3D DRAM solutions due to its low leakage, operational flexibility, and monolithic integration capability. Different from classical silicon-based devices, in-depth studies on the performances of nanoscale multi-gate transistors (e.g., a-InGaZnO-FET) are still barely conducted for physical description, due to the complicated multi-gating principle, finite-size effects on transport, increased variation sources and enlarged parasitic effect. Hence, high-performance multi-nanoscale (down to $\sim ~50$ nm) dual-gate a-IGZO transistors are fabricated, and a physical compact model is developed based on the surface potential for dual-gated coupling and the disordered transport with finite-size-correction. The short channel behaviors on sub-threshold swing, mobility and threshold voltage are investigated, and contact effects are validated by the transfer-line method (TLM). Regarding the specific challenge of dual-gate alignment, possible misalignment and parasitic effects on multi-device fluctuations are important of large-scale circuit design and analyzed by TCAD simulations. Besides, the bias-temperature instability (BTI) has been comprehensively investigated. In awareness of the above effects, this model bridges fabrication-based material properties and structural parameters, assisting in a threshold fluctuation-resistant operation scheme for capacitorless multi-bit memory, showing a great potential in future monolithic integration circuit design using BEOL-transistor.

Dynamic random access memory (DRAM) serves as a critical component in medical equipment. Given the exacting standards demanded by medical equipment products, manufacturers face pressure to improve their product quality. The electrical characteristics of these products are based on the resistance value of the DRAM components. Hence, the purpose of this study is to optimize the resistance value of DRAM components in medical equipment. We proposed a novel FMEA-TSTM-NNGA framework that integrates failure mode and effect analysis (FMEA), the two-stage Taguchi method (TSTM), neural networks (NN), and genetic algorithms (GA) to optimize the manufacturing process. Moreover, the proposed FMEA-TSTM-NNGA framework achieved a substantial reduction in experimental trials, cutting the required number by a factor of 85.3 when compared to the grid search method. Our framework successfully identified optimal manufacturing condition settings for the resistance values of DRAM components: Depo time = 27 s, Depo O2 flow = 151 sccm, ARC-LTO etch time = 43 s, ARC-LTO etch pressure = 97 mTorr, Ox-SiCO etch time = 91 s, Ox-SiCO gas ratio = 22%, and Polish time = 84 s. The results helped the case company improve the resistance value of DRAM components from 191.1 × 10−3 Ohm to 176.84 × 10−3 Ohm, which is closer to the target value of 176.5 × 10−3 Ohm. The proposed FMEA-TSTM-NNGA framework is designed to operate efficiently on resource-constrained, facilitating real-time adjustments to production attributes. This capability enables DRAM manufacturers to swiftly optimize product quality.

The Pass Gate Effect (PGE), often referred to as adjacent cell interference, presents a significant challenge in dynamic random-access memory (DRAM). In this study, we investigate the impact of PGE and propose innovative solutions to address this issue in DRAM technology, employing 10 nm node technology with buried channel array transistors. To evaluate the efficacy of our proposals, we utilized SILVACO for simulating various DRAM configurations. Our approach centers on two key structural optimizations: the introduction of a spherical Shallow Trench Isolation (STI) and the incorporation of a silicon nitride (Si3N4) layer within the spherical STI structure. These optimizations were meticulously designed to mitigate the PGE by considering several factors that are highly influential in its manifestation. To validate our approach, we conducted comprehensive simulations, comparing the PGE factors of typical DRAM structures with those of our proposed configurations. The results of our analysis strongly support the effectiveness of our proposed structural enhancements in alleviating the PGE when contrasted with conventional DRAM structures. Remarkably, our optimizations achieved a remarkable 82.4% reduction in the PGE, marking a significant breakthrough in the field of DRAM technology. By addressing the PGE challenge and substantially reducing its impact, our research contributes to the advancement of DRAM technology, offering practical solutions to enhance data integrity and reliability in the era of 10 nm node DRAM. [ABSTRACT FROM AUTHOR]

High-grade gliomas are extremely fatal tumors, marked by severe hypoxia and therapeutic resistance. Autophagy is a cellular degradative process that can be activated by hypoxia, ultimately resulting in tumor advancement and chemo-resistance. Our study aimed to examine the link between autophagy markers' expression in low-grade gliomas (LGGs) and high-grade gliomas (HGGs). In 39 glioma cases, we assessed the protein expression of autophagy markers LC3B, SQSTM1/p62, and DRAM by immunohistochemistry (IHC) and the mRNA expression of the autophagy genes PTEN, PI3K, AKT, mTOR, ULK1, ULK2, UVRAG, Beclin 1, and VPS34 using RT-qPCR. LC3B, SQSTM1/p62, and DRAM expression were positive in 64.1%, 51.3%, and 28.2% of glioma cases, respectively. The expression of LC3B and SQSTM1/p62 was notably higher in HGGs compared to LGGs. VPS34 exhibited a significant differential expression, displaying increased fold change in HGGs compared to LGGs. Additionally, it exhibited robust positive associations with Beclin1 (rs = 0.768), UVRAG (rs = 0.802), and ULK2 (rs = 0.786) in HGGs. This underscores a potential association between autophagy and the progression of gliomas. We provide preliminary data for the functional analysis of autophagy using a cell culture model and to identify potential targets for therapeutic interventions. [ABSTRACT FROM AUTHOR]

In order to prove conformance to memory standards and bound memory access latency, recently proposed real-time DRAM controllers rely on paper and pencil proofs, which can be troubling: they are difficult to read and review, they are often shown only partially and/or rely on abstractions for the sake of conciseness, and they can easily diverge from the controller implementation, as no formal link is established between both. We propose a new framework written in Coq, in which we model a DRAM controller and its expected behaviour as a formal specification. The trustworthiness in our solution is two-fold: (1) proofs that are typically done on paper and pencil are now done in Coq and thus certified by its kernel, and (2) the reviewer's job develops into making sure that the formal specification matches the standards—instead of performing a thorough check of the mathematical formalism. Our framework provides a generic DRAM model capturing a set of controller properties as proof obligations, which all implementations must comply with. We focus on properties related to the assertiveness that timing constraints are respected, every incoming request is handled in bounded time, and the DRAM command protocol is respected. We refine our specification with two implementations based on widely-known arbitration policies—First-in First-Out (FIFO) and Time-Division Multiplexing (TDM). We extract proved code from our model and use it as a "trusted core" on a cycle-accurate DRAM simulator. [ABSTRACT FROM AUTHOR]

In this article, we introduce Flip-On-Chip, the first end-to-end tool that thoroughly examines the vulnerability of embedded DRAM against rowhammer bit flips. Our tool, Flip-On-Chip, utilizes DRAM address mapping information to efficiently and deterministically perform a double-sided RowHammer test. We evaluated Flip-On-Chip on two DRAM modules: 1) LPDDR2 and 2) LPDDR4. It is found that our proposed tool increases the number of bit flips by 7.34 % on LPDDR2 and by 99.97 % on LPDDR4, as compared to state-of-the-art approaches provided in the literature. Additionally, Flip-On-Chip takes into account a number of system-level parameters to evaluate their influence on triggering Rowhammer bit flips. [ABSTRACT FROM AUTHOR]

Many dynamic random-access memory (DRAM) manufacturing companies encounter significant resistance value deviations during the PVD sputtering process for manufacturing Ti thin films. These resistance values are influenced by the thickness of the thin films. Current mitigation strategies focus on adjusting film thickness to reduce resistance deviations, but this approach affects product structure profile and performance. Additionally, varying Ti thin film thicknesses across different product structures increase manufacturing complexity. This study aims to minimize resistance value deviations across multiple film thicknesses with minimal resource utilization. To achieve this goal, we propose the TSDTM-ANN-GA framework, which integrates the two-stage dynamic Taguchi method (TSDTM), artificial neural networks (ANN), and genetic algorithms (GA). The proposed framework requires significantly fewer experimental resources than traditional full factorial design and grid search method, making it suitable for resource-constrained and low-power computing environments. Our TSDTM-ANN-GA framework successfully identified an optimal production condition configuration for five different Ti thin film thicknesses: Degas temperature = 245 °C, Ar flow = 55 sccm, DC power = 5911 W, and DC power ramp rate = 4009 W/s. The results indicate that the deviation between the resistance values and their design values for the five Ti thin film thicknesses decreased by 86.8%, 94.1%, 95.9%, 98.2%, and 98.8%, respectively. The proposed method effectively reduced resistance deviations for the five Ti thin film thicknesses and simplified manufacturing management, allowing the required design values to be achieved under the same manufacturing conditions. This framework can efficiently operate on resource-limited and low-power computers, achieving the goal of real-time dynamic production parameter adjustments and enabling DRAM manufacturing companies to improve product quality promptly.

The rise of AI technology, the expansion of smart and connected devices, and the COVID‐19 global pandemic have driven a change in the nature of social interactions from face‐to‐face to contact‐free/remote, which has tremendously increased the demand for various semiconductor devices. However, scaling and performance improvement of semiconductor devices are becoming more difficult every year, and extensive studies have been conducted to overcome these technological roadblocks. This paper reviews the present state of semiconductor development and discusses several approaches to overcome these scaling and performance limitations. Additionally, the importance of collaboration and the related ecosystem is emphasized to strengthen the cooperation among semiconductor stakeholders and support further semiconductor development. [ABSTRACT FROM AUTHOR]

With the significant growth in modern computing systems, dynamic random access memory (DRAM) has become a power/performance/energy bottleneck in data-intensive applications. Both the power management mechanism and downscaling method face decreasing performance or difficulties in the smaller footprint of the DRAM capacitor. Since optimizing the circuit of sense amplifier (SA) is an efficient method to reduce energy consumption, we propose two single bitline load sense amplifier (SBLSA) circuits, i.e., a redundant voltage discharged SBLSA (RVD-SBLSA) circuit and a bit aware SBLSA (BA-SBLSA) circuit, to improve conventional and single bitline write (SBW) circuits. The RVD-SBLSA circuit utilizes a clamp diode to discharge redundant voltage over VDD/2 with an additional working stage. The BA-SBLSA circuit abandons the single bitline load (SBL) circuit during read and write '1' operations. The RVD-SBLSA circuit can offer the lowest total energy consumption, and the BA-SBLSA circuit can make a better balance between energy consumption and latency. Through the simulation results, the proposed circuits can efficiently reduce energy consumption or balance energy consumption and latency and show huge potentials in very large-scale integrated circuits. [ABSTRACT FROM AUTHOR]

Using DNA as the next-generation medium for data storage offers unparalleled advantages in terms of data density, storage duration, and power consumption as compared to existing data storage technologies. To meet the high-speed data writing requirements in DNA data storage, this paper proposes a novel design for an ultra-high-density and high-throughput DNA synthesis platform. The presented design mainly leverages two functional modules: a dynamic random-access memory (DRAM)-like integrated circuit (IC) responsible for electrode addressing and voltage supply, and the static droplet array (SDA)-based microfluidic structure to eliminate any reaction species diffusion concern in electrochemical DNA synthesis. Through theoretical analysis and simulation studies, we validate the effective addressing of 10 million electrodes and stable, adjustable voltage supply by the integrated circuit. We also demonstrate a reaction unit size down to 3.16 × 3.16 μm2, equivalent to 10 million/cm2, that can rapidly and stably generate static droplets at each site, effectively constraining proton diffusion. Finally, we conducted a synthesis cycle experiment by incorporating fluorescent beacons on a microfabricated electrode array to examine the feasibility of our design.

Classification of defect chip patterns is one of the most important tasks in semiconductor manufacturing process. During the final stage of the process just before release, engineers must manually classify and summarise information of defect chips from a number of wafers that can aid in diagnosing the root causes of failures. Traditionally, several learning algorithms have been developed to classify defect patterns on wafer maps. However, most of them focused on a single wafer bin map based on certain features. The objective of this study is to propose a novel approach to classify defect patterns on multiple wafer maps based on uncertain features. To classify distinct defect patterns described by uncertain features on multiple wafer maps, we propose a generalised uncertain decision tree model considering correlations between uncertain features. In addition, we propose an approach to extract uncertain features of multiple wafer maps from the critical fail bit test (FBT) map, defect shape, and location based on a spatial autocorrelation method. Experiments were conducted using real-life DRAM wafers provided by the semiconductor industry. Results show that the proposed approach is much better than any existing methods reported in the literature. [ABSTRACT FROM AUTHOR]

DRAM-NVM-based hybrid memory opens up a varied range of power-performance-area operational configurations through page migration between the high-performance DRAM and the reliable NVM. The amalgamation of two technologies requires various modifications for the existing monolithic DRAM-based systems. This paper summarizes the current research work in the areas of data placement and page migration in hybrid memories. The challenges and design solutions from a range of NVMs-PCM, STT-RAM, ReRAM is presented. This paper also identifies several research challenges in these areas. [ABSTRACT FROM AUTHOR]

The rapid proliferation of the Internet of Things and the dramatic resurgence of artificial intelligence based application workloads have led to immense interest in performing inference on energy-constrained edge devices. Approximate computing (a design paradigm that trades off a small degradation in application quality for disproportionate energy savings) is a promising technique to enable energy-efficient inference at the edge. This article introduces the concept of an approximate edge inference system (AxIS) and proposes a systematic methodology to perform joint approximations between different subsystems in a deep neural network (DNN)-based edge inference system, leading to significant energy benefits compared to approximating individual subsystems in isolation. We use a smart camera system that executes various DNN-based image classification and object detection applications to illustrate how the sensor, memory, compute, and communication subsystems can all be approximated synergistically. We demonstrate our proposed methodology using two variants of a smart camera system: (a) CamEdge, where the DNN is executed locally on the edge device, and (b) CamCloud, where the edge device sends the captured image to a remote cloud server that executes the DNN. We have prototyped such an approximate inference system using an Intel Stratix IV GX-based Terasic TR4-230 FPGA development board. Experimental results obtained using six large DNNs and four compact DNNs running image classification applications demonstrate significant energy savings (≈ 1.6×–4.7× for large DNNs and ≈ 1.5×–3.6× for small DNNs), for minimal (<1%) loss in application-level quality. Furthermore, results using four object detection DNNs exhibit energy savings of ≈ 1.5×–5.2× for similar quality loss. Compared to approximating a single subsystem in isolation, AxIS achieves 1.05×–3.25× gains in energy savings for image classification and 1.35×–4.2× gains for object detection on average, for minimal (<1%) application-level quality loss. [ABSTRACT FROM AUTHOR]

Multiple-channel field-effect transistors (MCFETs) switch the current among different channels in the FET based on the applied voltage in its gate terminal. MCFETs can be used to design a multivalued logic circuit with the lowest number of circuit elements. Different MCFET logic circuits and unipolar inverters are now considered to be an option to follow Moore's law. However, many details about the performance of MCFET in different logic circuit applications are in the research phase. In this paper, a circuit model of MCFET based on Verilog-A has been developed and a circuit for multivalued dynamic random-access memory (DRAM) is designed. [ABSTRACT FROM AUTHOR]

This article describes a dual-controller dual-delay line delay lock loop (DC-DL DLL). The proposed DLL adopted a dual delay line structure, each delay line was composed of a coarse adjustment and a fine adjustment unit, and the dual delay lines had corresponding control units to reduce the mismatch between the delay lines, and it avoided the complicated design of duty cycle correction (DCC) circuit. A frequency divider was added to divide the input clock to achieve a wider input clock duty cycle adjustment. Additionally, a simple clock synthesis circuit was proposed to synthesize the required clock. The DLL design used the 25 nm process with a voltage of 1.2 V. The simulation results showed that at a working frequency of 1.6 GHz, the peak-to-peak jitter of the DC-DL DLL after locking was approximately 17.61 ps, the maximum output duty cycle error was about 1.3%, and the input duty cycle ranged from 20% to 80%, with a power consumption of 10.06 mW. [ABSTRACT FROM AUTHOR]

DRAM scalability is becoming a limiting factor to the available memory capacity in consumer devices. As a potential solution, manufacturers have introduced emerging non-volatile memories (NVMs) into the market, which can be used to increase the memory capacity of consumer devices by augmenting or replacing DRAM. In this work, we provide the first analysis of the impact of extending the main memory space of consumer devices using off-the-shelf NVMs. We equip real web-based Chromebook computers with the Intel Optane solid-state drive (SSD), which contains state-of-the-art low-latency NVM, and use the NVM as swap space. We analyze the performance and energy consumption of the Optane-equipped Chromebooks, and compare this with (i) a baseline system with double the amount of DRAM than the system with the NVM-based swap space; and (ii) a system where the Intel Optane SSD is naively replaced with a state-of-the-art NAND-flash-based SSD. Our experimental analysis reveals that while Optane-based swap space provides a cost-effective way to alleviate the DRAM capacity bottleneck in consumer devices, naive integration of the Optane SSD leads to several system-level overheads, mostly related to (1) the Linux block I/O layer, which can negatively impact overall performance; and (2) the off-chip traffic to the swap space, which can negatively impact energy consumption. To reduce the Linux block I/O layer overheads, we tailor several system-level mechanisms (i.e., the I/O scheduler and the I/O request completion mechanism) to the currently-running application’s access pattern. To reduce the off-chip traffic overhead, we leverage an operating system feature (called Zswap) that allocates some DRAM space to be used as a compressed in-DRAM cache for data swapped between DRAM and the Intel Optane SSD, significantly reducing energy consumption caused by the off-chip traffic to the swap space. We conclude that emerging NVMs are a cost-effective solution to alleviate the DRAM capacity bottleneck in consumer devices, which can be further enhanced by tailoring system-level mechanisms to better leverage the characteristics of our workloads and the NVM.

Total ionizing dose (TID) effects of gamma rays were investigated on DDR4 dynamic random access memory (DRAM) and analyzed using TCAD simulations. In this study, we considered the operating states, dose rates, temperatures, and annealing to analyze the impact of TID under different conditions. The worst degradation was observed in the operated state and at a low-dose rate because of the absence of an electrostatic barrier that reduced the possibility of interface trap formation under unbiased and high-dose rate conditions. At lower temperatures, the effects of radiation were mitigated by the reduced production of protons ( $\text{H}^{+}$ ). In addition, the unbiased DRAM and high-temperature conditions are the fastest to recover during post-irradiation annealing. In TCAD simulations, the retention time decreased with increasing temperature because the band-to-band tunneling (BTBT) generation increased. Furthermore, the retention time and row activation latency ( $t_{\mathrm {RCD}}$ ) degraded as the concentration of the interface traps increased. This is because the interface traps caused leakage currents and hindered the flow of electrons.

A novel memory cell transistor structure based on a saddle fin-based DRAM is presented for highly reliable operations. The overhang saddle fin (oss-fin) active structure is formed by two steps of etching of the fin; isotropic etching for the short side and anisotropic etching for the long side of the fin. The overhang sidewall fin structure results in the increase of retention time, decrease of isolation leakage current, increase of rowhammering tolerance, and increase of programming efficiency. A Technology Computer-Aided Design (TCAD) simulation study compares the overhang and the conventional saddle fin (s-fin) in terms of those reliability parameters. A lowered electric field underneath the storage node, a lowered passing gate coupling capacitance, and an elongated isolation leakage path are attributed to the reliability enhancements in the overhang saddle fin.

As the demand for transformer applications increases rapidly, technologies to solve memory bottlenecks are attracting attention. One of them is an in-DRAM Processing-In-Memory (PIM) architecture to perform the computation inside DRAM. Major DRAM makers introduce the PIM samples, executing all banks’ computations simultaneously to maximize the internal DRAM bandwidth for achieving the highest performance. However, the realization as a commercial product is problematic since the all-bank execution does not concurrently perform non-PIM applications during the PIM execution with PIM memory, thus separating their memory space. This paper proposes a BL-PIM architecture to increase the burst length (BL) of memory requests inside a bank to maximize internal bandwidth and overlap the computation across banks, thus achieving all-bank performance. On the other hand, outside a bank, it seems not to increase the BL, thus allowing us to preserve the data consistency in memory hierarchy and execute non-PIM and PIM applications together with PIM memory. Also, the memory-intensive PIM computation using larger BL significantly reduces their outstanding memory requests, thus minimizing the performance interference with other applications. We carefully extend the DRAM timing diagram and develop the cooperation mechanism between a memory controller and a PIM device. We implemented the BL-PIM architecture on FPGA and compared the performance with real machines using four transformer models and eight compute and memory-bound SPEC benchmarks. We achieved the BL-PIM performance up to 28.9x and 12.0x faster than the CPU single-thread and multi-threaded execution in the transformer models. Also, when we increased the burst length by 16 times as the maximum, the BL-PIM was 1.2x faster than the ideal all-bank PIM execution. We also experimented with the multi-workload execution using the SPEC benchmarks, showing that our architecture can minimize performance interference. To our knowledge, the study of the PIM’s multi-workload execution is the first in public.

Modern DRAM devices’ performance and energy efficiency are significantly improved when the row-buffer locality is exploited properly. In multi-core architectures, however, the DRAM-based main memory banks used by the processing units, called cores, are shared. Memory interference, also known as memory contention, occurs when many cores contend for simultaneous access to the shared banks. The performance benefits provided by utilizing the available row-buffer locality are diminished by the increased memory contention brought on by the integration of more cores. Large DRAM page sizes are therefore activated in order to access only a tiny amount of data. Poor energy efficiency or wasted opportunity to loosen DRAM power timing restrictions are both downsides to this page over-fetching issue. This study introduces a Fine-Grained Activation (FGA) technique to reduce the number of involved bitlines when accessing DRAM memory. This technique significantly improves the parallelism at the DRAM subarray level to support multiple memory accesses routed to distinct subarrays inside the same memory bank. The FGA technique presented in this research intends to provide large energy savings while simultaneously delivering significant performance gains. Our evaluation findings with 4-core multi-program benchmarks demonstrate that the FGA technique proposed in this paper can significantly improve both DRAM performance and DRAM energy efficiency with a negligible area overhead. In comparison to the baseline, the Half-DRAM page activation mechanism, and the recently suggested FGA mechanism, the proposed technique in this study reduces the average DRAM memory access latency for the evaluated four-core applications by 25.6%, 27.1%, and 14.8%, respectively. Our introduced technique also decreases the DRAM activation power by an average of 46.7%, 27.1%, and 14.7%, respectively, when compared with the baseline, Half-DRAM technique, and the recently proposed FGA mechanism.

In response to the increasing manufacturing complexity/cost in maintaining DRAM advancements through traditional scaling, three-dimensional integrated circuits (3D ICs) and 2.5-dimensional ICs with Si interposers are known as promising candidates to overcome these challenges due to their advantages of low power, small form factor, high density, and high bandwidth. In this work, we present a true process-heterogeneous stacked embedded DRAM (SeDRAM) using hybrid bonding 3D integration process, achieving high bandwidth of 34 GBps/Gbit and high energy efficiency of 0.88 pJ/bit. Moreover, the critical factors of the SeDRAM design are presented (e.g., the low data movement energy, high-density physical interface, simplified protocol definition, process compatibility, density extensibility, and hybrid bonding connection fast test by DFT (design for test). Our results and design methodology have paved the way to realize applications of hybrid bonding to high bandwidth and energy efficiency DRAM. More importantly, the SeDRAM solution can also support the maximum storage density of 48 Gbit and the bandwidth capability of TBps. It can greatly alleviate the "memory wall" problem and thus improve its competitiveness in near-memory computing/computing-in-memory fields. [ABSTRACT FROM AUTHOR]

This paper presents a capacitorless memory cell with bulk CMOS compatibility, consisting of a MOSFET with a virtual floating body formed by the trench. The name Key shape Floating Body Memory (KFBM) is derived from the resemblance of the structure to the shape of an antique key. The carrier concentration in the vertical device beneath the MOSFET results in over more than 5 orders of magnitude of the on–off cell current ratio with off-current less than 100pA/cell. The device achieves a retention time of about 1 s at 85C and over 10 s at 27C all the while maintaining high density and scalability. On the basis of TCAD simulation we have demonstrated high tolerance to disturbance (more than 1000 times with all types of signals), which has been an issue with DRAM memories. KFBM can incorporate both dynamic RAM and flash features.

In-memory computing is an alternative method to effectively accelerate the massive data-computing tasks of artificial intelligence (AI) and break the memory wall. In this work, we propose a 2T1C DRAM structure for in-memory computing. It integrates a monolayer graphene transistor, a monolayer MoS2 transistor, and a capacitor in a two-transistor-one-capacitor (2T1C) configuration. In this structure, the storage node is in a similar position to that of one-transistor-one-capacitor (1T1C) dynamic random-access memory (DRAM), while an additional graphene transistor is used to accomplish the non-destructive readout of the stored information. Furthermore, the ultralow leakage current of the MoS2 transistor enables the storage of multi-level voltages on the capacitor with a long retention time. The stored charges can effectually tune the channel conductance of the graphene transistor due to its excellent linearity so that linear analog multiplication can be realized. Because of the almost unlimited cycling endurance of DRAM, our 2T1C DRAM has great potential for in situ training and recognition, which can significantly improve the recognition accuracy of neural networks.