120 results on '"Doria, Rodrigo T."'
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2. Influence of interface traps position along channel in the low-frequency noise of junctionless nanowire transistors
3. Electrical parameters and low-frequency noise of AlGaN/GaN high-electron mobility transistors with different channel orientation
4. Junctionless nanowire transistors effective channel length extraction through capacitance characteristics
5. Interface traps density extraction through transient measurements in junctionless transistors
6. Influence of interface traps density and temperature variation on the NBTI effect in p-Type junctionless nanowire transistors
7. Thermal cross-coupling effects in side-by-side UTBB-FDSOI transistors
8. Suitability of applying ultrathin SOI‐based PIN diodes to photodetection of UV wavelength
9. Junctionless nanowire transistors parameters extraction based on drain current measurements
10. Characterization of Switching Properties in ReRAM Devices by the Capacitance of the MIM Structure.
11. Optimizing RF Energy Harvesting Systems for IoT Applications using Reinforcement Learning
12. Experimental Analysis of HfO2/X ReRAM devices by the Capacitance Measurements
13. Analysis of Standard-MOS and Ultra-Low-Power Diodes Composed by SOI UTBB Transistors
14. Standard MOS Diodes Composed by SOI UTBB Transistors
15. Junctionless Nanowire Transistor for Analog Applications: Cascode Current Mirror Configuration
16. Variability Modeling in Triple-Gate Junctionless Nanowire Transistors
17. Lateral PIN Photodiode with Germanium and Silicon Layer on SOI Wafers.
18. Ultra-Low-Power Diodes Composed by SOI UTBB Transistors
19. SOI UTBB Capacitive Cross-Coupling Effects in Ultimate Technological Nodes
20. Junctionless Nanowire Transistors Based Wilson Current Mirror Configuration
21. Junctionless Nanowire Transistors Based Common-Source Current Mirror
22. Modeling Schottky Diode Rectifiers Considering the Reverse Conduction for RF Wireless Power Transfer
23. On the Application of Junctionless Nanowire Transistors in Basic Analog Building Blocks
24. Drain Current and Short Channel Effects Modeling in Junctionless Nanowire Transistors
25. The Roles of the Gate Bias, Doping Concentration, Temperature and Geometry on the Harmonic Distortion of Junctionless Nanowire Transistors Operating in the Linear Regime
26. Origin of the Low-Frequency Noise in the Asymmetric Self-Cascode Structure Composed by Fully Depleted SOI nMOSFETs
27. Impact of the Series Resistance in the I-V Characteristics of Junctionless Nanowire Transistors and its dependence on the Temperature
28. Analog Operation Temperature Dependence of nMOS Junctionless Transistors Focusing on Harmonic Distortion
29. Thermal Cross-Coupling Effects Analysis in UTBB Transistors
30. Effect of Interface Traps on the RTS Noise Behavior of Junctionless Nanowires
31. Correlation between the NBTI Effect and the Surface Potential and Density of Interface Traps in Junctionless Nanowire Transistors
32. Analysis of the Thermal Properties of Self-Cascode Structures Composed by UTBB Transistors
33. Modeling Schottky Diode Rectifiers Considering the Reverse Conduction for RF Wireless Power Transfer.
34. Linearity Analysis in Double Gate Graded-Channel Soi Devices Applied to 2-Mos Mosfet-C Balanced Structures
35. Harmonic Distortion Analysis of SOI Triple Gate FinFETs Applied to 2-MOS Balanced Structures
36. Fin Width Influence on The Harmonic Distortion of Standard and Strained FinFETs Operating in Saturation
37. An Analytical Model for the Non-Linearity of Triple Gate SOI MOSFETs
38. Analysis of the substrate effect by the capacitive coupling in SOI UTBB Transistors
39. UTBB MOSFETs Thermal Coupling Analysis in Technological Node Level.
40. Analysis of the Output Conductance Degradation With the Substrate Bias in SOI UTB and UTBB Transistors
41. Adaption of triple gate junctionless MOSFETs analytical compact model for accurate circuit design in a wide temperature range
42. Lateral spacers influence on the effective channel length of junctionless nanowire transistors
43. A new method for junctionless transistors parameters extraction
44. Effect of the back bias on the analog performance of standard FD and UTBB transistors-based self-cascode structures
45. Analysis of p-type Junctionless nanowire transistors with different crystallographic orientations
46. Analysis of the substrate bias effect on the thermal properties of SOI UTBB transistors
47. Substrate Effect Evaluation by the Analysis of Intrinsic Capacitances in SOI UTBB Transistors.
48. Influence of the crystal orientation on the operation of junctionless nanowire transistors
49. Physical insights on the dynamic response of junctionless nanowire transistors
50. A new series resistance extraction method for junctionless nanowire transistors
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