Search

This paper presents a low-random noise of 2.6 e-rms, a low-power of 116.2 mW at video rate, and a high-speed up to 960 fps 2-mega pixels global-shutter type CMOS image sensor (CIS) using an advanced DRAM technology. To achieve a high performance global-shutter CIS, we proposed a novel architecture for the digital pixel sensor which is a remarkable global-shutter operation CIS with a pixel-wise ADC and an in-pixel digital memory. Each pixel has two small-pitch Cu-to-Cu interconnectors for the wafer-level stacking, and the pitch of each unit pixel is less than 5 μm which is the world’s smallest pixel embedding both pixel-level ADC and 22-bit memories.

This paper reports a 1280×960 DVS. A 4.95-μm pixel pitch is achieved with in-pixel Cu-Cu connection and the newly designed GIDL-suppression scheme. A sequential column selection scheme and a global event-holding function are implemented to minimize motion artifacts. The power consumption per pixel of 122 nW is 1.25× smaller and the maximum readout speed of 1.3 Geps is 4.33× faster than the previous state-of-the-art.

As the automotive and AI industries are expanding rapidly, global-shutter (GS) image sensors are playing a more significant role in the perception system. More specifically, GS image sensors are required in various fields involving IR, including the face-ID in mobile devices, the driver monitoring system in automotive applications, and factory automation. GS image sensors are necessary for these applications because they can capture freeze-frame images without motion distortion due to their advantage in the pixel operation method. The simultaneous pixel exposure and in-pixel storing capability allow GS image sensors to achieve high-quality imaging, while the sequential pixel exposure and readout of rolling-shutter (RS) image sensors results in image distortion known as the jello effect. For mobile and automotive applications, a small form factor while maintaining a low parasitic light sensitivity (PLS) and low noise is crucial. In conventional backside illuminated (BSI) charge-domain GS image sensors, a light-shielding structure over the storage area must be formed in order to suppress the influence of parasitic light during the readout operation. Therefore, the introduction of such a light-shielding structure reduces the effective photodiode area, which results in a loss of full-well capacity (FWC), light sensitivity of the sensor, and pixel scalability.

As the smart mobile device market continues to grow and the number of cameras per device rapidly increases, demand for CMOS image sensors (CIS) also increases. Two major trends in mobile device cameras are: (1) adopting smaller pixels that enable greater pixel count at similar optical format, and (2) bigger pixels for higher image quality. To be more specific, front-facing cameras have a trend towards smaller pixels, while rear main cameras have a trend towards both smaller and bigger pixels. The optical format of front-facing cameras is especially limited due to existing bezel-less or border-less display designs, yet higher resolution still-shot and video (such as 4K UHD) recording is desired. To implement greater pixel count in a limited camera module size, scaling of pixel size is required. The main challenges are to maintain acceptable photodiode full-well capacity (FWC) and sensitivity, while suppressing optical crosstalk [1]. To completely eliminate both electrical and optical crosstalk, deep-trench isolation (DTI) has evolved from early BDTI (Back-side DTI) to current FDTI (Front-side DTI) technology, which is also called full-depth DTI. In this paper, a 44Mpixel CIS with 0.7µm pixels using full-depth DTI is demonstrated.

Backside illuminated CMOS image sensors with a 3D stacked architecture, where the pixel array is attached on top of the logic circuit, was introduced and have just come to the market. Image sensor featuring 3D stacking was realized by connection between the interconnect layers of the top and bottom parts using vertical type through-silicon via (TSV).1 Cu bonding technology for 3D integration has been studied and widely applied.2As Wafer-to-wafer bonding process is now being used widely and matured through the production of Backside illuminated CMOS image sensors, Copper-copper bonding provides an attractive route to 3D stacked image sensor since it creates a strong metal bond and enables vertically electrical connection during the bonding process. Specific pre-bonding surface conditioning is necessary to insure high bonding quality of patterned Cu wafers using Cu-Cu non-thermo compression bonding for wafer-to-wafer 3D stacking. Surface preparations for the hybrid fusion bonding such as removal of Cu oxide, Cu surface protection and optimized CMP planarization patterned Cu surfaces have been studied,3 but the study on plasma condition for hybrid fusion bonding is relatively a few. The work described here is investigating of the plasma-related Cu patterned hybrid surface preparation under different plasma conditions. The main physical mechanisms about Cu-Cu non thermal compression bonding are spontaneous adhesion of hydrophilic surfaces followed by Cu diffusion across the bonding interface when Cu-Cu contact is reached (diffusion bonding) have been previously reported.4 The property of Cu dielectric diffusion barriers used in ULSI is hydrophobic. For the efficient bonding of hydrophobic-hydrophobic layers, surface conversion process is introduced.5 In the case of Cu-patterned hybrid bonding in typical Cu metallization layer in ULSI, Trade-off between dielectric diffusion barrier and Cu cannot be avoidable by surface conversion process. During the Cu-patterned hybrid bonding development, the common electrical failed areas were found. To investigate the failure mechanism, influence of plasma condition on the activation of wafer surface and bonding quality was studied. The wafer surface was examined by X-ray photoelectron spectroscopy (XPS), surface roughness, and observation of differential work function uniformity over a full wafer area caused by plasma-induced charge.6The ChemetriQ NVD inspection system from Qcept Technologies was used to inspect differential work function uniformity. After implementing plasma treatment applied in bonding process, Non-uniformity of a charge map and different plasma influence over a full wafer area were shown, even there was no difference through the AFM analysis. For the optimization of the bonding process, especially plasma process, a method to examine the surface condition in this paper makes it possible to monitor the plasma process and improve bonding process References: [1] S. Sukegawa et al., “A 1/4-inch 8Mpixel Back-Illuminated Stacked CMOS Image Sensor” ISSCC, pp 484-485, 2013 [2] Y. Tang et al.,“Wafer-level Cu–Cu bonding technology” Microelectronics Reliability. 52 (2) pp312-320, 2012 [3] B. Rebhan et al.,“Low-Temperature Cu-Cu Wafer Bonding” ECS Transactions, 50 (7) pp139-149, 2013. S. Farrens et al., “Metal Surface Preparation with Point of Use Wet Chemistry” ECS Transactions, 33 (4) pp17-26, 2010. D. F. Lim et al., “Surface Passivation of Cu for Low Temperature 3D Wafer Bonding” ECS Solid State Lett. 1 (1) pp11-14, 2012, L. D. Cioccio et al., “An Overview of Patterned Metal / Dielectric Surface Bonding: Mechanism, Alignment and Characterization” ECS Transactions, 33 (4) pp3-16, 2010 [4] P. Gueguen et al., “Copper Direct Bonding: an innovative 3D interconnect” presented at ECTC 2010 [5] A.Usenko et al., “Silicon Nitride Surface Conversion into Oxide to Enable Hydrophilic Bonding” ECS Transactions, 33 (4) pp475-483, 2010 [6] R. Spicer et al., “Controlling Process-Induced Heightens Productivity” Semiconductor International March pp2-6, 2009

Techniques to reduce random noise in complementary metal oxide semiconductor (CMOS) image sensor chips with pixel sizes as small as 2.2 ×2.2 µm2 are addressed. By applying dummy heat annealing and plasma nitrided (PN) oxide, random noise can be reduced by more than 40%. Measured results indicate that the gate oxide–Si interface is improved by a dummy heat treatment, and PN oxide is a good choice as a gate oxide for image sensors, since it has an optimal nitrogen profile as a gate oxide while it effectively suppresses boron penetration. The results show the importance of nitrogen profile control in gate oxides and of oxide curing for low noise characteristics in CMOS image sensors.

A novel tandem iodocyclization has been achieved by the regioselective ring-opening of epoxide and by the following intramolecular 1,4-cycloaddition of α,β-unsaturated ester with catalytic amount of SmI 2 and I 2 (1.2-2.5equivalent) under mild and neutral reaction conditions.

Various epoxy esters readily reacted with SmI 2 (2 equiv) in the presence of ethyl bromoacetate (1 equiv) and HMPA (6 equiv) under mild conditions (THF, −78 °C, 2 h, Ar) providing the corresponding γ-lactones via tandem epoxide opening-cyclization reaction in good to excellent yields.

We demonstrate a new postmetallization annealing and ultraviolet (UV) treatment process for reducing the dark current of image sensors. The new method utilizes a large amount of hydrogen in a plasma-silicon nitride film (p-SiNx) as a hydrogen diffusion source. Through charge pumping measurement, it is proved that this method effectively reduces the interface trap density of pixel transistors, thereby decreasing the dark current of image sensors. Although the postetch process for removing p-SiNx films induces plasma damage during the etch step, the damage can be effectively cured by the subsequent UV annealing.

Plasma doping (PLAD) was applied to reduce the dark current of CMOS image sensor (CIS), for the first time. PLAD was employed around shallow trench isolation (STI) to screen the defective sidewalls and edges of STI from the depletion region of photodiode. This technique can provide not only shallow but also conformal doping around the STI, making it a suitable doping technique for pinning purposes for CISs with sub-2-mum pixel pitch. The measured results show that temporal noise and dark signal deviation as well as dark level decrease

Regio- and stereoselective iodinative cleavage of 2′,3′-anhydropurine nucleosides was achieved with samarium diiodide and ethyl bromoacetate to produce the corresponding 3′-iodopurine nucleosides, which were then converted to 3′-deoxypurine nucleosides including the natural product cordycepin.

A new SmI2-promoted intramolecular reductive cyclization of β-(α-bromo siloxy) carbonyl compounds is reported.

In this work we present a CMOS-compatible self-aligning process for the large-scale-integration of high-performance nanowire field effect transistors with well-saturated drain currents, steep subthreshold slopes at low drain voltage and a large on/off current ratio (>10(7)). The subthreshold swing is as small as 45 mV/dec, which is substantially beyond the thermodynamic limit (60 mV/dec) of conventional planar MOSFETs. These excellent device characteristics are achieved by using a clean integration process and a device structure that allows effective gate-channel-source coupling to tune the source/drain Schottky barriers at the nanoscale.

Various epoxy esters readily reacted with SmI 2 (2 equiv) in the presence of ethyl bromoacetate (1 equiv) and HMPA (6 equiv) under mild conditions (THF, −78 °C, 2 h, Ar) providing the corresponding γ-lactones via tandem epoxide opening-cyclization reaction in good to excellent yields.

Technology and characteristics of 8-mega density CMOS image sensor (CIS) with unit pixel size of 1.75times1.75mum2 are introduced. With recessed transfer gate (RTG) structure and other sophisticated process/device technology, remarkably enhanced saturation capacity and ultra-low dark current have been obtained, which satisfy the requirements of high density digital still camera (DSC) application

5 mega CMOS image sensor with 1.9mum-pitch pixels has been implemented with 0.13 mum low power CMOS process. By applying 4-shared pixel architecture, 2.5V operation voltage, and tight design rules for some critical layers in pixels, high fill factor and the corresponding high saturation could be obtained. Image lag was sufficiently suppressed by pulse-boosting of transfer gate voltage and electrical cross-talk was suppressed by use of n-type epitaxial layer. It is shown that several sophisticated processes improve sensitivity, temporal random noise, and dark current. With this technology, full 5-mega density CMOS image sensor chips have been successfully developed

A novel tandem iodocyclization has been achieved by the regioselective ring-opening of epoxide and by the following intramolecular 1,4-cycloaddition of α,β-unsaturated ester with catalytic amount of SmI 2 and I 2 (1.2-2.5equivalent) under mild and neutral reaction conditions.

In this study, a method for deriving the tensile flow characteristics of austenitic materials from an instrumented indentation technique is presented along with its experimental verification. We proposed a modified algorithm for austenitic materials that takes their hardening behaviour into account. First, the true strain based on sine function instead of tangent function was adapted. It was proved that the sine function shows constant degrees of hardening which is a main characteristic of the hardening of austenitic materials. Second, a simple and linear constitutive equation was newly suggested to optimize indentation flow curves. The modified approach was experimentally verified by comparing tensile properties of five austenitic materials from uniaxial tensile test and instrumented indentation tests.

A new SmI2-promoted intramolecular reductive cyclization of β-(α-bromo siloxy) carbonyl compounds is reported.