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Experimental results are presented on proton induced single-event-upsets (SEU) on a 65 nm silicon-on-insulator (SOI) SRAM. The low energy proton SEU results are very different for the 65 nm SRAM as compared with SRAMs fabricated in previous technology generations. Specifically, no upset threshold is observed as the proton energy is decreased down to 1 MeV; and a sharp rise in the upset cross-section is observed below 1 MeV. The increase below 1 MeV is attributed to upsets caused by direct ionization from the low energy protons. The implications of the low energy proton upsets are discussed for space applications of 65 nm SRAMs; and the implications for radiation assurance testing are also discussed. Index Terms--Proton irradiation, silicon-on-insulator (SOI) technology, single event upset (SEU), SRAM.

Transistors and ICs built in several different captive and commercial facilities were exposed to moisture, irradiated, and annealed. The moisture exposures were performed using highly accelerated stress test (HAST) at 130[degrees]C and 85% relative humidity. Irradiation of n-channel transistors exposed to HAST followed by a long-term anneal resulted in some increase in interface-trap and oxide-trapped charge buildup. However, exposing p-channel transistors to HAST preirradiation resulted in extremely large and unexpected voltage shifts immediately following irradiation. They were observed for devices with either doped oxide or nitride final chip passivation. Because of this, nitride passivation may not be sufficient to prevent [H.sub.2]O from causing enhanced radiation-induced degradation over long time periods in some devices (e.g., commercial devices with nitride final chip passivation packaged in plastic packages). The smaller voltage shifts for the n-channel transistors may be related to the formation of phosphosilicate glass (PSG) overlying the sources and drains of the n-channel transistors impeding the diffusion of moisture to the gate oxides. It is shown that, the large radiation-induced voltage shifts for the p-channel transistors can lead to enhanced IC parametric degradation and functional failure at lower radiation levels. Large increases in radiation-induced field oxide leakage current were also observed for transistors exposed to HAST preirradiation. Transistors were also annealed (prior to irradiation) and irradiated in [H.sub.2]. Approximately the same level of radiation-induced degradation was observed for n- and p-channel transistors suggesting that the diffusion kinetics for [H.sub.2] diffusion are considerably different than for [H.sub.2]O diffusion. These results raise the concern that exposure of devices to moisture or hydrogen can lead to long-term radiation-induced aging effects. Index Terms--Aging effects, hydrogen exposure, ionizing radiation, moisture exposure, MOS radiation effects.

It is shown that protons and neutrons can induce enhanced degradation in power MOSFETs, including both trench and planar geometry devices. Specifically, large shifts in current-voltage characteristics can be observed at extremely low proton total dose levels (as low as ~ 2 rad(Si[O.sub.2])). These shifts can induce significant increases in device 'off' state leakage current. Neutron irradiations show similar degradation at equivalent fluence levels, even though neutrons do not deposit dose due to direct ionization. These data suggest that the mechanism responsible for the enhanced degradation is a microdose effect associated with secondary particles produced through nuclear interactions between protons and neutrons and the materials in integrated circuits. The secondary particles deposit enough charge in the gate oxide to induce a parasitic drain to source leakage path in the transistor. Although the results are demonstrated here for only trench and planar geometry power MOSFETs, microdose effects can impact the radiation response of other integrated circuit types. Hardness assurances issues implications are discussed. Index Terms--Microdose effects, neutron effects, power MOSFETs, proton effects, radiation effects, radiation hardness assurance, radiation hardness assurance methodology, radiation hardness assurance testing, single event effects.

The effect of high energy proton irradiation and angle of incidence on single-event latchup (SEL) hardness is investigated as a function of temperature and power supply voltage to determine worst-case hardness assurance test conditions for space environments. SRAMs from several vendors were characterized for single-event latchup SEL hardness at proton energies from 20 to 500 MeV at temperatures of 25 [degrees]C and 80 [degrees]C, and at both normal and grazing angles of incidence. For all SRAMs investigated, the largest SEL cross section is observed for irradiation with protons with energies larger than 200 MeV. In addition, it is shown that for proton with energies [greater than or equal to] 400 MeV, there is not a significant increase in SEL cross section for grazing angles of incidence compared to normal incidence irradiation. Based on the results of several years of research, in addition to these new results, we propose a hardness assurance test procedure for qualifying parts for use in proton-rich space environments. Index Terms--COTS, hardness assurance, proton, radiation effects, SEU, single event, single-event latchup (SEL), SRAM.

The radiation effects community has developed a number of hardness assurance test guidelines to assess and assure the radiation hardness of integrated circuits for use in space and/or high-energy particle accelerator applications. These include test guidelines for total dose hardness assurance qualification and single event effects (SEE) qualification. In this work, issues associated with these hardness assurance test guidelines are discussed. For total dose qualification, the main test methodologies used in the U.S. and Europe are reviewed and differences between the guidelines are discussed. In addition, some key issues that must be considered when performing total dose hardness assurance testing are addressed. Following these discussions we review some emerging issues relevant to SEE device qualification that are not covered in present SEE test guidelines. The hardness assurance implications of these issues are addressed. Index Terms--Integrated circuit radiation effects, integrated circuit reliability, proton-induced single-event latchup, radiation effects, radiation hardening (electronics), radiation hardness assurance, radiation hardness assurance methodology, radiation hardness assurance testing, single event effects, single-event upset.

Electronic devices in space environments can contain numerous types of oxides and insulators. Ionizing radiation can induce significant charge buildup in these oxides and insulators leading to device degradation and failure. Electrons and protons in space can lead to radiation-induced total-dose effects. The two primary types of radiation-induced charge are oxide-trapped charge and interface-trap charge. These charges can cause large radiation-induced threshold voltage shifts and increases in leakage currents. Two alternate dielectrics that have been investigated for replacing silicon dioxide are hafnium oxides and reoxidized nitrided oxides (RNO). For advanced technologies, which may employ alternate dielectrics, radiation-induced voltage shifts in these insulators may be negligible. Radiation-induced charge buildup in parasitic field oxides and in SOI buried oxides can also lead to device degradation and failure. Indeed, for advanced commercial technologies, the total-dose hardness of ICs is normally dominated by radiation-induced charge buildup in either parasitic field oxides and/or SOI buried oxides. Heavy ions in space can also degrade the oxides in electronic devices through several different mechanisms including single-event gate rupture, reduction in device lifetime, and large voltage shifts in power MOSFETs. Index Terms--Aging, MOS devices, oxide breakdown, power MOSFETs, radiation effects, silicon-on-insulator, total dose effects.

Heavy ion cross section data taken from a hardened-by-design circuit are presented which deviate from the traditional single sensitive volume or classical rectangular parallelepiped model of single event upset. TCAD and SPICE analysis demonstrate a SEU mechanism dominated by multiple node charge collection. Monte Carlo simulation is used to model the response and predict an on-orbit error rate. Index Terms--Geant4, MRED, rate prediction, SEU.

Large, unexpected shifts in the current-voltage (IV) characteristics of commercial power MOSFETs irradiated with heavy ions have been observed. The shifts can be more than sixty-five times larger than the shifts resulting from total dose irradiation with gamma rays or electrons, and are shown to strongly depend on both the irradiation bias and the ion linear energy transfer (LET). These large shifts are a significant concern for devices intended to operate in low power space applications because it is shown that they can lead to off-state leakage currents greater than 1 A. The data are consistent with the formation of parasitic transistors resulting from the microdose deposited in the gate oxides of these devices by the heavy ions. These results have significant implications for hardness assurance testing of MOS devices for use in space. Index Terms--COTS, gamma ray, heavy ion, microdose, power MOSFETS, proton, radiation, total dose.

The radiation hardness of nominally identical SRAM test chips fabricated in five commercial foundries is examined. Large variations in single-event latchup and total dose response are observed. The softest SRAMs fail functionally at ~200 krad(Si[O.sub.2]) and have a fairly large single-event latchup cross section. This is in contrast to the hardest foundry split which is nearly immune to single-event latchup at room temperature, and remains functional to a total dose of 400 krad(Si[O.sub.2]). Three of the splits show a similar increase in radiation induced leakage current, which is dependent on both the characterization bias as well as the pattern written to the memory array. The other two splits show neither a pattern nor a bias dependence on the leakage current. Heavy-ion microbeam experiments confirm that the most latchup sensitive area of these SRAMs is the peripheral circuitry, not the memory array itself. Qualification and hardened-by-design integrated circuit implications are discussed. Index Terms--Commercial foundry, COTS, heavy-ion, leakage current, neutron, proton, radiation effects, radiation response, SEL, SEU, single event, SRAM, total-dose.

To explore the impact of temperature on the post-irradiation response of ICs, we characterized the temperature response of transistors, SRAMs, and a custom mixed-signal ASIC. Devices were irradiated at room temperature and electrically characterized post irradiation as a function of temperature. Devices exhibit significantly more parametric degradation when characterized at elevated temperatures. In addition to parametric degradation, it is demonstrated that post-irradiation elevated temperature characterization can also induce functional failures at significantly lower total dose levels than at room temperature. As a result, to ensure system functionality, it is essential that devices be characterized over the full system temperature range pre- and post-irradiation. Recommendations for incorporating temperature testing into a hardness assurance test method (i.e., Method 1019) are suggested. Methods for minimizing the detrimental effects of elevated temperature anneals on hardness assurance testing are also discussed. Index Terms--Hardness assurance testing, integrated circuit radiation effects, integrated circuit reliability, radiation effects, radiation hardening (electronics).

The type of final chip passivation layer used to fabricate linear bipolar circuits can have a major impact on the total dose hardness of some circuits. It is demonstrated that National Semiconductor Corporation linear bipolar devices fabricated with only an amorphous silicon carbide passivation layer do not exhibit enhanced low-dose-rate sensitivity (ELDRS), while devices from the same production lot fabricated with other types of passivation layers are ELDRS sensitive. SiC passivation possesses mechanical, electrical and chemical properties that make it compatible with linear device fabrication processes. These properties of SiC passivation layers, combined with the excellent radiation response of devices passivated with SiC, make SiC passivation layers a very attractive choice for devices packaged in either ceramic or plastic-encapsulated packages for use in space environments. Index Terms--Enhanced low-dose-rate sensitivity (ELDRS), hardness assurance testing, integrated circuit reliability, integrated circuit testing, linear bipolar integrated circuits, mechanical stress, passivation layers, pre-irradiation elevated temperature stress, radiation effects, radiation hardening (electronics), radiation response, reliability screens, silicon carbide, thermal cycling, thermal stress effects.

The total dose hardness of several commercial power MOSFET technologies is examined. After exposure to 20 krad(Si[O.sub.2]) most of the n- and p-channel devices examined in this work show substantial (2 to 6 orders of magnitude) increases in off-state leakage current. For the n-channel devices, the increase in radiation-induced leakage current follows standard behavior for moderately thick gate oxides, i.e., the increase in leakage current is dominated by large negative threshold voltage shifts, which cause the transistor to be partially on even when no bias is applied to the gate electrode. N-channel devices biased during irradiation show a significantly larger leakage current increase than grounded devices. The increase in leakage current for the p-channel devices, however, was unexpected. For the p-channel devices, it is shown using electrical characterization and simulation that the radiation-induced leakage current increase is related to an increase in the reverse bias leakage characteristics of the gated diode which is formed by the drain epitaxial layer and the body. This mechanism does not significantly contribute to radiation-induced leakage current in typical p-channel MOS transistors. The p-channel leakage current increase is nearly identical for both biased and grounded irradiations and therefore has serious implications for long duration missions since even devices which are usually powered off could show significant degradation and potentially fail. Index Terms--Commercial-off-the-shelf (COTS), interface trap, leakage current, oxide trapped charge, power MOSFET, radiation effects, radiation hardened, radiation response, simulation, vertical double diffused power MOSFET (VDMOSFET).

Single-event transients (SETs) in digital circuits/processes are examined. SETs appear to substantially mitigate traditional SEU static-latch hardening techniques below 0.25 [micro]m. The resulting IC error rate for advanced technology node hardened-electronics is dominated by the combinational-logic SET rate. Index Terms--Error-rate, heavy ion, radiation effects, single event effects, single event transient, single event upset, transient propagation, transient pulse width.

The production and propagation of single-event transients in scaled metal oxide semiconductor (CMOS) digital logic circuits are examined. Scaling trends to the 100-nm technology node are explored using three-dimensional mixed-level simulations, including both bulk CMOS and silicon-on-insulator (SOI) technologies. Significant transients in deep submicron circuits are predicted for particle strikes with linear energy transfer as low as 2 MeV-[cm.sup.2]/mg, and unattenuated propagation of such transients can occur in bulk CMOS circuits at the 100-nm technology node. Transients approaching 1 ns in duration are predicted in bulk CMOS circuits. Body-tied SOI circuits produce much shorter transients than their bulk counterparts, making them more amenable to transient filtering schemes based on temporal redundancy. Body-tied SOI circuits also maintain a significant advantage in single-event transient immunity with scaling. Index Terms--Integrated circuit reliability, integrated circuit scaling, integrated circuit testing, radiation effects, radiation hardening (electronics), radiation response, single event effects, single event transient, single event upset.

The post-irradiation annealing behavior of total dose degradation in LM139 comparators fabricated in National Semiconductor Corporation's (NSC) enhanced low-dose-rate sensitive (ELDRS) linear bipolar technology is examined. Data show that a large fraction of the radiation-induced increase in input bias current recovers after a 100[degrees]C anneal. The recovery in input bias current is linked to a significant amount of interface-trap annealing at 100[degrees]C. This is qualitatively consistent with previous data on interface-trap annealing and recent models for interface-trap annealing associated with hydrogen motion at the silicon/silcon dioxide interface. The annealing results have implications for hardness assurance testing. If the radiation induced charge that is responsible for ELDRS (whether it be interface or border traps) can anneal at 100[degrees]C, these data suggest that elevated temperature irradiations sometimes used to bound the ELDRS response of ICs may also cause some annealing of radiation-induced charge. These data help explain why high-dose-rate irradiations at elevated temperatures in some cases underestimate low-dose-rate degradation. In addition, these data confirm that high-dose-rate irradiations followed by elevated temperature anneals do not mimic the mechanisms that cause enhanced degradation at low dose rates in devices with ELDRS. Index Terms--Bipolar linear integrated circuits, defect annealing, enhanced low-dose-rate sensitivity, hardness assurance testing, integrated circuit reliability, integrated circuit testing, passivation layers, pre-irradiation elevated temperature stress, radiation effects, radiation hardening (electronics), radiation response, thermal cycling, thermal stress effects, thermal stresses.

We examine the radiation response, annealing characteristics, and long-term reliability of capacitors with Al gates and [Al.sub.2][O.sub.3]-Si[O.sub.x][N.sub.y] gate dielectrics stacks which received a forming gas anneal (FGA) or an [O.sub.2] and FG anneal after high-[kappa] deposition. By comparison to a theoretical capacitance-voltage (CV) curve, the FG annealed devices are found to have a large preirradiation interface trapped charge density of ~7 + [10.sup.11] [cm.sup.-2], whereas devices annealed in [O.sub.2] and FG show a large density (~9 x [10.sup.11] [cm.sup.-2]) of negative bulk charge. The midgap voltage shift ([DELTA] [V.sub.mg]) increases monotonically with dose for both sets of devices, but the [O.sub.2] annealed devices exhibit 50% less trapping at a total dose of 2 Mrad(Si[O.sub.2]). The radiation-induced voltage shifts are found to recover during long duration biased anneals as a result of tunneling and thermal annealing. For short times and large biases, the annealing response is found to be dominated by tunneling. After 1,000 s of annealing, there is a 50% reduction in [DELTA] [V.sub.mg] for devices annealed at 2.0 MV/cm and a 7.5 % recovery for devices annealed at 1.0 MV/cm. For longer times, the annealing response of these devices is dominated by thermal annealing. Accelerated life testing shows these devices have a broad failure distribution with a large population of extrinsic failures. Extrapolation of the reliability data suggests these particular devices would have to be operated at an electric field less than ~2.5 MV/cm to achieve a ten-year operational lifetime. Improved reliability is, therefore, required before insertion into a manufacturing environment. Index Terms--Alternative dielectric, annealing, bias dependence, high-[kappa], interface trap, MOS capacitor, oxide trapped charge, processing, radiation effects, radiation response, reliability.

Combining broad-beam circuit level single-event upset (SEU) response with heavy ion microprobe charge collection measurements on single silicon-germanium heterojunction bipolar transistors improves understanding of the charge collection mechanisms responsible for SEU response of digital SiGe HBT technology. This new understanding of the SEU mechanisms shows that the right rectangular parallele-piped model for the sensitive volume is not applicable to this technology. A new first-order physical model is proposed and calibrated with moderate success. Index Terms--Ground testing, modeling, SiGe, silicon germanium, single event effect, single event upset.

This paper presents the first 3-D simulation of heavy-ion induced charge collection in a SiGe HBT, together with microbeam testing data. The charge collected by the terminals is a strong function of the ion striking position. The sensitive area of charge collection for each terminal is identified based on analysis of the device structure and simulation results. For a normal strike between the deep trench edges, most of the electrons and holes are collected by the collector and substrate terminals, respectively. For an ion strike between the shallow trench edges surrounding the emitter, the base collects appreciable amount of charge. Emitter collects negligible amount of charge. Good agreement is achieved between the experimental and simulated data. Problems encountered with mesh generation and charge collection simulation are also discussed. Index Terms--Deep trench, DESSIS, HBT, LET, mesh, polysilicon emitter, shallow trench, SIMS, SRIM, UHV/CVD.

It is shown that final chip passivation layers can have a significant impact on total dose hardness. A number of final chip passivation layers are evaluated to identify films that mitigate enhanced low-dose-rate sensitivity (ELDRS) in National Semiconductor Corporation's linear bipolar technologies. It is shown that devices fabricated with either a low temperature oxide or a tetraethyl ortho silicate passivation do not exhibit significant ELDRS effects up to 100 krad(Si[O.sub.2]). Passivation studies on CMOS SRAMs suggest that it is unlikely that the passivation layers (or processing tools) are acting as a new source of hydrogen, which could drift or diffuse into the oxide and increase ELDRS sensitivity. Instead, it is possible that the passivation layers affect the mechanical stress in the oxide, which may affect oxide trap properties and possibly the release and mobility of hydrogen. Correlations between mechanical stress induced by the passivation layers and radiation degradation are discussed. Index Terms--Bipolar linear integrated circuits, enhanced low-dose-rate sensitivity, hardness assurance testing, integrated circuit reliability, integrated circuit testing, mechanical stress, passivation layers, pre-irradiation elevated temperature stress, radiation effects, radiation hardening (electronics), radiation response, thermal cycling, thermal stress effects, thermal stresses.

Physical mechanisms responsible for nondestructive single-event effects in digital microelectronics are reviewed, concentrating on silicon MOS devices and integrated circuits. A brief historical overview of single-event effects in space and terrestrial systems is given, and upset mechanisms in dynamic random access memories, static random access memories, and combinational logic are detailed. Techniques for mitigating single-event upset are described, as well as methods for predicting device and circuit single-event response using computer simulations. The impact of technology trends on single-event susceptibility and future areas of concern are explored. Index Terms--Charge collection, heavy ion irradiation, radiation effects, radiation hardening, single-event effects, single-event upset, soft errors, terrestrial cosmic rays.

Final chip passivation layers are shown to have a major impact on the total dose hardness of bipolar linear technologies. It is found that devices fabricated without passivation layers do not exhibit enhanced low-dose-rate sensitivity (ELDRS) or pre-irradiation elevated-temperature stress (PETS) sensitivity, whereas devices from the same production lot fabricated with either oxide/nitride or doped-glass passivation layers are ELDRS and PETS sensitive. In addition, removing the passivation layers after fabrication can mitigate ELDRS and PETS effects. ELDRS and PETS effects do not appear to be inherently related to circuit design or layout, but are related to mechanical stress effects, hydrogen in the device, or a combination of the two. These results suggest that proper engineering of the final chip passivation layer might eliminate ELDRS and PETS effects in bipolar integrated circuits. Index Terms--Bipolar linear-integrated circuits, enhanced low-dose-rate sensitivity, hardness-assurance testing, integrated-circuit reliability, integrated-circuit testing, mechanical stress, passivation layers, pre-irradiation elevated-temperature stress, radiation effects, radiation hardening (electronics), radiation response, reliability screens, thermal cycling, thermal-stress effects, thermal stresses.

Pulsed lasers show excellent promise for single-event upset (SEU) studies in laboratory environments due to their simplicity of use. However, a one-to-one relationship between a laser hit and a heavy-ion hit has not been developed so far. With the assumption that the collected charge from a SEU hit dictates the circuit-level response, equivalency between a laser hit and heavy-ion hit can be established if the collected charge from both hits is identical. This paper presents a methodology to identify the equivalent laser characteristics for a heavy-ion hit by calculating the collected charge through device-level simulations. Such knowledge will enable SEU hardness assurance of circuits using lasers.

In this paper we review the current status of device simulation of ionizing-radiation-induced charge collection and single-event upset (SEU), with an emphasis on significant results of recent years. We present an overview of device-modeling techniques applicable to the SEU problem and the unique challenges this task presents to the device modeler. We examine unloaded simulations of radiation-induced charge collection in simple p/n diodes, SEU in dynamic random access memories (DRAM's), and SEU in static random access memories (SRAM's). We conclude with a few thoughts on future issues likely to confront the SEU device modeler.