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Read disturbance is analyzed in vertically channel-stacked NAND flash memory, which has string select transistors (SSTs) to access each channel layer independently. Additional read disturbance is observed at the cells adjacent to the selected cell in the unselected channel layers as well as typical read disturbance caused by repetitive Fowler–Nordheim tunneling (F-N) stress. Technology computer-aided design simulations and measurements are performed to investigate the disturbance mechanisms. It is found that bitline-side [common-source line-side] adjacent cell is disturbed by the hot carrier injection (HCI), which results from positively [negatively] boosted channel potential by the rising [falling] of the voltage ( ${V}_{\text {unsel}}$ ) applied to unselected cells, respectively. A novel read operation, in which the selected cells are maintained in turned on state during the ${V}_{\text {unsel}}$ rising/falling and then are restored to their own states, is proposed to suppress the occurrence of the HCIs. As a result, it is revealed that the HCI-induced read disturbances are successfully suppressed by the proposed method.

To obtain high channel boosting potential and reduce a program disturbance in channel stacked NAND flash memory with layer selection by multilevel (LSM) operation, a new program scheme using boosted common source line (CSL) is proposed. The proposed scheme can be achieved by applying proper bias to each layer through its own CSL. Technology computer-aided design (TCAD) simulations are performed to verify the validity of the new method in LSM. Through TCAD simulation, it is revealed that the program disturbance characteristics is effectively improved by the proposed scheme.

In this letter, a channel-stacked array with tied bit-line (BL) and ground select transistor (GST) is proposed to access each layer independently without additional string select transistors (SSTs) to a conventional planar NAND array. The proposed structure can maximize memory density, since additional SSTs are not required for layer selection and the placement of BLs/word lines is similar to that of the conventional NAND array except for island-type GSTs. Basic memory operations are performed with fabricated devices. The selected layer is erased only by applying erase voltage to the selected common source line (CSL) and by biasing inhibition voltage to other CSLs. Only the selected layer is read by applying the same voltage as BL voltage to the CSLs of the unselected layers. In addition, the selected strings in the selected layer are programmed and other strings in the selected and unselected layers are all inhibited by the combination of CSL and BL voltages. Consequently, stable memory operations are obtained successfully in the proposed structure without interference between stacked layers.

In this paper, we propose new string select transistors (SSTs)/dummy SSTs (DSSTs) threshold voltage ( $V_{\mathrm{ th}}$ ) setting methods in simplified channel-stacked array with layer selection by multilevel operation (SLSM). In these methods, SSTs/DSSTs on each layer are set to their targeted $V_{\mathrm{ th}}$ values by incremental step pulse program/one erase with various erase voltages, respectively. In the fabricated pseudo-SLSM, the validity of the new methods is verified. As a result, it is confirmed that the $V_{\mathrm{ th}}$ values of SSTs/DSSTs are set to the targeted $V_{\mathrm{ th}}$ values by the new methods and SSTs with extremely narrow $V_{\mathrm{ th}}$ distribution can be obtained in the consequence. Moreover, memory operations such as erase, program, and read are performed in the fabricated structure after setting the $V_{\mathrm{ th}}$ values of all the SSTs/DSSTs by the new methods. Despite unique LSM operations, stable memory operations are obtained successfully without the interference between stacked layers.

Wastewater heat recovery heat pump systems use heated wastewater from public baths or factories as the heat pump’s heat source. Generally, this system uses a bare tube evaporator. In the heat transfer process from wastewater to refrigerant, thermal resistance is caused primarily by fouling deposits on the outside surface of tube. Fouling directly increases thermal resistance and decreases heat pump efficiency. Thus, it is desirable to eliminate fouling. In this study, we fabricated a fouling mitigation device using a bubbling fluidized bed with cleaning sponge balls in the wastewater bath. Experimental conditions were as follows: 20°C cold-water temperature, 40°C wastewater temperature, 100 L/h cold water flow rate, and 0.161  heat exchanger surface area. Experimental results showed that the thermal resistance of fouling decreased by 56% with the fluidized bed alone and by 86% with both the fluidized bed and cleaning sponge balls.

Program disturbance is analyzed in a simplified channel-stacked array with layer selection by multilevel operation after setting the threshold voltages ( $V_{\textrm {th}}$ ) of string select transistors (SSTs)/dummy SSTs. There are additional unselected cells that should be inhibited in different ways, and they have the worse disturbance characteristics compared with conventional NAND arrays. Technology computer-aided design simulations and measurements are performed to investigate the disturbance mechanism of the additional cases. It is found that initially nonprecharged channel and large leakage current flowing from channel to bitline degrade the disturbance. New program method is proposed along with low gate bias of dummy wordline. As a result, program disturbance is significantly improved and reliability is also enhanced by reducing the potential difference between the SST gate and the channel.

In order to obtain high channel boosting potential and to reduce a program disturbance in channel stacked type with layer selection by multi-level operation (LSM), a new program scheme using boosted common source line (CSL) is proposed. The proposed scheme can be achieved by applying proper bias to each layer through its own CSL. To verify the validity of the new method in LSM, TCAD simulations are performed. Through TCAD simulation, it is revealed that the program disturbance characteristics is significantly improved by the proposed scheme.

In this study, the effects of nitride trap layer properties on location of charge centroid in charge-trap flash (CTF) memory are closely investigated. In the operations of CTF memories, charges tunnel into the nitride layer through thin oxide, unlike the floating-gate (FG) type flash memory where the charges are stored in the conductive poly-crystalline Si. Deeper understanding of distribution of the trapped charges should be beneficial in setting up an accurate compact model of CTF memory cell, where the charge centroid becomes a very practical means by which a rather large number of trapped electrons can be dealt in the more mathematical manner as a whole electron cloud. The relation between charge centroid and program voltage (Kpgm) depending on nitride layer properties is analytically studied.

In this letter, we propose a simplified channel-stacked array with a layer selection by multi-level operation (SLSM) and a new string select transistors (SSTs) threshold voltage ( $V_{\mathrm {th}}$ ) setting method that all the SSTs on each layer are set to targeted the $V_{\mathrm {th}}$ values simultaneously by one erase operation. To verify the validity of the new method in SLSM, TCAD simulations are performed, and a fabricated pseudo SLSM is measured. It is verified that the $V_{\mathrm {th}}$ values of SSTs are set to the targeted $V_{\mathrm {th}}$ values by the new method. Moreover, memory operations are examined in the fabricated structure after setting the $V_{\mathrm {th}}$ values of all the SSTs by the new method. As a result, stable memory operations are obtained successfully without the interference between stacked layers.

Charge trap characteristic at tunneling oxide of floating gate NAND flash observed after program/erase (P/E) cycling. At initial P/E cycling, acceptor-like interface traps and positive oxide traps are generated simultaneously but the effect of interface trap is dominant and consequently threshold voltage increase. However, once the interface traps are generated, change of interface trap is negligible under program or erase operation and threshold voltage variation mainly depends on oxide traps. Additionally, voltage acceleration factor of threshold voltage change at low erase voltage is extracted for relative reliability test of NAND flash memory devices.

In this study, the gate-all-around (GAA) poly-Si channel flash memories with charge trap layer (Si3N4) have been successfully fabricated. Electric characteristics of fabricated devices including threshold voltage shift with program/erase operation have been investigated. Gate configurations were structured differently according to each defined channel width. Results show that devices with gate-all-around structure have superior program efficiency. To investigate the effect of gate configuration on the program efficiency, TCAD simulation was carried out.

In 3D stacked NAND flash memory, the number of stacked layers tends to increase for high density storage capacity. With the increase of the height of devices, it is important to achieve a good vertical etch profile by which word line (WL) gate dimensions are affected. In this paper, we investigate the effect of the variation of gate dimensions on the program characteristics in 3D NAND flash memory array by using TCAD simulation. Also, we compare the cell characteristics of NAND flash with different structures, gate-all-around (GAA) and double gate (DG).

As the needs for high density NAND flash memory have been dramatically increasing, the memory density has also increased by scaling down the technology node. As the scaling of NAND flash memory is accelerated, the short channel effect is more severe and further scaling down is faced with process limitations. So, various types of 3D stacked NAND flash memory has been introduced and reported for ultra-high-density data storage and Fig. 1 shows one of the previously reported 3D stacked NAND flash memory structures [1–3]. However, as the distance between layers is reduced, several channel coupling problems are emerging. In this paper, we investigate the self boosting disturbance induced by channel coupling between layers in the 3D stacked NAND flash memory.

In this study, the gate-all-around (GAA) poly-Si channel flash memories with a nitride charge trap layer (Si 3 N 4 ) have been successfully fabricated. Electrical characteristics of fabricated devices including the threshold voltage shift with program/erase operation have been investigated. Gate structures were formed differently according to each defined channel width. Results show that devices with the gate-all-around structure have superior program efficiency. To investigate the effect of gate structure on the program efficiency, TCAD simulation was carried out. Another issue of the fabricated devices is poor erase operation due to the quality of the blocking oxide. This issue has been studied through the capacitor composed of the same stack structure, and the way to improve the erase operation has been proposed.

In this study, we investigate the variation of threshold voltage and ON-cell current caused by cell gate length fluctuation in silicon–oxide–nitride–oxide–silicon (SONOS) NAND flash memory with virtual source and drain (VSD). The fluctuation in cell gate length caused by process errors such as line edge roughness, etch slope variation, and lithography resolution-induced error affects threshold voltage and ON-cell current considerably. Our results show that three-dimensional (3D) structures have robust immunity to the cell gate length fluctuation effect. From the viewpoint of array design, threshold voltage and ON-cell current variation due to cell gate length fluctuation can be reasonably mitigated by enlarging the cell gate length in a word line (WL) pitch and reducing the body doping concentration. In addition, the tendency of the variation by technology node scaling and the comparison with the junctionless NAND flash memory structure are also investigated.