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In this talk, we present an overview of our current research focus in developing non-destructive metrology for monitoring reliability issues in 3D-integrated electronic systems. Working closely with the semiconductor industry, we have been looking at various performance limiting phenomena in 3D-interconnects, the associated dielectrics, and advanced packaging for integrated circuits. The talk will identify some common reliability concerns, and identify some metrology gaps, for 3-D integrated systems. We will introduce a suite of microwave-based Broadband Dielectric Spectroscopic (BDS) techniques and show how these non-destructive metrologies can serve as early warning monitors for reliability issues. These techniques are based on the application of high frequency microwaves, to probe impedance changes due to material and structural changes in integrated circuits under various external stress. For example, we will also discuss the combination of BDS with scanning probe infrastructure to create the Scanning Microwave Microscopy (SMM) technique, which has been used to detect buried artifacts and characterize metallic contacts. We further illustrate the capabilities of the BDS-based techniques with case studies of three potential reliability issues in 3D IC. We conclude with a forward look at the future metrology and standards needs 3-D interconnects and the associated advanced packaging.

GaN high electron mobility transistors (HEMTs) on SiC substrates are produced for both commercial and defense applications that require high voltage, high power, and high efficiency operation. Although leading GaN HEMT manufacturers have reported excellent RF power characteristics and encouraging reliability, long-term reliability in the space environment remains a major concern due to unknown degradation mechanisms. For the present study, we continued to investigate degraded RF GaN HEMTs using micro-analytical techniques. Our RF AlGaN-GaN devices grown on SiC substrate had a Ni-Pd-Au Schottky gate length of 0.25 μm, a total gate width of 6 × 150 μm periphery, and a field plate. First, we performed DC bias-temperature stress tests on GaN HEMTs and some GaN HEMTs were thermally stressed as control samples. Second, we employed focused ion beam (FIB) to prepare TEM cross sections from degraded and control devices for defect analysis using a high resolution TEM. Pits, cracks, and pockets of palladium were found at the edge of the drain side of the gate. We report our detailed analysis results including our understanding on the out-diffusion of Pd as a potential degradation mechanism in our RF GaN HEMTs.

GaN high electron mobility transistors (HEMTs) on SiC substrates are produced for both commercial and defense applications that require high voltage, high power, and high efficiency operation. Although leading GaN HEMT manufacturers have reported excellent RF power characteristics and encouraging reliability, long-term reliability in the space environment remains a major concern due to unknown degradation mechanisms. For the present study, we investigated stressed/degraded RF GaN HEMTs using micro-analytical techniques. Our RF AlGaN-GaN devices grown on SiC substrate had a Ni-Pd-Au Schottky gate length of 0.25 μm, a total gate width of 6 × 150 μm periphery, and a field plate. First, we performed DC bias-temperature stress tests on GaN HEMTs and some GaN HEMTs were thermally stressed as monitor samples. Second, we employed focused ion beam (FIB) to prepare TEM cross sections from degraded and monitor devices for defect analysis using a high resolution TEM. Defects containing highly Pd-enriched features were found at the edge of the drain side of the gate. We present our detailed analysis results including our understanding on the out-diffusion of Pd as a potential degradation mechanism in our RF devices.

The inevitable current overshoot which follows forming in filamentary RRAM devices is often perceived as a source of variability that should be minimized. This sentiment has led to efforts to curtail the overshoot by decreasing the parasitic capacitance using highly integrated 1T-1R or 1R-1R device structures. While this is readily achievable in single device test structures, it poses an intricate design constraint for memory array designs. Several papers (Degraeve et al., 2010, 2014; Fantini et al., 2013; Raghavan et al., 2013; Padovani et al., 2015) suggest that there is insufficient current to form stable filaments for small parasitic capacitances and/or low current compliance levels. Thus, the relationship between minimizing overshoot current and improved filament stability is tenuous. In this study, we utilize the forming energy-based understanding of filamentary forming to reveal that the parasitic capacitance should be optimized, rather than minimized for better filament control.

We observe a gamma-irradiation-induced change in electrically detected magnetic resonance (EDMR) in TiN/Ti/HfO2/TiN resistive random access memory (RRAM). EDMR measurements exclusively detect electrically active defects, which are directly involved in the transport mechanisms within these devices. The EDMR response has an isotropic g value of 2.001 ± 0.0003. The response increases dramatically with increased gamma irradiation. We tentatively associate this EDMR response with spin-dependent trap-assisted tunneling events at O2− centers coupled to hafnium ions. Although our study cannot fully identify the role of these defects in electronic transport, the study does unambiguously identify changes in transport defects caused by the ionizing radiation on defects involved in electronic transport in RRAM devices. This paper also contributes more broadly to the RRAM field by providing direct, though incomplete, information about atomic scale defects involved in electronic transport in leading RRAM systems.

Traditional metrology has been unable to adequately address the reliability needs of emerging integrated circuits at the nano scale; thus, new metrology and techniques are needed. In this paper, we use microwave propagation characteristics (insertion loss and dispersion) to study the atmospheric interconnect corrosion under accelerated stress conditions. The results presented in this work indicate that the corrosion resilience of the test device is limited by the thermal aging of the passivation layer.

To combat the large variability problem in resistive random access memory, current compliance elements are commonly used to limit the in-rush current during the forming operation. Regardless of the compliance element (1R-1R or 1T-1R), some degree of current overshoot is unavoidable. The peak value of the overshoot current is often used as a predictive metric of the filament characteristics and is linked to the parasitic capacitance of the test structure. The reported detrimental effects of higher parasitic capacitance seem to support this concept. However, this understanding is inconsistent with the recent successes of compliance-free ultrashort pulse forming which guarantees a maximum peak overshoot current. We use detailed circuit analysis and experimental measurements of 1R-1R and 1T-1R structures to show that the peak overshoot is independent of the parasitic capacitance while the overshoot duration is strongly dependent on the parasitic capacitance. Forming control can be achieved, in ultrashort pulse forming, since the overshoot duration is always less than the applied pulse duration. The demonstrated success of ultrashort pulse forming becomes easier to reconcile after identifying the importance of overshoot duration.

Charge-capture/emission is ubiquitous in electron devices. Its dynamics often play critical roles in device operation and reliability. Treatment of this basic process is found in many text books and is considered well understood. As in many electron device models, the individuality of immobile charge is commonly replaced with the average quantity of charge density. This has worked remarkably well when large numbers of individual charges (ensemble) are involved. As device geometries become very small, the ensemble “averaging” becomes far less accurate. In this work, the charge-capture/emission dynamic of Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) is re-examined with full consideration of individual charges and the local field in their immediate vicinity. A dramatic modification of the local band diagram resulted, forcing a drastic change in emission mechanism. The implication is that many well-understood phenomena involving charge capture/emission will need to be reconsidered. As an example, this new picture is applied to the random telegraph noise (RTN) phenomenon. When the screening of a trapped charge by a polar medium such as SiO2 is quantitatively accounted for in this local field picture, a new physically sound RTN emission mechanism emerges. Similarly, the dynamics of post-stress recovery of Negative-Bias-Instability of p-channel MOSFET can be more rationally explained.

Resistive random access memory (RRAM) technology promises superior performance and scalability while employing well-developed fabrication processes. Conductance in insulating oxides employed in RRAM devices can be strongly affected by atomic-level changes that makes cell switching properties extremely sensitive to operation conditions inducing local structural modifications. This opens an opportunity to condition the memory cell stack by forming a conductive filament capable of high frequency, low energy switching. Certain materials with pre-existing conductive paths, in particular some polycrystalline oxides, like hafnia, are shown to respond well to this approach. For this class of materials, the concept of ultra-fast pulse technique as an ultimate method for assessing RRAM switching capabilities in circuitry operations is discussed. Hafnia-based cells demonstrate compliance-free (1R) forming with no current overshoot, low operation currents, and reduced variability.

High-mobility alternative channel materials to silicon are critical to the continued scaling of MOS devices. The analysis of capacitance–voltage (C–V) measurements on these new materials with high-k gate dielectrics is a critical technique to determine many important gate-stack parameters. While there are very useful C–V analysis tools available to the community, these tools are all limited in their applicability to alternative semiconductor channel MOS gate-stack analysis since they were developed for silicon. Here, we report on a new comprehensive C–V simulation and extraction tool, called CV Alternative Channel Extraction (ACE), that incorporates a wide range of semiconductors and dielectrics with the capability to implement customized gate stacks. Fermi–Dirac carrier statistics, nonparabolic bands, and quantum mechanical effects are all implemented with options to turn each of these off as the user desires. Interface state capacitance ( ${C}_{\mathsf {it}}$ ) is implemented using a common model for systems like Si and Ge. A more complex ${C}_{\mathsf {it}}$ model is also implemented for III–Vs that accurately captures frequency dispersion in accumulation that arises from tunneling. CV ACE enables extremely fast simulation and extraction and can accommodate measurements performed at variable temperatures and frequencies to allow for a more accurate extraction of interface state density ( ${D}_{\mathsf {it}}$ ).

Scaled advanced node devices incorporate new combinations of semiconductor materials and ultra-thin multi-layer dielectric stacks. As a consequence, inter-material interactions may unpredictably affect transistor electrical characteristics and reliability. Conventional reliability tests may miss spontaneously-occurring device recovery as well as parameters shift caused by extremely high frequency circuit operations and, therefore, may underestimate or overestimate lifetime. The proposed application-specific reliability tests account for degradation processes occurring under the conditions of interest; it can also define a safe range of use conditions that may significantly extend the device lifetime beyond the conventional reliability predictions supplied by manufacturers. We present data in support of application-specific reliability testing and discuss its use in prequalification of new technologies.

We report on new fluctuation dynamics of the high resistance state of Hafnia-based RRAM devices after RESET. We observe that large amplitude fluctuations occur more frequently immediately after programming and their frequency of occurrence decays in the tens of microseconds. The fluctuation amplitude, on the other hand, does not decay noticeably over the entire millisecond read time. While post-programming instability and post-programming resistance dispersion have both been reported in the literature, the relaxation in the frequency of occurrence without a commensurate amplitude decay is new. Since picosecond pulses were used for our RESET operation, post-programming thermalization occurs on the nanosecond time scale. This clearly eliminates a thermally driven mechanism as the cause of the observed fluctuation behavior. Furthermore, reducing the READ voltage by tenfold does not have any effect and also eliminates read disturb as possible cause.

Leading GaN HEMT manufacturers have reported excellent RF power characteristics and encouraging reliability. However, long-term reliability in the space environment still remains a major concern due to a number of defects and traps as well as unknown degradation mechanisms. Thus, careful study of reliability and radiation effects of GaN HEMTs should be performed before GaN HEMT technology based solid state power amplifiers (SSPAs) are successfully deployed in space satellite systems. We studied both RF GaN HEMTs fabricated per our design and commercial high-power GaN HEMTs, both grown on SiC substrates. Our RF devices had a nominal Ni-Au Schottky gate length of 0.25 μm, a total gate width of 6 × 150 μm periphery, and a field plate, while high-power devices had a Ni-Au Schottky gate length of 0.4 μm, a total gate width of 10 × 350 μm periphery, and a field plate. First, DC and RF characteristics of RF devices were compared before and after they were aged under different conditions (DC and temperature). Focused-ion-beam was employed to prepare TEM cross sections from degraded devices for defect analysis using a high-resolution TEM. Also, we performed strain analysis on pristine and degraded devices using TEM-based techniques. Second, DC characteristics of high-power devices were compared before and after they were irradiated with protons and heavy ions. Some of devices were exposed while they were unbiased, DC biased, and DC and RF biased.

In this letter, we use gated Hall method for direct measurement of free carrier density and electron mobility in inversion InGaAs MOSFET channels. At room temperature, the highest Hall mobility of 1800 cm2/Vs is observed at electron density in the channel $\approx 1\times 10^{12}$ cm $^{-2}$ . A comparison with mobility values estimated from transistor characteristics reveals a significant underestimation of mobility, which arises from overestimation of channel density obtained from $C$ – $V$ measurements. Temperature dependence of the electron mobility provides the evidence that remote Coulomb scattering dominates at electron density $ cm $^{-2}$ . Contrary to the capacitance-based methods commonly used for extraction of interface trap density, a gated Hall method can separate the contributions of fast-trapped charges and free carriers in the channel to the total charge of a MOS capacitor. This allows for reliable estimation of trap density at the III–V/high- $k$ interface including border traps. The results illustrate that even high-quality interfaces providing high-mobility transport suffer from fast border traps above the conduction band. In contrast with Si where the effect of border traps is negligible, in low density-of-state InGaAs channel material as much as half of the channel electrons can be trapped and excluded from transport, increasing switching energy and dissipated power.

Intrinsic switching characteristics of two resistive memory technologies, hafnia (RRAM)- and carbon nanotube (CNT)- based, are evaluated with respect to their implementation in deep neural networks (DNN) and possible mitigation approaches to performance degradation. Both RRAM (poly-crystalline metal oxide) and NRAM (fabric of interlocking matrix of CNTs) operations employ modulations of the conductive paths through a semi-isolating layer sandwiched between electrodes. RRAM and NRAM characteristics demonstrate similar features when evaluated employing commonly used switching times > 100 ns: variability of the weights update values linked to stochasticity of the switching processes, asymmetric weight change, and memory update saturation. Though materials are different, the observed undesirable trends have a common cause that is excessive energy released within the duration of switching operations: it induces gradual changes in the material structure surrounding conductive paths. Such changes, in turn, affect temperature distribution and related structural rearrangements during the subsequent switching. In particular, memory update saturation reflects on exhaustion of the number of structural blocks (atoms, CNTs) available for expanding the conductive path under specific used operation conditions. As follows, by reducing energy released in each operation we may suppress excessive structural changes, hence related performance degradation features. Indeed, under sub-ns switching conditions relevant to high-frequency circuitry operations, both RRAM and NRAM demonstrate significant performance improvement making them promising for DNN implementations.

The distributed oxide trap model based on tunneling of carriers from the semiconductor surface is unified with the two-band Shockley–Read–Hall type of capture and emission model for interface states. The new model explains the often observed upturn of MOS conductance at high frequencies when biased in inversion. The unified two-band model fully covers both types of charge traps in all MOS bias regions.

We propose a new defect characterization technique for high- $k$ dielectric stacks in III-V MOSFETs. This technique allows extracting the defect density from the simulations of the $C$ – $V$ and $G$ – $V$ characteristics at different frequencies. The simulation is performed using a physical distributed compact model, where the trap-assisted capture and emission processes are described in the framework of the multiphonon trap-assisted tunneling theory, including lattice relaxation. The technique, tested on InGaAs MOS devices with different gate-stacks, allows profiling the interfacial and bulk defects in the ( $E, z$ ) domain. The extracted map, consistent with previous report, allows reproducing $C$ – $V$ and $G$ – $V$ curves on the whole frequency and gate voltage ranges and monitoring the quality of dielectric stacks for the optimization of the manufacturing process.

Traditional metrology has been unable to adequately address the needs of the emerging integrated circuits (ICs) at the nano scale; thus, new metrology and techniques are needed. For example, the reliability challenges in fabrication need to be well understood and controlled to facilitate mass production of through-substrate-via (TSV) enabled three-dimensional integrated circuits (3D-ICs). This requires new approaches to the metrology. In this paper, we use the microwave propagation characteristics to study the reliability issues that precede the physical damage caused by electromigration in the Cu-filled TSVs. The pre-failure microwave insertion losses and group delay are dependent on both the device temperature and the amount of current forced through the devices-under-test. The microwave insertion losses increase with the increase in the test temperature, while the group delay increases with the increase in the forced direct current magnitude. The microwave insertion losses are attributed to the defect mobility at the Cu-TiN interface, and the group delay changes are due to resistive heating in the interconnects, which perturbs the dielectric properties of the cladding dielectrics of the copper fill in the TSVs. https://doi.org/10.1063/1.4992135.

There is an increasing number of reports on polar polymer-based Ferroelectric Field Effect Transistors (FeFETs), where the hysteresis of the drain current – gate voltage (I(d)-V(g)) curve is investigated as the result of the ferroelectric polarization effect. However, separating ferroelectric effect from many of the factors (such as charge injection/trapping and the presence of mobile ions in the polymer) that confound interpretation is still confusing and controversial. This work presents a methodology to reliably identify the confounding factors which obscure the polarization effect in FeFETs. Careful observation of the I(d)-V(g) curves, as well as monitoring the I(d)-V(g) hysteresis and flat band voltage shift as a function of temperature and sweep frequency identifies the dominant mechanism. This methodology is demonstrated using 15-nm thick high glass transition temperature polar polymer-based FeFETs. In these devices, room temperature hysteresis is largely a consequence of charge trapping and mobile ions, while ferroelectric polarization is observed at elevated temperatures. This methodology can be used to unambiguously prove the effect of ferroelectric polarization in FeFETs.

The low processing temperature of polymeric materials and their wide range of applications make polar polymer based ferroelectric memory very promising and attractive. The typical configuration of the ferroelectric memory cell is the FeFET (Ferroelectric field-effect-transistor) with the polar polymer incorporated in the gate dielectric stack. The memory effect in these devices originates from the polarization of the ferroelectric polymer film and results in a hysteresis of the Id-Vg characteristics. In this study, we fabricated FeFETs based on ultrathin poly-Si channel and CP1- polymer (glass-transition temperature (Tg ~260 C) as the gate dielectric. We investigated the hysteresis of the Id-Vg curves over a wide range of temperatures and frequencies. We observed the effects of thermocycling on the device, such as the change of the hysteresis loop direction at temperatures close to Tg (associated with the change of the dominant hysteresis mechanism), and the simultaneous significant decrease in gate leakage current (which may indicate significant reduction of active defects in the polymer layer). The reversibility of the observed phenomena was also investigated through consecutive thermocycles. Soaking the chip in warm water (60 C) for 3 hours changes the magnitude of the hysteresis loop without changing the direction. The gate leakage current also remains very low. Thus, humidity may play some role in the hysteresis magnitude but not the loop direction, nor does it play any role in the leakage current. In this paper, we will discuss possible explanations of these observations.

We propose a physical model for the fast component ( \( s) of the positive bias temperature instability (PBTI) process in SiO x /HfO2 gate-stacks. The model is based on the electron-phonon interaction governing the trapping/emission of injected electrons at the preexisting defects in the dielectric stack. The model successfully reproduces the experimental time dependences of the \(V_{\mathrm {{TH}}}\) shift on both stress voltage and temperature. Simulations allow the extraction of the physical characteristics of the defects contributing to PBTI, which are found to match those assisting the leakage current in these stacks (i.e., oxygen vacancies).

InGaAs MOS C-V and G-V characteristics are measured under illumination to identify regions of strong minority carrier response related to surface inversion. For the MOS structure with n-type substrate biased in inversion, a high density of surface states in the proximity of the valence band edge is present that masks the response of light generated minority carriers at room temperature. Much stronger effect of illumination is observed at low temperature where the surface-state response is suppressed due to carrier freeze out. On the other hand, for the MOS structure with p-type substrate, strong minority carrier response under illumination is readily observed in inversion even at room temperature, reflecting that the density of surface states near the edge of conduction band is negligible. All the data can be explained in the framework of small-signal equivalent circuit, by modeling the minority carrier generation with a light-dependent conductance plugged in between the conduction band and the valence band. The model is validated against the measured MOS conductance with and without light in inversion.

We report on the impact of H2 high-pressure annealing (HPA) onto In0.7Ga0.3As MOSCAPs and quantum-well (QW) MOSFETs with Al2O3/HfO2 gate-stack. After HPA with process condition of 300 °C, H2 ambient and pressure of 20 atm, we observed notable improvements of the capacitance–voltage (CV) characteristics in InGaAs MOSCAPs with Al2O3/HfO2 gate-stack, such as reduction of equivalent-oxide-thickness and less frequency dispersion in the accumulation region. There was 20% improvement of the interfacial trap density ( $D_{{\rm {it}}})$ . Then, we incorporated the HPA process into the fabrication of sub-100-nm In0.7Ga0.3As QW MOSFETs, to investigate the impact of HPA process. After HPA process, the device with $L_{g} = 50$ nm exhibits improved subthreshold-swing (SS) = 105 mV/decade, in comparison with SS = 130 mV/decade for the reference device without HPA process. Finally, we carried out reliability assessment under a constant-voltage-stress (CVS), and it turns out that the HPA process was effective in mitigating a shift of threshold voltage ( $\Delta \text{V}_{T})$ during the CVS. These are attributed to the effective passivation of oxide traps in the high- $k$ dielectric layer and interfacial traps, after HPA process in the H2 ambient.

Instability of InGaAs channel nMOSFETs with the Al2O3/ ZrO2 gate stack under positive bias stress demonstrates recoverable and unrecoverable components, which can be tentatively assigned to the pre-existing and generated defects, respectively. The recoverable component is determined to be primarily associated with the defects in the Al2O3 interfacial layer (IL), the slow trapping at which is responsible for the power law time dependency of the threshold voltage shift and transconductance change. The fast electron trapping in the ZrO2 film exhibits negligible recovery, in contrast to the Si-based devices with a similar high-k dielectric film. Generation of new electron trapping defects is found to occur in the IL, preferentially in the region close to the substrate, while trap generation in the high-k dielectric is negligible.

We introduce a data analysis methodology for multifrequency charge-pumping (CP) measurements, which allows extracting both spatial and energy profiles of the CP-active traps in the gate dielectrics along with the defect energy characteristics. The analysis is based on the charge trapping/detrapping model accounting for carriers tunneling between the substrate and the oxide traps and multiphonon-assisted structural trap relaxation associated with charge carrier localization in the trap. Comparison of the spatial and energy trap distribution profiles obtained from CP data collected on a set of high-k dielectric gate stacks of different thicknesses facilitate the calibration of the model parameters. Extraction of the bulk trap characteristics, including trap ionization and relaxation energies, extends the utility of the CP technique from quantifying defect density toward identifying the nature of defects in the dielectric.

Capacitance-voltage ( $C$ – $V$ ) measurement and analysis is highly useful for determining important information about MOS gate stacks. Parameters such as the equivalent oxide thickness (EOT), substrate doping density, flatband voltage, fixed oxide charge, density of interface traps ( ${D}_{ \rm {it}}$ ), and effective gate work function can all be extracted from experimental $C$ – $V$ curves. However, to extract these gate-stack parameters accurately, the correct models must be utilized. In Part I, we described the modeling and implementation of a $C$ – $V$ code that can be used for alternative channel semiconductors in conjunction with high- $k$ gate dielectrics and metal gates. Importantly, this new code (CV ACE) includes the effects of nonparabolic bands and quantum capacitance, enabling accurate models to be applied to experimental $C$ – $V$ curves. In this paper, we demonstrate the capabilities of this new code to extract accurate parameters, including EOT and ${D}_{ \rm {it}}$ profiles from experimental high- $k$ on Ge and In0.53Ga0.47As gate stacks.

A methodology for the evaluation of ultra-fast interfacial traps, using jitter measurements as a probe, is developed. This methodology is applied to study the effect of PBTI stress on the density of ultra-fast electron traps (with 500 ps to 5 ns characteristic capture/emission times) in a high-k/Si nMOSFET. It is shown, that in spite of an observed increase of timing jitter after PBTI stress, this increase may not be correlated with an increasing density of interface traps. Rather, it is solely caused by a VT shift which simply decreases the output signal amplitude. The results indicate that ultra-fast (presumably interface) traps may not be affected by PBTI stress.

The superior transport properties of III-V materials make them attractive choices to enable improved performance at low power. This paper examines the integration challenges of III-V materials in advanced CMOS logic at or beyond the 11 nm technology node, and reports VLSI compatible junction, contact and gate stack process modules with Xj¬5x1019cm-3, ρc= 6 Ω.µm2 and Dit = 4 x 1012 eV-1.cm-2.

The accuracy of the split-CV mobility extraction method is analyzed in buried-channel InGaAs MOSFETs with a Al2O3 gate dielectric and an InP barrier, through a “simulated experiment” procedure using 2-D numerical device simulations that are preliminarily calibrated against experimental I-V and CV curves. The different error sources limiting the method accuracy are pointed out. It is suggested that, as a result of these errors, the split- CV method can appreciably underestimate the actual channel mobility in these devices, with an error of >;20% and >;50% on peak mobility and high-VGS mobility, respectively. The method should therefore not be adopted for accurate mobility measurement in this operating regime but only as a fast response technique providing a conservative estimation of channel mobility. Moreover, the method provides mobility values that rapidly drop below the peak value for decreasing VGS. It is shown that this behavior can be an artifact of the extraction method, which may mask physical mechanisms causing a real mobility drop with decreasing channel carrier density, such as Coulomb scattering mechanisms. This poses limitations to the adoption of split-CV mobility as a reference for mobility model assessment in this operating regime. The proposed methodology can be applied to other III-V FETs, including both heterostructure-based and inversion-mode devices.

Low frequency noise (LFN) characterization was performed on the HfSiON gate stacks fabricated with the SiON interfacial layers (ILs) and a La cap layer. The LFN data identified N and La related defects located in the IL/HK region.

In the present work, we studied Hall effect and resistivity at various temperatures in un-gated and gated MOSFET structures with different high-k gate oxides and buried modulation-doped InAlAs/InGaAs/InP quantum well (QW) channels. Data is obtained on mobility behavior as a function of top semiconductor barrier thickness, carrier concentration, nature of oxide, and annealing. Improvement of Hall mobility has been demonstrated with the increase of top barrier thickness. In the structures with 3nm-thick top barrier the Hall mobility of ~5500 cm2/Vs at room temperature was demonstrated with ALD oxides at sheet densities (1-2)x1012 cm-2. Degradation of mobility with reduction of screening at low carrier density and due to increased coulomb scattering after thermal annealing is demonstrated. Gated Hall measurements allowed to directly obtain mobility vs. carrier density characteristics, and also determine the interface trap density using CV's and Hall concentration data.

Hall electron mobility in buried QW InGaAs channels, grown on InP substrates with HfO 2 gate oxide, is analyzed experimentally and theoretically as a function of top barrier thickness and composition, carrier density, and temperature. Temperature slope α in μ ~Tα dependence is changing from α=-1.1 to +1 with the reduction of the top barrier thickness indicating the dominant role of remote Coulomb scattering (RCS) in interface-related contribution to mobility degradation. Insertion of low-k SiO x interface layer formed by oxidation of thin in-situ MBE grown amorphous Si passivation layer has been found to improve the channel mobility, but at the expense of increased EOT. This mobility improvement is also consistent with dominant role of RCS. We were able to a obtain a reasonable match between experiment and simple theory of the RCS assuming the density of charges at the high-k/barrier interface to be in the range of (2-4)×1013 cm-2.

Device technologies developed to address specific needs for neuromorphic systems include non-volatile memory (NVM), which can serve as microelectronic "synapses" for low-power mobile computing applications. Desirable memory stack characteristics include, among others, scalability, fast programming, low voltage and power operations, high retention and endurance, multi-state operation and 3D integration capability. Metal-oxide RRAM meets most of these requirements [1]; however, the critical capabilities such as symmetric and gradual conductance update, and potentiation and depression in spike-timing-dependent-plasticity scheme have not been demonstrated. In this study, we show that hafnia-based filamental RRAM devices are capable of gradual multi-level switching at ultra-fast (ps) time scale at low operation voltages (< 1V). This enables high frequency/bandwidth operations with extremely low energy switching. RRAM devices are formed by crossbar 50x50 nm MIM capacitors fabricated with an ALD polycrystalline 5nm HfO2 film and TiN electrodes. An ultra-fast pulse setup (Fig. 1) provides precise control over the power delivered to the cell and removes the need for a current compliance control (1R configuration). Resistance is shown to stepwise increase or decrease depending on voltage value and polarity (Fig. 2). To evaluate how synaptic weight can be modulated by the time between the incoming signals, we investigated dependency of the RRAM resistance on time between the consequent pulses (Fig. 3). Reducing the time interval between pulses below 2 ns results in significant amplification of their effect on resistance. It’s consistent with theoretical expectations that, by briefly increasing local temperature [2], the first pulse magnifies the structural changes inducing by the subsequent pulse. To emulate the effect of time window between the pulses from pre- and post- synaptic neurons, a pair of pulses of positive (pre-synaptic) and negative (post-synaptic) polarity was applied to the same electrode (Fig. 4). In bi-polar switching, a negative polarity pulse induces resistance change in the same direction as a positive pulse applied to the opposite electrode. Potentiation or depression were observed depending on a positive pulse preceding or following the negative one, consistent with the reported brain-inspired operations. A very short time interval between incoming signals enabling potentiation/depression processes implies extremely fast neuromorphic system operations capabilities. G. Bersuker et al., J. Comput. Electron. 16, 1085, 2017 D. M. Nminibapiel et al., EDL 38, 326, 2017 Figure 1

Current overshoot during forming/SET of RRAM devices is frequently considered one of the key factors contributing to variation of the formed filament [1,2,4,5]. It is generally believed that to minimize variation, the current overshoot should be controlled by minimizing the device parasitics [2,4,5]. On the other hand, there are reports suggesting that RRAM requires an optimum energy to form a robust filament [3,6,7]. In this paper, we show that for RRAM systems with compliance control, such as 1T-1R, this forming energy is linked to the current overshoot which in turn is linked to capacitance. In other words, blindly minimizing parasitics is a poor strategy. Instead, the device should be engineered for optimum (not minimum) parasitics. Previously, it has been shown that the duration of the overshoot current is determined by the parasitic capacitance [1]. A surprising consequence is that even with a long programming pulse, the actual current that flows through the RRAM can become very short when current compliance is used. For devices with extremely low parasitics, such as in actual production devices, it can lead to an effective programming pulse duration that is picoseconds or less. This unexpected ultra-short effective programming pulse means that an unexpectedly low amount of energy is dissipated into the filament and can lead to poor retention and endurance. Thus, it suggests that the common idea of minimizing the parasitics is counter-productive. In order to verify, high speed 1T-1R measurements were done with the experimental set up shown in Fig. 1. Five similar sized crossbar devices with different drain capacitances were measured. The details of the devices are given in Fig. 2. As shown in Fig. 1, we measure the current at the source side of the transistor by connecting it to the 50 Ω input of the oscilloscope (Fig. 3). This is not a direct measurement of the current going through the RRAM because only part of the charge of the parasitic capacitor flows through the transistor. The current paths are depicted in Fig. 4. Nevertheless, the measured current mirrors the current flowing through the RRAM and serves as a proxy. The current peaks (Fig. 3) for devices 1 to 3 decay in that order. These devices have similar capacitance but the post forming resistance decreases by the same order. For devices 4 and 5, that do not have a probe pad connected to the drain, the capacitances are much lower and thus an extremely short current peak is seen for device 4 and almost no current peak is observed for device 5. The missing current peak is due to finite sampling resolution (12.5 ps) of the oscilloscope and the current pulse being very short. To verify, we compare the results with spice modeling as shown in Fig. 4, including reflections of the fast pulse due to inevitable impedance mismatch of the device (not designed for RF measurements) and with a resolution of 12.5 ps to match that of the oscilloscope. For the simulations, the RRAM device was modeled as a variable resistor with resistance changing linearly from 20 MΩ to about 6 kΩ. Good agreement between the spice simulations and the measured current is achieved, as shown in Fig. 5. The simulated current waveforms, with 12.5 ps sampling resolution for all 5 devices are shown in Fig. 6. The peak is noticeable for device 5. In Fig. 7 we focus only on device 5; the sampling resolution is changed to 2 ps and the peak is clearly recovered. The agreement between simulation and experiment confirms our model prediction that (1) no matter how low the parasitic component is, current overshoot exists; (2) the magnitude of the current overshoot is determined by the applied voltage and the RRAM resistance, not the parasitic capacitance; (3) the parasitic capacitance determines the duration of the current overshoot. Fig. 8 shows the simulated current overshoot for devices of the same Rform and forming voltage but different parasitic capacitance. Clearly, both (2) and (3) affects the energy dissipated into the RRAM filament. With a targeted resistance, the only control available is the applied voltage and parasitic capacitance. When the parasitic capacitance is very low, the voltage must increase to provide optimum energy for a stable RRAM with long retention times and good endurance. However, high voltage tends to amplify the stochastic nature of the filament and can only go so far before losing control. Thus, the main avenue left for optimizing RRAM is to optimize the parasitics instead of minimizing it – a major departure from common wisdom. Figure 1

We report on enhanced room-temperature detection of terahertz radiation by several connected field-effect transistors. For this enhanced nonresonant detection, we have designed, fabricated, and tested plasmonic structures consisting of multiple InGaAs/GaAs pseudomorphic high electron-mobility transistors connected in series. Results show a 1.63-THz response that is directly proportional to the number of detecting transistors biased by a direct drain current at the same gate-to-source bias voltages. The responsivity in the saturation regime was found to be 170 V/W with the noise equivalent power in the range of 10-7 W/Hz0.5. The experimental data are in agreement with the detection mechanism based on the rectification of overdamped plasma waves excited by terahertz radiation in the transistor channel.

We describe the compact model that captures the new physics involved in Thin Film Transistors with non-ideal contacts, where the contact itself controls the carrier density under the contact. Such a contact could be modeled as a non-linear transmission line consisting of thin film transistors with leaky gates. However, we show that the compact model that incorporates a contact thin film transistor and non-ideal diodes can adequately describe experimental data, such as dependencies of field effect mobility on the gate length for different materials systems ranging from amorphous silicon to organic semiconductors. The model can also describe the capacitance-voltage characteristics and suitable for implementation in circuit simulators, such as AIM-Spice.

quantum well (QW) heterostructures [1{3].The strain-induced valence band splitting in Ge/GeSi structures decreases theefiective masses of two-dimensional holes and the binding energies of conflnedacceptors compared with those in bulk Ge, in contrast to the donors whose bindingenergy is known to increase due to additional conflnement of the wave functionby the QW potential. In this paper, we employ the newly developed technique [3]to distinguish between difierent type shallow acceptor centers contributing to themagnetoabsorption in the THz range in Ge/GeSi heterostructures. The methodis based on measuring the difierential impurity magnetoabsorption in THz rangeat the modulated bandgap optical excitation. The absorption signal is due to free(137)

Display Omitted A defect spectroscopy technique is developed to investigate high-? dielectrics.The method exploit simultaneous simulations of I-V and multi-frequency C-V and G-V.Sensitivity curves for IV, CV and GV are used to determine the defect map.The defects map and the native oxide thickness is determined for III-V MOS.Other physical parameters of the MOS system are determined consistently. In this paper we present a novel defect spectroscopy technique to investigate the properties of high-? metal-gate oxides. This technique, based on the simultaneous simulations of I-V, C-V and G-V curves at different frequencies, allows profiling the distribution of interfacial and bulk defects inside the gate oxide and investigating the composition of the high-? stacks on III-V materials. The proposed technique is applied to investigate the properties of high-? stacks of InGaAs MOSFETs.

We present a comprehensive simulation framework to interpret electrical characteristics (I-V, C-V, G-V, Charge-Pumping, BTI, CVS, RVS, ∶) commonly used for material characterization and reliability analysis of gate dielectric stacks in modern semiconductor devices. By accounting for the physical processes controlling charge transport through the dielectric (e.g. carrier trapping/de-trapping at the defect sites, defect generation, etc.), which is modeled using a novel approach based of material characteristics [1], [2], the simulations provide a unique link between the electrical measurements data and specific atomic defects in the dielectric stack. Within this methodology, the software allows an accurate defect spectroscopy by cross-correlating measurements of pre-stress electrical parameters (IV, CV, BTI). These data are then used to project the stack reliability through the simulations of stress-induced leakage current (SILC) and time-dependent dielectric degradation trends, demonstrating the tool capabilities as a technology characterization/optimization benchmark.