50 results on '"Dlugosz R"'
Search Results
2. Advanced Training Set Generator for Use in Self-Organizing Neural Networks
3. Realization of the conscience mechanism in CMOS implementation of winner-takes-all self-organizing neural networks
4. Integrated CMOS GSM baseband channel selecting filters realized using switched capacitor finite impulse response technique
5. Hardware Implementation of Selected Statistical Quantities for Applications in Automotive V2I Communication System
6. A Parallel Adaptive LMS FIR Filter Realized in CMOS Technology
7. A programmable current-mode digital-to-analog converter with correction of nonlinearity of input-output characteristics
8. Performance Evaluation of Block-Based Adaptive Algorithms
9. Multi-Rate Signal Processing with the Use of Filter Banks Composed of Parallel FIR Filters
10. Parallel Programmable Asynchronous Neighborhood Mechanism for Kohonen SOM Implemented in CMOS Technology
11. Hierarchical Asynchronous Multiplexer for Readout Front-End ASIC for Multi-Element Detectors in Medical Imaging
12. Analog, Continuous Time, Fully Parallel, Programmable Image Processor Based on Vector Gilbert Multiplier
13. Current Mode Analog Kohonen Neural Network
14. AnaDig--An Educational Chip for VLSI Device Characterization
15. High-precision analogue peak detector for X-ray imaging applications
16. 0.35 μm 22μW Multiphase Programmable Clock Generator for Circular Memory SC FIR Filter For Wireless Sensor Applications
17. A new, low cost, precise measurement card for testing of ultra-low power analog ASICs.
18. An FPGA implementation of the asynchronous programmable neighborhood mechanism for WTM Self-Organizing Map.
19. A flexible winner takes all neural network with the conscience mechanism realized on microcontrollers.
20. Kohonen winner takes all neural network realized on microcontrollers with AVR and ARM cores.
21. A low power current-mode binary-tree WTA / LTA circuit for Kohonen neural networks.
22. Influence of information leakage in analog memory on learning Kohonen network on silicon.
23. Design and optimization of operational amplifiers for SC systems - a comparative study in CMOS 0.18 µm, 0.35 µm, and 0.8 µm technologies.
24. Power and area efficient circular-memory switched-capacitor FIR baseband filter for WCDMA/GSM.
25. Current-mode memory cell with power down phase for discrete time analog iterative decoders.
26. Asynchronous front-end asic for X-ray medical imaging applications implemented in CMOS 0.18μm technology.
27. Experimental Kohonen neural network implemented in CMOS 0.18μm technology.
28. CMOS programmable asynchronous neighborhood mechanism for WTM kohonen neural network.
29. Experimental results of CMOS-implemented conscience mechanism applied for WTA networks.
30. Flexible Ultra Low Power Successive Approximation Analog-to-Digital Converter with Asynchronous Clock Generator.
31. Current Mode Euclidean Distance Calculation Circuit for Kohonen's Neural Network Implemented in CMOS 0.18?m Technology.
32. Analog-Counter-Based Conscience Mechanism in Kohonen's Neural Network Implemented in CMOS 0.18 μm Technology.
33. An Examination of the Effect of Feature Size Scaling on Effective Power Consumption in Analog to Digital Converters.
34. Ultra Low Power Current-mode Algorithmic Analog-to-digital Converter Implemented In 0.18 /spl mu/m CMOS Technology For Wireless Sensor Network.
35. New Ultra Low Power Switched - Current Finite Impulse Response Filters Realized In Cmos 0.18 /spl mu/m Technology.
36. Implementation Of The Conscience Mechanism For Kohonen's Neural Network In Cmos 0.18 /spl mu/m Technology.
37. Analog baseband filtering realized using switched capacitor finite impulse response filter.
38. CMOS programmable asynchronous neighborhood mechanism for WTM kohonen neural network
39. Low power current-mode binary-tree asynchronous Min/Max circuit
40. Experimental Kohonen Neural Network Implemented in CMOS 0.18μm Technology
41. An optimized learning algorithm based on linear filters suitable for hardware implemented self-organizing maps
42. 3.125 Gb/s Power Efficient Line Driver with 2-level Pre-emphasis and 2kV HBM ESD Protection
43. Analog baseband filtering realized using switched capacitor finite impulse response filter
44. Ultra Low Power Current-mode Algorithmic Analog-to-digital Converter Implemented In 0.18 μm CMOS Technology For Wireless Sensor Network
45. Finite impulse response filter banks realized using switched capacitor technique
46. New Ultra Low Power Switched - Current Finite Impulse Response Filters Realized In Cmos 0.18 μm Technology
47. 3.125 Gb/s power efficient line driver with 2-level pre-emphasis and 2 kV HBM ESD protection.
48. Impact of Hepatic Artery Variations and Reconstructions on the Outcome of Orthotopic Liver Transplantation.
49. First European Case of Simultaneous Liver and Pancreas Transplantation as Treatment of Wolcott-Rallison Syndrome in a Small Child.
50. Novel techniques for a wireless motion capture system for the monitoring and rehabilitation of disabled persons for application in smart buildings.
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