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This article describes the methodology used to derive the 22FDX® Fully-Depleted Silicon-On-Insulator (FDSOI) Chip Package Interaction (CPI) qualification envelope. In the first part it is discussed how the individual market segments influence the technology features and offerings, including BEOL stacks and package types. In the following, the criteria used for the selection of BEOL stacks, die and package sizes and the interconnect type for the qualification envelope are summarized and explained. The three CPI qualification stages and related characterization methods are presented. CPI test structures used in the envelope are reported and their placement on the technology qualification vehicles (TQV) is outlined on the basis of flip chip TQV. Finally, the paper presents the passing 22FDX® package and board level reliability results obtained for wire bond, flip chip, as well as wafer level fan-in and fan-out package technologies. Key aspects of the individual qualifications are reported.

In previous works, the resulting damages in the back end of line (BEoL) stack triggered by Copper pillar (Cu-pillar) shear-off events were evaluated and classified [1]. It was determined, especially by utilizing acoustic emission (AE) measurements, that damage events consist of multiple extremely fast sub-processes. The objective of this work is the development of an approach to enable the identification of the areas of damage initiation and comprehend the damage propagation in a BEoL stack under mechanical load by triggering only the initial sub-processes. Mechanical stress was induced into the BEoL stack utilizing a displacement-controlled sub-critical Cu-pillar loading approach with the approximate parametrization determined in previous experiments [1]. During mechanical loading, AE signals were constantly measured. As soon as significant acoustic events were detected, the experiment was aborted. The occurring damages were analyzed utilizing a customized nano X-ray computed tomography (nXCT) setup and focused ion beam (FIB) milling as well as scanning electron microscopy (SEM) imaging. In this work, a methodology could be developed to enable the evaluation of BEoL damages in an early, sub-critical stage. These results provide a better understanding of the damage formation and propagation in the BEoL stack and enable a design optimization procedure for the most damage prone areas.

Standardization in optical networking enables operators to benefit from using open source components. We investigate quality of transmission of open source hard- and software in the Deutsche Telekom R&D SASER network and optimize the working point.

In order to address the Chip-Package Interaction (CPI) risks associated with advanced silicon packaging, GLOBALFOUNDRIES has developed Finite Element (FE) models to simulate the mechanical stress in the Backend of Line (BEoL) and Far Back End of Line (FBEoL) during the flip-chip assembly process and multiple reflow (MR) cycling test. This paper discusses the complexity involved in the CPI mechanical performance and use of various modeling methods to assess and mitigate the CPI failure risk. The paper also highlights the quantitative package model validation against experimental data based on newly developed Cohesive Zone Material (CZM) modeling methodology.

In order to address the Chip-Package Interaction (CPI) risks associated with the Wafer Level Chip Scale Package (WLCSP), GLOBALFOUNDRIES has developed Finite Element (FE) models to simulate the mechanical stress in the Backend of Line (BEoL) and Far Back End of Line (FBEoL) during mass reflow process. This paper discusses the CPI failure risk associated with WLCSP, modeled with and without the redistribution layers (RDL) introduction above the BEoL. The WLCSP model has been modified to assess the design variations within the RDL and the FBEoL. The paper also highlights the FE model verification between the two-dimensional (2D) versus the three-dimensional (3D) models and validation by comparing the simulation results to the experimental test data.

This paper describes major contributing factors to the CPI risk and reveals the mitigation strategy successfully applied jointly by GLOBALFOUNDRIES as the silicon supplier and Qualcomm Technologies, Inc., as the customer responsible for packaging. This strategy involves thermo-mechanical modelling, data collection on wafer level using shear test to assess the BEoL-stability, Cu Pillar process development and optimization. The qualification of these process changes had been completed and implemented in volume production. The paper also discusses mechanical wafer level and thermo-mechanical package modeling approaches. A model has been applied to determine the critical factors on BEoL stress/strain during the flip-chip assembly reflow process. These factors include for instance the Cu Pillar bump geometry and stack up. The results of the modelling work were used to set up experiments to further mitigate CPI related failure modes in BEoL on the package level. GLOBALFOUNDRIES and Qualcomm Technologies, Inc., assessed Cu Pillar design related rules such as Cu Pillar diameter and height as well as the Cu Pillar stack up. Process improvements were carried out to reduce the undercut of the barrier underneath the Cu Pillar. The paper reveals how effectively an optimized Cu Pillar design and improved Cu Pillar processing can contribute to the risk mitigation of CPI failure modes in the BEoL for critical package designs and assembly processes with low margin against BEoL fracture during solder reflow. Furthermore, process improvements applied to enhance the BEoL stack strength were investigated and have been implemented in high-volume production. A strong correlation was established between data collected on wafer level to assess the BEoL strength and data collected on package level.

This paper describes a systematic approach to the identification of primary contributing factors to the Chip Package Interaction (CPI) risk and reveals the mitigation strategy successfully applied by GLOBALFOUNDRIES. The strategy includes modeling at bump and package level, gathering experimental data on blanket dielectric back end of line (BEoL) films, collecting data on wafer material with a complete BEoL stack, and finally using readouts on the package level. Advanced measurement methods generate data on the wafer level to achieve fast turn-around times. These methods include: (i) Dual-Cantilever Beam (DCB) test, (ii) Modified Edge Lift-off Test (MELT), (iii) Single Pillar Shear Test (SPST) and (iv) Bump Assisted BEoL Stability Indentation (BABSI) tests. The paper describes the methodology to gather data on the wafer level with a complete BEoL metallization stack that assesses the BEoL integrity. Furthermore, the package level thermomechanical modeling approach is discussed. The model has been used to determine the critical factors on BEoL stress/strain during the flip-chip assembly reflow processes. Silicon design-related factors in the BEoL that contribute to the risk for CPI related failures were investigated and options to reduce the CPI risk are discussed. Finally the paper reveals package level qualification data flip-chip CSP and wafer level packaging Fan-In for advanced technology nodes.

This paper summarizes the work which was done to understand the die warpage at different temperatures and the influence on the assembly yield in a FCCSP package in combination with Cu pillar first level interconnects. A Cu BEoL stack with two ultra-thick metal (UTM) layers was selected as one of the most critical learning vehicles to understand and quantify the effect of a high effective Cu thickness in combination with a reduced die thickness to match the package form factor requirements. With this vehicle, the “BEoL to bulk silicon thickness”-ratio can reach up to 10% or more, depending on die thickness.Based on a bi-material strip working hypothesis (bulk silicon + BEoL stack) an experiment design was devised with the aim of maximizing the assembly yield and minimizing the die warpage. Die thickness, Cu pillar solder height, BEoL metal density and assembly parameters have been selected as experiment design factors. The FC assembly was run in multiple experiments in a standard reflow process. The assembly yield was determined by inline x-ray inspection for non-wet failures and electrical test on packaged samples.The Shadow Moire technique was used to collect substrate and die warpage hysteresis data in the temperature range in between RT and 260°C reflecting the behavior during the solder reflow process. The die warpage hysteresis was identified as a key factor for high assembly yields: the lower the hysteresis the lower the assembly yield loss.Additional cross sections were prepared to confirm the results of the X-Ray inspection and electrical tests. The critical fails occurred at the die corners showing non-wetting of the solder and matched the working hypothesis.The collected die warpage hysteresis data matched well with a prediction of the warpage hysteresis during the solder reflow using the rule of mixture for the BEoL CTE. With the collected results a forecast of the assembly yield loss in dependency of the different factors is possible.After solving the assembly challenges the packages were stressed in standard package reliability tests and passed the requirements. Additionally, assembly robustness tests were run (Multiple reflow, quick temperature cycle) and passed with margin.

Recently, Wafer Level Packaging (WLP) has been in high demand, especially in mobile device applications as a path to enable miniaturization while maintaining good electrical performance. The relatively inexpensive package cost and simplified supply chain are encouraging other industries to adapt WLP capabilities for radio frequency (RF), communications/sensing (mmWave) and automotive applications. However, to date its application space has been limited to a small die form factor due to challenging chip board interaction (CBI) control. The combination of ultralow dielectric constant (ULK) based advanced silicon technology and WLP is another challenge for industry to overcome.In this article, to systematically address the CBI, a large test vehicle based on 22-nm fully depleted silicon on insulator (FD-SOI) technology platform and WLP technology is described. In particular, CBI during drop test and temperature cycle on board is investigated and its failure mode analysis is discussed. The impact of silicon die thickness and ball grid array (BGA) metallurgy is also explored.

Advanced silicon technology nodes are using backend of line (BEOL) stacks consisting of ultra low-k (ULK) materials. ULK materials in combination with Flip Chip (FC) packages and Cu pillar first level interconnects require a chip package interaction (CPI) characterization strategy. Package level tests are needed to account for the thermal mismatch or warpage induced stress between the silicon die and the polymer substrate.

Crack propagation in BEoL (back-end of line) interconnect structures is a concern in terms of chip reliability. Due to the application of porous ultra low-k (ULK) materials, a careful trade-off is necessary between reducing signal delays and also decreasing mechanical properties of the interconnect structures. Therefore, fast and reliable measurement techniques for characterizing mechanical properties as film adhesion and fracture toughness are needed. In the present investigation, a camera assisted double-cantilever beam (DCB) technique has been used to obtain locally resolved adhesion measurements within the die. Two chip designs, produced in leading-edge technology nodes with two different ULK materials, were tested. The G"c values measured within the die show a correlation to density and arrangement of the Cu structures. ULK containing metallization levels with lowest k values have been identified as preferred crack paths. The measurements are compared with results of the four-point bending (4PB) test not having the local resolution of DCB but typically used for unpatterned film stacks and possessing a mode I/II load mixity. The DCB tests yield reduced G"c values compared to the 4PB tests, which can be understood as result of the different loading modes of both techniques.

For mobile applications, advanced silicon technology nodes are using Back End Of Line (BEOL) stacks with Ultra Low-k (ULK) materials. Employing these ULK materials in combination with advanced Flip Chip (FC) packages requires a profound understanding of the chip package interaction (CPI). To match high I/O and reduced pitch requirements, Cu pillars are widely used as first level interconnect technology [MCC15, KAU15, KUE12 LEE013, RYA12]. In general, Cu pillars are known to increase the stress in the BEOL stacks compared to conventional SnAg interconnects. More viscoplastic deformation occurs in SnAg interconnects and reduces the stress in the BEOL. Therefore, the combination of Cu pillars and aggressive low cost, high performance BEOL stacks with ULK materials requires a systematic concept for the CPI qualification. This includes window studies and margin tests and requires a close collaboration of silicon foundry and the assembly facility.

To cope with the forecasted traffic increase in mobile networks small cell deployments are considered as a key enabler. Compared with Macro Sites (MS), Small Cells (SC) will be deployed on a larger scale and thus require a more cost effective transport connection than in today's CWDM backhaul networks. An important question for this transport network is “Is it preferable to have a common converged transport network in the access aggregation to cope with fixed mass market and potentially new small cell sites or is a separate network for the SC better?”. This paper investigates NG-PON2, and WDM-PON with different flavours as well as CWDM as a reference for different backhaul and fronthaul architectures. The results show the cost for the different transport options as a function of number of deployed small cells considering both FTTC and FTTH areas. From these results one can conclude that re-using an already deployed mass market solution is not always the most beneficial choice.

Next-generation optical access technologies and architectures are evaluated based on operators' requirements. The study presented in this article compares different FTTH access network architectures. Additionally, the impact of new business models on network architectures is discussed.

Fibre to the Home (FTTH) networks enable high‐speed access and require the deployment of new fibre‐based in‐building networks. There are challenges for network operators with respect to cost‐efficient deployment of in‐building networks: important points are concerned with network design and planning, environment and regulation and with network termination. Associated home networks have to be able to cope with the increasing bit rate demands of emerging Internet services in a sustainable way; the energy efficiency of home communication networks has become a topic of increasing importance.

Mobile traffic is heavily increasing in the last years and a massive continuous growth is forecasted for the next decade. To cope with this significant traffic increase in mobile networks and the further evolving competitive market situation, operators are looking for solutions to increase the capacity of their mobile networks, while keeping the cost low. Besides enhancements of mobile radio technology and adding new spectrum to the existing sites, densification of radio sites, by so called small cells, is considered as a very promising option to increase capacity. Adding small cells to the already existing macro cell layer lead to heterogeneous networks (HetNet). Because of the scarce radio spectrum it is most likely that the radio sites in HetNets will use the same frequencies and therefore create interferences. To mitigate this impact different coordination methods have been proposed creating new challenging requirements on the transport network compared to today's backhaul. Cost effective and scalable transport solutions are an important fundament for wide and successful deployment of HetNets. This paper investigates and assesses techno-economically different architectures for backhaul and fronthaul transport of existing and newly deployed radio sites in HetNet architectures taking requirements from interference co-ordination into account.

Fixed-mobile convergence initially focused on optimizing fixed and mobile telephone infrastructure for voice services. The appearance of VoIP and smartphones, the growing popularity of social networks and video hosting services, the emerging of 5G, Internet of Things, machine-to-machine communication and ever newer over-the-top services motivated manufacturers, network operators and service providers to refocus and data delivery. The tutorial highlights the structural and functional aspects for efficiently instrumenting this convergence process, including infrastructure considerations, network function virtualization, software defined networking, unified functionality. The presentations are embedded into an overview of the past efforts, a summary of the state of the art, and a look-ahead for future communications networks. The authors are members of the Combo European consortium working on fixed-mobile convergence.

With the recent increase in Gold (Au) wire cost; Copper (Cu) wire becomes an attractive way to manage overall package cost. On the other hand, Copper wire bonding introduces much higher mechanical impact to underlying BEoLstructures and actives because of the higher stiffness and lower ductility of Copper compared to Gold. These trends are accompanied by the application of new porous or nano-particle filled materials like low-k and ultra low-k materials for Back-end of line (BEoL) layers of advanced CMOS technologies. As a result, higher delamination and cracking risks in BEoLstructures underneath bonded areas represent an increasing challenge for the thermo-mechanical reliability requirements. To overcome the related reliability issues the authors performed a two level nonlinear FEM-simulation approach. Initially nonlinear axisymmetric modeling and simulation of the copper bonding process are coupled with a spatial simulation model of the whole BeoL and bond pad structure. Cracking and delamination risks are estimated by a surface based cohesive contact approach and the utilization of a crushing foam constitutive material model for ultra low-k materials.

In order to address the Chip-Package Interaction (CPI) challenges at an early stage of the product development, GLOBALFOUNDRIES has developed Finite Element (FE) models to simulate the mechanical stress in Backend of Line (BEoL). This paper elaborates the methodology involved in developing a single bump simulation model to assess failure risk under mechanical loading. The paper also highlights the FE models validation by comparing the simulation results to the experimental test data.

Kurzfassung Die Möglichkeiten transmissionselektronenmikroskopischer Analysen an komplexen Werkstoffsystemen sind in hohem Maße von den verfügbaren Präparationsmethoden abhängig. Die Focused-Ion-Beam-Technik mit der Möglichkeit hochqualitativer Zielpräparationen mit Genauigkeiten im Bereich 10 -8 m erweitert das Anwendungsspektrum beträchtlich. Die vorgestellte Methode nutzt einen metallographischen Schliff, an dem mit lichtoptischen oder rasterelektronenmikroskopischen Mitteln eine Charakterisierung und Auswahl der speziell interessierenden Details stattfinden kann. Untersuchungsobjekt ist das Grenzflächensystem einer Lötverbindung, wie sie bei der Montage von Chips entsteht. Der metallographische Schliff wird für die Arbeit im Focused-Ion-Beam-Gerät vorbereitet, mit einem Liftout-System wird eine Lamelle entnommen und an einem TEM-Probenträger befestigt. Die finalen Polierschritte erzeugen eine TEM-Probe, die für eine Reihe von zusätzlichen Untersuchungen (analytische TEM, Beugungsuntersuchungen) besonders geeignet ist.

Optical systems and technologies have been radically changing the telecommunication networks for past 15 years; today wavelength division multiplexing (WDM) technology, optical amplifiers, and simple optical switching elements like optical add-drop multiplexers (OADMs) are used in the backbone networks of all operators worldwide. Optical systems nowadays provide the basis for cost-effective transmission of large amounts of bandwidth over the Internet, and will enable its future growth and the spreading of new applications and services. This paper summarizes the main trends in optical networking and investigates potential future application areas. Optical system technology has become so pervasive in network design that it needs to be considered in the context of provisioning new applications and services. Therefore, the analysis is not limited to the aspects of physical transmission, but also takes into account recent developments in integrated network design as well as network control and management. The following sections describe the key functionalities of future optical network architectures, and the key findings of the theoretical analysis are supported by the results of a field trial of advanced transmission technology

This paper investigates the challenges for developing the current local area network (LAN)-based Ethernet protocol into a technology for future network architectures that is capable of satisfying dynamic traffic demands with hard service guarantees using high-bit-rate channels (80...100 Gb/s). The objective is to combine high-speed optical transmission and physical interfaces (PHY) with a medium access control (MAC) protocol, designed to meet the service guarantees in future metropolitan-area networks (MANs). Ethernet is an ideal candidate for the extension into the MAN as it allows seamless compatibility with the majority of existing LANs. The proposed extension of the MAC protocol focuses on backward compatibility as well as on the exploitation of the wavelength domain for routing of variable traffic demands. The high bit rates envisaged will easily exhaust the capacity of a single optical fiber in the C band and will require network algorithms optimizing the reuse of wavelength resources. To investigate this, four different static and dynamic optical architectures were studied that potentially offer advantages over current link-based designs. Both analytical and numerical modeling techniques were applied to quantify and compare the network performance for all architectures in terms of achievable throughput, delay, and the number of required wavelengths and to investigate the impact of nonuniform traffic demands. The results show that significant resource savings can be achieved by using end-to-end dynamic lightpath allocation, but at the expense of high delay.

Increasing bandwidth demand drives the need for next-generation optical access (NGOA) networks that can meet future end-user service requirements. This paper gives an overview of NGOA solutions, the enabling optical access network technologies, architecture principles, and related economics and business models. NGOA requirements (including peak and sustainable data rate, reach, cost, node consolidation, and open access) are proposed, and the different solutions are compared against such requirements in different scenarios (in terms of population density and system migration). Unsurprisingly, it is found that different solutions are best suited for different scenarios. The conclusions drawn from such findings allow us to formulate recommendations in terms of technology, strategy, and policy. The paper is based on the main results of the European FP7 OASE Integrated Project that ran between January 1, 2010 and February 28, 2013.