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This paper presents an innovative readout scheme that utilizes a pair of differential‐clocks‐assisted time‐to‐digital converter (DCA‐TDC) in CMOS image sensors (CISs). The DCA‐TDC utilizes only half the number of ordinary TDC delay chain units by employing a binary‐weighted search algorithm to determine the most significant bit (MSB) for fine quantization of a single‐slope analog‐to‐digital converter (SS ADC). Additionally, the layout area and dynamic power introduced by the improved DCA‐TDC delay chain are halved compared to an ordinary TDC delay chain. The proposed SS ADC is designed and simulated using the 0.11 μm standard CMOS proces, achieving an 11‐bit ADC with a column‐level power consumption of 65.4 μW, and a row conversion time of 2.72 μs, within a design environment featuring an analog voltage of 3.3 V, a digital voltage of 1.5 V, a clock frequency of 62.5 MHz, and a temporal resolution of 500 ps. Furthermore, this design achieves an effective number of bits (ENOB) of 10.71 and a figure of merit (FoM) of 110.5 fJ/step. By interpolating a DCA‐TDC, the quantization speed is enhanced compared to traditional SS ADCs, presenting an effective solution for high‐frame‐rate CIS implementations. [ABSTRACT FROM AUTHOR]

This paper proposes a power‐optimized column‐parallel cyclic analog to digital converter (ADC) for complementary metal oxide semiconductors (CMOS) image sensor readout circuits. The design combines a 2.5‐bit/cycle architecture with a comparator shutdown technique based on the comparator‐based switched‐capacitor (CBSC) circuits, which results in a significant reduction in the operating time of the threshold detection comparator compared with conventional CBSC circuits. This reduction in operating time leads to power savings as the threshold detection comparator can be shut down quickly. The paper also presents a comprehensive analysis of the nonideal factors of CBSC circuits and the coarse and fine conversion allocation scheme. The 10‐bit two‐stage comparator‐based cyclic ADC is designed in a 110 nm 1P4 M CMOS technology. Simulation results show that the effective number of bit (ENOB) is 9.7 bits, with each column consuming 103 μW of power. The proposed cyclic ADC has a figure of merit (FOM) of 123 fJ/conv‐step. Compared with conventional structures, the proposed design reduces the power consumption of the ADC by 34.3% while maintaining the same level of performance. [ABSTRACT FROM AUTHOR]

Summary: An analog background calibration approach is presented for the full calibration of pipeline analog‐to‐digital converters (ADCs). A well‐trained neural network acts close to the ideal 1.5‐bit stage, and its residue is compared with the real 1.5‐bit stage including gain error and amplifier nonlinearities. The detected error is used to compensate for the imperfect residue using four calibration polynomial coefficients. The corrected residue enters the second stage of the pipeline ADC and follows a normal path to achieve high resolution. The introduced structure is verified in a 12‐bit pipelined ADC composed of 11 stages; the first 10 stages have a 1.5‐bit structure, while the last stage is a 2‐bit flash. The sampling frequency is 100 MHz, and 10% non‐ideal factors (5% for each of the nonlinear and gain errors and 10% for the aggregated error) are considered for the first stage, while the input is 19.5 MHz sinusoidal waveform. A random noise is applied to the input to limit the effective number of bits (ENOB) to almost 11.8. The evaluation parameters of the ADC are extracted, signal‐to‐noise and distortion ratio increases from 39.14 to 72.91 dB, spurious free dynamic range improves from 40.94 to 79.69 dB, and the ENOB enhances from 6.2 to 11.82. The presented mechanism shows an acceptable accuracy in the high‐speed and high‐resolution ADCs. [ABSTRACT FROM AUTHOR]

This paper presents an ultra-low power comparator with minimum delay and low offset, used in successive approximation register analog-to-digital converters (SAR ADCs) for biomedical system-on-chips (SoCs). To reduce the power consumption, the proposed comparator is designed with a minimum supply voltage in the sub-threshold region. Additionally, intermediate switches are utilized in the design to serve two purposes: 1) breaking the connection between the latch and preamplifier parts during the pre-charge phase to reduce power consumption, 2) reducing the parasitic resistance of the discharge path during the evaluation phase to enhance effective transconductance of the latch ( g m e f f , l a t c h ). Furthermore, the proposed design incorporates, two transistors as auxiliary paths to increase the speed of discharging in the latching process. Overall, the proposed design aims to achieve a low power and high-performance comparator simulated at a frequency of 50 kHz using TSMC 65nm CMOS technology. The post-layout simulation results show that the proposed structure enjoyed from an ultra-low power consumption of 141.4 pW as well as excellent delay and offset with 357 ns and 3.32 mV values, respectively. The occupied area of the designed layout for the proposed comparator is 106.8 μm2 allowed us to embed it in multi-channel recording system on chips (SoCs). The Figure of Merit (FoM) of the proposed comparator is 0.000463 fVW/Hz. Moreover, the proposed comparator has been validated by using it in successive approximation conversion algorithm with a sampling frequency of 1 kS/s. [ABSTRACT FROM AUTHOR]

This work presents a novel 10-bit 2GS/s time-interleaved digital-to-analog converter (TI-DAC). The presented TI-DAC benefits from a combination of two 1 GHz hybrid sub-DACs and bootstrapped switches to multiplex the output voltage of each sub-DAC. In the presented TI-DAC, the dynamic non-idealities of each sub-DAC do not propagate to the main DAC output, making the design of each sub-DAC simpler. Also, using hybrid sub-DACs lead to a considerable reduction in the occupied area and power consumption. Besides, a new glitch neutralizer in the unit current cells is proposed to improve the DAC linearity. The design and post-layout simulations of this TI-DAC are carried out using Cadence Virtuoso tools in 65 nm CMOS technology. The achieved integral non-linearity and differential non-linearity parameters are better than 0.8 least significant bit (LSB) and 0.2 LSB, respectively. The proposed TI-DAC consumes 18.2 mW from a supply voltage of 1.2 V. Additionally, the spurious-free dynamic range of above 59 dB across the entire Nyquist band for the designed 2GS/s TI-DAC is achieved, considering only 0.034 mm2 of area occupation. [ABSTRACT FROM AUTHOR]

ABSTRACT This paper introduces a 4‐channel 24‐ to 28‐GHz RF front‐end MIMO system designed for 5G applications. The transmitter (Tx) and receiver (Rx) chips are fabricated using 130‐nm SiGe BiCMOS technology. The chips contain a 6‐bit phase shifter (PS), 1‐bit attenuator (ATT), 3‐bit variable gain amplifier (VGA), serial peripheral interface (SPI), Wilkinson combiner, power amplifier (PA), and low noise amplifier (LNA). The designed vector‐sum PS, employing a current DAC for semi‐digitization, achieves a 6‐bit phase resolution with minimal root‐mean‐square (RMS) phase error. This design choice allows for the high bit control of the current DAC within a compact chip area. Four‐bit amplitude control is obtained with VGA and ATT. The VGA provides 8‐dB amplitude range while ATT enlarges overall amplitude control with additional 8 dB. L‐R‐L phase compensation technique is utilized to reduce the phase error that arises from ATT. The sub‐blocks are designed to operate with low DC power such that the DC power consumption of overall RX and TX is 50 and 97 mW, respectively. The measurement results of a single‐channel indicate a gain of 15.5‐dB and −25‐dBm IP1dB for the RX chip and 26.5‐dB and 10‐dBm OP1dB for the TX chip while each chip occupies 0.83 mm2$$ {}^2 $$. The RX chip exhibits a measured noise figure (NF) of 4.3 dB at 26 GHz. Both Tx and Rx chips achieve 6‐bit phase control and 4‐bit amplitude control with low RMS phase error of 2.6° and gain error of 0.3 dB. Low RMS gain and phase errors over a wide bandwidth are attributed to the high precision DAC employed in the control of VGA and PS. Both chips are flip‐chip packaged and undergo upconversion/downconversion via external mixers on a printed circuit board (PCB). System‐level tests with 64‐quadrature amplitude modulation (QAM) show an error vector magnitude (EVM) of 2.72% at 27 GHz for RX and 5.02% at 24 GHz for TX, with a 50‐MBaud modulated signal applied at a data rate of 300 MBps. [ABSTRACT FROM AUTHOR]

In this paper, we propose an N -bit optical digital-to-analog converter (DAC) by integrating N pairs of 2 × 2 phase change based on-chip photonic switches and 2 × 2 multimode interference (MMI) splitters. An on-chip photonic switch is constructed by integrating a wavelength-selectable racetrack micro-ring resonator with the phase change chalcogenide Ge2Sb2Se4Te (GSST). The GSST-integrated switch utilizes a racetrack resonator configuration for performing the accurate modulation of the resonant wavelength to prevent intercoupling between adjacent units. In order for electrothermal heating of the GSST film to trigger its phase transition for switchable control, an indium tin oxide heater with a bowtie-shaped structure is integrated into the racetrack resonator. Using numerical calculations, we demonstrate that an 8 V voltage pulse at a duration of 300 ns, with an energy consumption of 18.45 nJ, could change the optical state from an OFF state to an ON state. Another 6 V voltage pulse of 250 ns duration, followed by a 4 V pulse of varying duration, with a total energy consumption of 34.78 nJ, can switch the optical state from an ON state to an OFF state. The asymmetric structure of the 2 × 2 MMI shows ultra-high transmittance approaching 50% in the through port (connected to the next order of MMI), enabling the creation of multistage cascaded MMI splitters with an output light power ratio close to 50%. Our results show that this configuration potentially offers a feasible solution for applications of optical DACs. [ABSTRACT FROM AUTHOR]

Field programmable gate arrays (FPGAs) have not only enhanced traditional sensing methods, such as pixel detection (CCD and CMOS), but also enabled the development of innovative approaches with significant potential for particle detection. This is particularly relevant in terahertz (THz) ray detection, where microbolometer-based focal plane arrays (FPAs) using microelectromechanical (MEMS) resonators are among the most promising solutions. Designing high-performance, high-pixel-density sensors is challenging without FPGAs, which are crucial for deterministic parallel processing, fast ADC/DAC control, and handling large data throughput. This paper presents a MEMS-resonator detector, fully managed via an FPGA, capable of controlling pixel excitation and tracking resonance-frequency shifts due to radiation using parallel digital lock-in amplifiers. The innovative FPGA architecture, based on a lock-in matrix, enhances the open-loop readout technique by a factor of 32. Measurements were performed on a frequency-multiplexed, 256-pixel sensor designed for imaging applications. [ABSTRACT FROM AUTHOR]

This paper presents a programmable digital filtering unit dedicated to operating with signals from infrared (IR) detection modules. The designed device is quite useful for increasing the signal-to-noise ratio due to the reduction in noise and interference from detector–amplifier circuits or external radiation sources. Moreover, the developed device is flexible due to the possibility of programming the desired filter types and their responses. In the circuit, an advanced field-programmable gate array FPGA chip was used to ensure an adequate number of resources that are necessary to implement an effective filtration process. The proposed circuity was assisted by a 32-bit microcontroller to perform controlling functions and could operate at frequency sampling of up to 40 MSa/s with 16-bit resolution. In addition, in our application, the sampling frequency decimation enabled obtaining relatively narrow passband characteristics also in the low frequency range. The filtered signal was available in real time at the digital-to-analog converter output. In the paper, we showed results of simulations and real measurements of filters implementation in the FPGA device. Moreover, we also presented a practical application of the proposed circuit in cooperation with an InAsSb mid-IR detector module, where its self-noise was effectively reduced. The presented device can be regarded as an attractive alternative to the lock-in technique, artificial intelligence algorithms, or wavelet transform in applications where their use is impossible or problematic. Comparing the presented device with the previous proposal, a higher signal-to-noise ratio improvement and wider bandwidth of operation were obtained. [ABSTRACT FROM AUTHOR]

This paper presents a highly efficient, low-power, compact mixed-signal sinusoidal current generator (CG) integrated circuit (IC) designed for bioelectrical impedance spectroscopy (BIS) with low total harmonic distortion (THD). The proposed system employs a 9-bit sine wave lookup table (LUT) which is simplified to a 4-bit data stream through a third-order digital delta–sigma modulator (ΔΣM). Unlike conventional analog low-pass filters (LPF), which statically limit bandwidth, the finite impulse response (FIR) filter attenuates high-frequency noise according to the operating frequency, allowing the frequency range of the sinusoidal signal to vary. Additionally, the output of the FIR filter is applied to a 6-bit capacitive digital-to-analog converter (CDAC) with data-weighted averaging (DWA), enabling dynamic capacitor matching and seamless interfacing. The sinusoidal CG IC, fabricated using a 65 nm CMOS process, produces a 5 μA amplitude and operates over a wide frequency range of 0.6 to 20 kHz. This highly synthesizable CG achieves a THD of 0.04%, consumes 19.2 μW of power, and occupies an area of 0.0798 mm2. These attributes make the CG IC highly suitable for compact, low-power bio-impedance applications. [ABSTRACT FROM AUTHOR]

Summary: A current‐mode (CM) bandgap voltage reference (BGR) with second‐order curvature compensation is presented in this paper. The proposed CM BGR offers a simple compensation structure that requires only six additional transistors compared with traditional BGR designs, making it an attractive solution for low temperature coefficient (TC) voltage references. Proportional to absolute temperature (PTAT) current digital‐to‐analog converters (DACs) are used to suppress the effect of process variation and device mismatch on TC. The compensation signal is generated using the voltage difference of two bipolar junction transistor (BJT) emitter–bases whose currents are the sum and difference of the PTAT current and the zero to absolute temperature (ZTAT) current, respectively. The proposed CM BGR is designed with 0.18‐μm BIPOLAR CMOS DMOS process. A TC is 2.41 ppm/°C over a wide temperature range of −40°C to 150°C. The linear sensitivity of the supply voltage from 1.2 to 2 V is 0.027%/V. With an active area of 0.0721 mm2, it consumes 68 μA at room temperature. The integrated output noise from 0.1 to 10 Hz is 21.9 μV. [ABSTRACT FROM AUTHOR]

With the increasing demand for accurate and robust positioning solutions, the use of GNSS antenna arrays has gained significant attention. However, their development and testing are frequently constrained by the inflexibility of traditional hardware platforms, often requiring extensive reconfiguration throughout the development cycle. This paper presents a platform based on a system on chip to develop a highly flexible software-controlled system that is capable of directly sampling up to 16 antenna elements. Multibeam digital beamforming is implemented using the available FPGA resources and the resulting signal is reproduced by the integrated DAC and can be connected to any conventional single antenna GNSS receiver. This paper presents the architecture of the platform, detailing its components and capabilities. Our experimental results demonstrate that the system can phase shift every channel with errors of less than 0.5° and can reconfigure 4 simultaneous beams of a 16-antenna array at speeds of 1.2 kHz, and 20 beams at around 400 Hz. The average delay introduced by each channel of the system is around 381 ns with a maximum deviation of 1.05 ns. The delay was also measured for the implementation using 4 beams, which achieves a slightly bigger average delay of 384.6 ns while keeping the variation to 5 to 6 ns. This system is intended to be used as the backbone for the development of antenna arrays and beamforming algorithms. Given its flexibility, it is not necessary to develop new hardware between development iterations or even for different systems, as only the software layer needs to be modified. Consequently, it is possible to expedite the development stage before producing dedicated solutions for industrial applications. [ABSTRACT FROM AUTHOR]

A method of expanding the operating range of the amplifier is presented, which allows reducing the coefficient of nonlinear distortions of the calibration signal to 0.003%. The structural diagram of the analog-digital amplifier of the input signal to the output, which provides minimal nonlinear distortion of the output signal, is given. The principle of operation of the amplifier is described. The input scaling amplifier and output highvolt digital-to-analog converter transmission coefficients dependens diagrams on the input signal amplitude are given. The results of experimental studies of the metrological characteristics of the experimental sample of the amplifier are given. References 10, figures 2. [ABSTRACT FROM AUTHOR]

The technique of sampling rate conversion is frequently employed in various fields. A discrete time-varying filter, as well as a sample skip or sample duplicate operation, are required for the most general instance of an irrational and time-variable conversion factor. A wide band of signals is employed in a communication system, especially in specific situations where data must be transferred directly. A broadband sample rate converter with changeable filter parameters is necessary in such cases. Sample rate conversion is a communication system technology that accepts a band-limited high sample rate modulated signal and uses filtering to retrieve the original message signal. In this work, an energy-efficient implementation of a reconfigurable field programmable gate arrays (FPGA) architecture for a sample rate converter is proposed. In applications such as multi-rate signal processing and the construction of channelized receivers, sample rate conversion is used. In this work, a new FPGA based design is proposed to perform multiple sample rate conversion for various data transmission protocols such as Wi-Fi, ZigBee and Bluetooth. A lowpass filter with a 2.45 GHz filter with the minimum number of taps is used to avoid the aliasing effect. Xilinx synthesis tools are used to estimate hardware resource utilization and speed analyses. XC6VCX240t-2FF484 FPGA achieves 15% hardware resource occupancy at a maximum clock speed of 133 MHz. [ABSTRACT FROM AUTHOR]

In this work, the system-level design of noise-shaping (NS) successive-approximation (SAR) analog-to-digital converters (ADCs) is investigated and analyzed. It is shown that despite the fact that the NS SAR architecture shares the same fundamental NS principle with the Σ Δ architecture, there are a few implementation differences that imply different considerations for optimum system-level design, particularly in the selection of the system oversampling ratio (OSR) and consequent resolution of the associated digital-to-analog converter (DAC) for a certain target overall resolution. In addition, the impacts of the OSR value on the power dissipation and figure-of-merit (FOM) are addressed in details. [ABSTRACT FROM AUTHOR]

The study aimed to develop a portable electronic nose system for detecting adulteration with soybean protein isolate (SPI) in chicken meat. The system mainly consisted of three parts: the gas sensor array, the DSP28335 control board, and the upper computer. The DSP28335 control board, developed using C language, included analog to digital converter (ADC) module, digital output (DO) module, pulse width modulation (PWM) module, controller area network (CAN) module, power module, drive circuit, and so forth. The upper computer, developed using LabVIEW, facilitated user interaction with the user by primarily handling CAN configuration and monitoring, displaying and storing sensor data, temperature and flow data, and sending and monitoring electronic nose commands. The feasibility of the proposed electronic nose for characterizing adulterated chicken meat was tested on six classes of chicken meat that had been adulterated with varied quantities of SPI. The mass fractions of SPI were 0%, 5%, 10%, 15%, 20%, and 25%, respectively. On the basis of odor data from the electronic nose, K‐nearest neighbor (KNN), linear discriminant analysis (LDA), and support vector machine (SVM) were applied to qualitatively distinguish minced chicken meat with different adulteration ratios. The results showed that the SVM model had the best recognition effect. When the best parameters (c, g) were c = 16 and g = 1, the accuracy of SVM model was 97.22% and 93.75% in the training and testing sets, respectively. These results demonstrated that the portable electronic nose designed in this paper effectively identifies minced chicken meat under various adulteration conditions, enabling rapid and nondestructive detection of chicken meat adulteration. [ABSTRACT FROM AUTHOR]

This paper presents a thorough robust Class-AB power amplifier design and its application in pressure-mode sensor-on-chip nonlinearity correction. Considering its use in piezoresistive sensing applications, a gain-boosting-aided folded cascode structure is utilized to increase the amplifier's gain by a large amount as well as enhancing the power rejection ability, and a push–pull structure with miller compensation, a floating gate technique, and an adaptive output driving limiting structures are adopted to achieve high-efficiency current driving capability, high stability, and electronic environmental compatibility. This amplifier is applied in a real sensor nonlinearity correction on-chip system. With the help of a self-designed 7-bit + sign DAC and a self-designed two-stage operational amplifier, this system is compatible with nonlinear correction at different signal conditioning output values. It can also drive resistive sensors as small as 300 ohms and as high as tens of thousands of ohms. The designed two-stage operational amplifier utilizes the TSMC 0.18 um process, resulting in a final circuit power consumption of 0.183 mW. The amplifier exhibits a gain greater than 140 dB, a phase margin of 68°, and a unit gain bandwidth exceeding 199.76 kHz. The output voltage range spans from 0 to 4.6 V. The final simulation results indicate that the nonlinear correction system designed in this paper can correct piezoresistive sensors with a nonlinearity of up to ±2.5% under various PVT (Process–Voltage–Temperature) conditions. After calibration by this system, the maximum error in the output voltage is 4 mV, effectively reducing the nonlinearity to 4% of its original value in the worst-case scenario. [ABSTRACT FROM AUTHOR]

This study proposes a cost‐effective, small‐size, and portable impedance analyzer using the AD5941 Analog Front End (AFE) that makes frequency sweep measurement for various applications. The design utilizes a microcontroller and an AD5941 circuit for impedance measurement. The AD541 is a high precision impedance converter system that consists of a 16‐bit, 1.6 MSPS, analog to digital converter (ADC), an integrated waveform generator, and a digital signal processing (DSP) block. The AD5941 has many advantages over the AD5933 which was used in numerous studies in the past decade. Also, the device implements the four‐wire impedance method which is an impedance measuring technique that reduces the effect of electrodes to achieve higher accuracy. A supporting Graphic User Interface (GUI) software is employed to control the Impedance Analyzer device and to visualize the measurement. This impedance analyzer achieves a frequency resolution of 0.015 Hz and can generate sinusoid up to 200 kHz. In frequency range from 10 kHz to 150 kHz, the device can measure impedance in the range of 10 Ω–100 kΩ with less than 4.3% of error in comparison with benchtop impedance analyzer, Microtest 6632. Moreover, our impedance measurement device has undergone testing involving human calf measurements and electrochemical quantification, particularly for estimating Sodium Chlorite. The experimental outcomes demonstrate that our design not only fulfills the criteria of an impedance analyzer device but also performs effectively across diverse applications. © 2024 Institute of Electrical Engineers of Japan and Wiley Periodicals LLC. [ABSTRACT FROM AUTHOR]

DC–DC buck converters have been designed by incorporating different control stages to drive the switches. Among the most commonly used controllers, the sliding mode control (SMC) and proportional-integral-derivative (PID) controller have shown advantages in accomplishing fast slew rate, reducing settling time and mitigating overshoot. The proposed work introduces the implementation of both SMC and PID controllers by using the field-programmable gate array (FPGA) device. The FPGA is chosen to exploit its main advantage for fast verification and prototyping of the controllers. In this manner, a DC–DC buck converter is emulated on an FPGA by applying an explicit multi-step numerical method. The SMC controller is synthesized into the FPGA by using a signum function, and the PID is synthesized by applying the difference quotient method to approximate the derivative action, and the second-order Adams–Bashforth method to approximate the integral action. The FPGA synthesis of the converter and controllers is performed by designing digital blocks using computer arithmetic of 32 and 64 bits, in fixed-point format. The experimental results are shown on an oscilloscope by using a digital-to-analog converter to observe the voltage regulation generated by the SMC and PID controllers on the DC–DC buck converter. [ABSTRACT FROM AUTHOR]

Contemporary society electronic technology has evolved into a pivotal component across various facets of our lives. Its indispensability is particularly evident in the advancement of medical, agricultural, industrial, and other sectors. As this technology continues to play a crucial role, optimizing its performance in terms of speed, accuracy, and energy consumption becomes paramount. This paper introduces a novel electrical design for the threshold inverter quantization comparator circuit aiming to meet the evolving demands of modern electronic applications. The proposed design enhances the classic threshold inverter quantization comparator's performance by significantly reducing its power consumption. Through rigorous mathematical analysis and simulation results it is demonstrated that the proposed comparator design achieves a remarkable 50% reduction in power consumption compared to the conventional threshold inverter quantization comparator. Subsequently the newly devised design is applied to the construction of a 4-bit flash analog-to-digital converter using 0.35 µm complementary metal-oxide-semiconductor (CMOS) technology. [ABSTRACT FROM AUTHOR]

This research paper presents a 12-bit 8–4-segmented current-steering DAC (digital-to-analog converter) that offers notable advantages, particularly in terms of its reduced power consumption compared to other similar designs. The exceptional performance of our DAC can be attributed to two key factors: the use of a thermometer encoder and an efficient digital input bit segmentation. These features contribute to enhanced precision and reduced power requirements, setting our DAC apart from the existing solutions in the field. These enhancements significantly reduce glitches and improve the accuracy of the DAC's output. DAC dissipates a total power of about 44.95 mW when running at a sample rate of 1.2 GHz with the CMOS technology of 45 nm. While the supply input voltage is held constant at 1.2 V, the DAC's digital input is pulsating in nature in which the ON voltage is 1 V and OFF voltage is 0 V. Also, the DAC has a spurious-free dynamic range (SFDR) of 41.77 dB. [ABSTRACT FROM AUTHOR]

In this research, we present a 16-bit multi-mode digital-to-analog converter (DAC) with a time-interleaved (TI) structure operating at a frequency of 4 GHz over a bandwidth (BW) of 20 MHz, which is in compliance with the fifth generation (5G) wireless communications. The proposed architecture uses only one clock frequency to generate radio frequency (RF) signals and includes a second-order (2nd-order) delta-sigma modulator (DSM) with a reconfigurable low-pass (LP) mode, band-pass (BP) mode at Fs/4, and high-pass (HP) mode for signal synthesis. To increase the sampling frequency (Fs) of the TI structure, four channels are proposed, each working at a frequency of Fs/4. Since there are simple coefficients for all modes, the multiplication operation can be performed using a shifter block. This leads to design simplification, lower power consumption, smaller occupied area, and higher speed. A major challenge in designing this type of structure is the duty-cycle-error (DCE), especially in interleaved mode. In this research, we propose a new solution that solves DCE-related problems without adding digital circuits to the output of the DSM, by adjusting the analog filter circuit. Simulation results in MATLAB show that the value of signal-to-noise and distortion ratio (SNDR) in LP is equal to 106.14 dB, in BP is equal to 107.84 dB, and in HP is equal to 105.34 dB. Compensating for filters increases the spurious-free dynamic range (SFDR) to more than 118 dB. [ABSTRACT FROM AUTHOR]

To identify whether the circuit under test is fault-free or faulty, fault diagnosis is conducted in an analog circuit. However, in the case of fault detection (FD) techniques, the size of FD is the main challenge in testing, especially for complex analog circuits. Hence to reduce the size of FD, specific test nodes are chosen to perform fault diagnosis from the available accessible test nodes. Specific test nodes are selected based on the faults classification efficiency of fault diagnosis. Therefore, this paper proposes an approach for single and multiple soft fault diagnosis using minimum test nodes in analog electronic circuits. The proposed double deep Q-learning-based hybrid Simulated annealing–Tabu search (DDQN-Hybrid SATS) technique determines minimum test nodes with the utilization of distance metric for fault classification. The DDQN-Hybrid SATS technique is used to identify minimum nodes for testing. In this, the double deep Q learning network (DDQN) ensures better reliability and faster convergence in learning but suffers from catastrophic forgetting issues. To prevent such issues, the DDQN approach is optimized using a hybrid SATS algorithm. The hybrid optimization of simulated annealing (SA) and Tabu search (TS) coalesce the advantages of individual optimization procedures to provide the optimum solution in a fast and effective way. The results for a fourth-order low pass filter are presented (i.e., first CUT) and an eight-bit digital to analog converter (i.e., second CUT). Moreover, the simulation experiment reveals that the proposed DDQN-Hybrid SATS technique achieves greater overall fault classification accuracy of about 96.25% than other compared techniques with minimum computation time. [ABSTRACT FROM AUTHOR]

This paper presents a comprehensive review of the state-of-art high-speed dynamic comparators. The comparator is a critical block of high-speed, low-power analog-to-digital converters, determining the speed and overall power consumption. Therefore, the design of a high-speed comparator with tolerable offset, noise and power consumption is of utmost importance. Recent work reported on high-speed comparator topologies is investigated in detail with the help of simulations in 65 nm CMOS technology. Various parameters, such as delay, energy consumption, speed, offset, kickback noise, power delay product, etc., are compared. A detailed comparative study is also presented on several design methodologies. [ABSTRACT FROM AUTHOR]

An automated device is designed to measure the density of a liquid material using hydrostatic pressure method. A low cost pressure sensor is calibrated and used to get highly accurate readings. The calibration is done by measuring the pressure values vs. the generated voltage signal. The calibration has been challenging due to the low accuracy of the sensor but proved to be highly effective in applications. The interface is developed using a microcontroller, motor drives, analog to digital converters and sensors. The device is designed to get several readings automatically by changing the positions of the device/liquid column heights to increase the accuracy. Also the device can be programmed to measure the real time density of a liquid continuously. The readings were analyzed and averaged by a software developed in python language. The instruments accuracy was tested against 3 liquid types, water, coconut oil, kerosene oil, and showed a low error (0.007%, 0.001%, and 0.002% respectively) compared to the readings of a standard Pycnometer. The low error percentages confirm the accuracy of the device and the effectiveness of the sensor calibrations. [ABSTRACT FROM AUTHOR]

Electron beam lithography (EBL) involves the transfer of a pattern onto the surface of a substrate by first scanning a thin layer of organic film (called resist) on the surface by a tightly focused and precisely controlled electron beam (exposure) and then selectively removing the exposed or nonexposed regions of the resist in a solvent (developing). It is widely used for fabrication of integrated circuits, mask manufacturing, photoelectric device processing, and other fields. The key to drawing circular patterns by EBL is the graphics production and control. In an EBL system, an embedded processor calculates and generates the trajectory coordinates for movement of the electron beam, and outputs the corresponding voltage signal through a digital-to-analog converter (DAC) to control a deflector that changes the position of the electron beam. Through this procedure, it is possible to guarantee the accuracy and real-time control of electron beam scanning deflection. Existing EBL systems mostly use the method of polygonal approximation to expose circles. A circle is divided into several polygons, and the smaller the segmentation, the higher is the precision of the splicing circle. However, owing to the need to generate and scan each polygon separately, an increase in the number of segments will lead to a decrease in the overall lithography speed. In this paper, based on Bresenham's circle algorithm and exploiting the capabilities of a field-programmable gate array and DAC, an improved real-time circle-producing algorithm is designed for EBL. The algorithm can directly generate circular graphics coordinates such as those for a single circle, solid circle, solid ring, or concentric ring, and is able to effectively realizes deflection and scanning of the electron beam for circular graphics lithography. Compared with the polygonal approximation method, the improved algorithm exhibits improved precision and speed. At the same time, the point generation strategy is optimized to solve the blank pixel and pseudo-pixel problems that arise with Bresenham's circle algorithm. A complete electron beam deflection system is established to carry out lithography experiments, the results of which show that the error between the exposure results and the preset patterns is at the nanometer level, indicating that the improved algorithm meets the requirements for real-time control and high precision of EBL. HIGHLIGHTS: • To improve the accuracy and speed of production of circular patterns in electron beam lithography, a method of directly exposing circular patterns by controlling the electron beam is proposed, in which the trajectory coordinates of the beam are generated in real time without image stitching. • Bresenham's circle algorithm encounters two problems in circle production: blank pixels will appear when solid circles are generated, and pseudo-pixels occur when a circle of a specific radius is generated. In this paper, Bresenham's algorithm is optimized and improved to solve these two problems, and the effectiveness of the improved algorithm is demonstrated by simulation and experiment. • Experimental results show that the proposed method can effectively control electron beam photolithography of single-line-wide circles, solid circles, solid rings, concentric circles, etc. The error between the lithography results and the preset parameters is at the nanometer level. [ABSTRACT FROM AUTHOR]

A system-level implementation of a parallel-path hybrid switched-capacitor amplifier is presented in this paper. The proposed parallel-path amplifier incorporates a gain and slew rate-boosting switching path in parallel with an embedded assisted SAR path, aiming for IoT applications. As an alternative concept to the conventional analog topologies, the proposed amplifier combines nonlinear and linear paths to provide coarse and fine amplifications. In the coarse amplification, a high current is provided through a switching path for a fraction of time, which improves the slew rate and open-loop DC gain without adding significant static current. Moreover, high accuracy is achieved through the embedded assisted SAR path, which provides a resolution of 1/2N. In addition, each extra bit of the embedded SAR path improves the total open-loop DC gain by 6 dB. The theory of operation is performed to study how the switching and assisted SAR paths can enhance the amplifier's settling error. In addition, an existence trade-off between the coarse amplification error and the capacitive digital-to-analog converter's number of bits is investigated. The theory and system-level simulation show that the gain and slewing restrictions of the conventional topologies, especially in advanced CMOS technology, can be handled much easier by this parallel combination, where the switching path and assisted SAR path combination provides a high slewing capability and high DC open-loop gain. [ABSTRACT FROM AUTHOR]

Tomato disease image recognition plays a crucial role in agricultural production. Today, whilemachine vision methods based on deep learning have achieved some success indiseaserecognition, theystill faceseveralchallenges. These include issues such as imbalanced datasets, unclear disease features, small inter-class differences, and large intra-class variations. To address these challenges, this paper proposes a method for classifying and recognizing tomato leaf diseases based on machine vision. First, to enhance the disease feature details in images, a piecewise linear transformation method is used for image enhancement, and oversampling is employed to expand the dataset, compensating for the imbalanced dataset. Next, this paper introduces a convolutional block with a dual attention mechanismcalled DAC Block, which is used to construct a lightweight model named LDAMNet. The DAC Block innovatively uses Hybrid Channel Attention (HCA) and Coordinate Attention (CSA) to process channel information and spatial information of input images respectively, enhancing the model's feature extraction capabilities. Additionally, this paper proposes a Robust Cross-Entropy (RCE) loss function that is robust tonoisylabels, aimedat reducing the impact of noisy labels on the LDAM Net model during training. Experimental results show that this method achieves an average recognition accuracy of 98.71% on the tomato disease dataset, effectively retaining disease information in images and capturing disease areas. Furthermore, the method also demonstrates strong recognition capabilities on rice crop disease datasets, indicating good generalization performance and the ability to function effectively in disease recognition across different crops. The research findings of this paper provide new ideas and methods for the field of crop disease recognition. However, future research needs to further optimize the model's structure and computational efficiency, and validate its application effects in more practical scenarios. [ABSTRACT FROM AUTHOR]

Schematic illustration of plantar pressure distribution visualization system including a 9-channel pressure sensor array, analog to digital converter, data analysis software, and operation interface. [Display omitted] Based on real-time detection of plantar pressure, gait recognition could provide important health information for rehabilitation administration, fatigue prevention, and sports training assessment. So far, such researches are extremely limited due to lacking of reliable, stable and comfortable plantar pressure sensors. Herein, a strategy for preparing high compression strength and resilience conductive iongels has been proposed by implanting physically entangled polymer chains with covalently cross-linked networks. The resulting iongels have excellent mechanical properties including nice compliance (young's modulus < 300 kPa), high compression strength (>10 MPa at a strain of 90 %), and good resilience (self-recovery within seconds). And capacitive pressure sensor composed by them possesses excellent sensitivity, good linear response even under very small stress (∼kPa), and long-term durability (cycles > 100,000) under high-stress conditions (133 kPa). Then, capacitive pressure sensor arrays have been prepared for high-precision detection of plantar pressure spatial distribution, which also exhibit excellent sensing performances and long-term stability. Further, an extremely sensitive and fast response plantar pressure monitoring system has been designed for monitoring plantar pressure of foot at different postures including upright, forward and backward. The system achieves real-time tracking and monitoring of changes of plantar pressure during different static and dynamic posture processes. And the characteristics of plantar pressure information can be digitally and photography displayed. Finally, we propose an intelligent framework for real-time detection of plantar pressure by combining electronic insoles with data analysis system, which presents excellent applications in sport trainings and safety precautions. [ABSTRACT FROM AUTHOR]

We consider the methods used for calibration of coordinate-time measuring instruments of current parameters of the global navigation satellite systems. For the calibration of coordinate-time measuring instruments in the process of their design and testing, it is customary to use simulators of signals of the global navigation satellite systems. However, these simulators should be also calibrated. At present, there exist various procedures of guaranteeing the metrological characteristics of simulators, including their calibration with the help of an oscilloscope. However, this method has not only advantages but also disadvantages connected with the application of oscilloscope. Note that the development of a new reference measuring device, namely, a calibrator of the simulator of signals of the global navigation satellite systems is now carried out at the VNIIFTRI. Since the operation of the calibrator is based on the same principles as the operation of the navigation receiver and the calibrator determines the time of propagation of the signal (group delay time) received from the calibrated simulator, it is extremely important to accurately evaluate the intrinsic group delay time of the calibrator introduced by the receiving path and to develop the procedure for the determination of this metrological characteristic. The applied circuit solutions used in the design of calibrators include digital blocks, e.g., digital-to-analog or analog-to-digital converters. The aim of the performed investigations is to estimate the group delay time in the input circuit of the calibrator containing an analog-to-digital converter. The traditional methods used for estimating the group delay time by using S‑parameters are not suitable for this purpose because they do not enable one to compare analog and digital signals. In the present work, we develop an indirect method for estimating the group delay time of a signal in the receiving path of the calibrator according to the step responses of the circuit. The method proposed by the authors determines the group delay time of the signal in the receiving path of the calibrator according to the step response of the circuit. The field of application of the proposed method is the verification and calibration of measuring devices, which use input and output signals with analog-to-digital conversion. By using this method, we estimated the group delay time of the signal in the calibrator circuit containing an analog-to-digital converter. We present the results of investigations of the indicated time characteristic by the proposed method for circuits containing various microwave devices (power splitters and circulators). The proposed method enables us to obtain exact estimates of the frequency characteristics of circuits of measuring devices and normalize their metrological characteristics. [ABSTRACT FROM AUTHOR]

The Lanzhou Heavy Ion Research Facility (LIRF) is the largest heavy ion research facility in China, providing a substantial volume of experimental data for fundamental research in nuclear physics. The Topmetal-CEE is a pixel readout chip specifically designed for tracking detectors. Within the Topmetal-CEE framework, the front-end amplifier and comparator necessitate precisely adjustable bias voltages. Hence, in this paper, a 14-bit resolution DAC with an R-2R resistor network structure is designed, along with an amplifier featuring high driving capabilities as the DAC driver, thus preventing potential impedance issues when driving large pixel arrays. Test results demonstrate that the DAC module, operating under a 3.3 V supply voltage, can consistently output voltages ranging from 0 to 1.8 V. Furthermore, the differential non-linearity error is less than 1.07 LSB, and the integral non-linearity error is less than 1.57 LSB. [ABSTRACT FROM AUTHOR]

This two-part work develops a comprehensive toolbox for the statistical characterization of nonlinear distortions of DAC-generated signal constellations to be transmitted over communication links, be they electronic (wireline, wireless) or photonic, Mach–Zehnder modulator (MZM)-based optical interconnects in particular. The all-analytic toolbox developed here delivers closed-form expressions for the second-order statistics (means, variances) of all relevant constellation metrics of the DACs' building blocks and of DAC-driven MZM-based optical transmitters, all the way to the slicer in the optical receivers over a linear channel with coherent detection. The key impairment targeted by the model is the random current mismatch of the ASIC devices implementing the DAC drivers. In particular the (skew-)centrosymmetry of the DAC metrics is formally derived and explored. A key applicative insight is that the conventional INL/DNL (Integral NonLinearity/Differential NonLinearity) constellation metrics, widely adopted in the electronic devices and circuits community, are not quite useful in the context of communication systems, since these metrics are ill-suited to predict communication link statistical performance. To rectify this deficiency of existing electronic DAC metrics, we introduce modified variants of the INL|DNL, namely the integral error vector (IEV) and the differential error vector (DEV) constellation metrics. The new IEV|DEV represent straightforward predictors of relevant communication-minded metrics: error vector magnitude (EVM) treated here in Part I, and Symbol/Bit Error-Rates (SER, BER) treated in the upcoming Part II of this paper. [ABSTRACT FROM AUTHOR]

Data converters are necessary for the conversion process of analog and digital signals. Successive approximation register (SAR) analog-to-digital converters (ADC) can achieve high levels of accuracy while consuming relatively low amounts of power and operating at relatively high speeds. This paper describes a design of 8-bit 125 kS/s SAR ADC with a proposed high-speed comparator design based on dynamic latch architecture. The proposed design of the comparator enhances the performance compared to a conventional dynamic comparator by adding two parallel clocked input complementary metal-oxide semiconductor (CMOS) transistors which reduce the parasitic resistance in the latch ground path and serve to minimize the latch delay time. The design of each sub-system for the ADC is explained thoroughly, which contains a sample and hold circuit, successive approximation register, charge redistribution types digital-to-analog converter, and the new proposed comparator. The proposed design is implemented using 180 nm CMOS technology with a power supply of 1.2 V. The average inaccuracy in differential non-linearity (DNL) is +0.6/-0.8 LSB (least significant bit), and integral non-linearity (INL) is +0.4/-0.7 LSB. The proposed design exhibits a delay time of 157 ps at 1 MHz clock frequency. [ABSTRACT FROM AUTHOR]

This work presents the detailed design of a Successive Approximation Analog to Digital Data Converter (SAR ADC) using bulk 180 nm CMOS IC technology. The focus of the study is on replacing the typical Successive Approximation Register array with a Finite State Machine. This converter features a fully differential and bipolar architecture, which leads to the logic SAR nonlinear behavior. A novel digital control logic mitigates the conversion errors through the conditions in the previous logic states. The logic scheme, in combination with a robust continuous comparator, demonstrates tolerance to Process, Voltage, and Temperature variations. The architecture does not include calibration or additional redundancies in post-layout simulations to emphasize the exclusive benefits of the new SAR logic. The proposed SAR ADC achieves a 14.07 effective number of bits with 7.04 fJ/conversion step Walden figure of merit in biomedical applications. [ABSTRACT FROM AUTHOR]

Summary A wide‐range direct digital frequency synthesizer (DDS) is considered an essential component that is used in measuring electrochemical impedance spectroscopy (EIS). Since it depends on exciting the electrochemical sensor by a pure sine wave, total harmonic distortion (THD) is considered a challenging specification for an accurate EIS measurement. This paper introduces a complete system and circuit designs of a wide range DDS with a comprehensive system model using MATLAB environment. In addition, it presents the usage of a reconfigurable digital‐to‐analog converter (DAC) on the circuit level that is used either as a 4‐bit delta‐sigma ( ΔΣ$$ \Delta \Sigma $$) DAC or an 8‐bit binary‐weighted DAC for both low‐ and high‐frequency ranges, respectively. The designed DDS generates an output frequency range from 762.933 Hz to 10 MHz using a physical 8‐bit DAC. The circuits are simulated using 0.18 μm CMOS technology. The designed DDS system achieves THD less than 0.05% with superior free dynamic range (SFDR) 66 dBc for low‐frequency range and 0.08% with SFDR 62 dBc for high‐frequency range. The DDS circuits occupy an area of 400  × 800 μm. The whole system consumes a 2.5 mW power consumption from a 1.8 V supply. [ABSTRACT FROM AUTHOR]

We consider the park of high-precision instruments for measuring alternating voltage playing the role of working standards of the first and second categories within the frequency range 0.1–30.0 MHz. It is indicated that thermoelectric voltage transducers developed more than 30 years ago are now used as working standards of the first category without alternative despite the fact that they exceeded their service life and do not meet contemporary operating requirements. As an alternative to the sets of thermoelectric converters within the frequency range 0.1–30.0 MHz, it is possible to use the calibrators of alternating voltage. However, in the indicated frequency range, there are no calibrators of alternating voltage that can be used as working standards of the first category. Thus, an N5-10 high-frequency calibrator of AC voltage whose characteristics exceed the requirements to the characteristics of working standards of the first category was developed for operation within the frequency range 0.1–30.0 MHz under voltages of 1·10−3–10V. We describe the concept of design, the characteristics, and operating capabilities of the H5-10 calibrator. In the design of the calibrator, we used the method of equating the amplitude of high-frequency voltage with the known amplitude of low-frequency sinusoidal voltage by the method of amplitude detection. The high-frequency sinusoidal voltage in the calibrator is formed by a frequency synthesizer with the help of the method of direct digital synthesis by using a system of band-pass filters. The accuracy and stability of the amplitude of high-frequency voltage at the output of the calibrator are maintained by an automatic regulation system based on the principle of mutually reciprocal transformations realized with the use of a two-diode integrated assembly of identical Schottky diodes. The low-frequency stable voltage for the base input of the automatic regulation system is formed by a low-frequency calibrator at a frequency of 10 kHz. This calibrator generates an AC voltage within the range 0.1–10.0 V with a harmonic coefficient smaller than 0.01% and an amplitude tuning discreteness of 0.001%. The low-frequency calibrator is constructed on multiplying digital-to-analog converters by the method of digital synthesis of sinusoidal voltage with a stable measure of constant voltage of 2.5 V. The nominal output voltages of the H5-10 calibrator within the range 0.1–10.0 V are reproduced by an automatic regulation system. At the same time, within the range 1–100 mV, they are reproduced by scaling with the use of a voltage divider. The main fields of usage of the developed H5-10 calibrator are the verification and calibration of electronic voltmeters, voltage calibrators, multimeters, and voltage transducers used as working standards of lower categories. [ABSTRACT FROM AUTHOR]

Accurate data acquisition is crucial in embedded systems. This study aimed to evaluate the data acquisition ability of the ESP32 Analog to Digital Converter (ADC) module when combined with the I2S module to collect high-frequency data. Sine waves at various frequencies and white noise were recorded in this mode. The recorded data were analyzed by the fast Fourier transform (FFT) to assess the accuracy of the recorded data and evaluate the generated noise. Digital filters are proposed to improve the quality of the collected signals. A 2D spectrogram imaging algorithm is proposed to convert the data to time-frequency domain images. The results showed that the ADC module could effectively collect signals at frequencies up to 96 kHz; frequency errors were proportional to the sampling rate, and the maximum was 79.6 Hz, equivalent to 0.38%. The execution time of the lowpass and highpass filters was about 6.83 ms and for the bandpass filter about 5.97 ms; the spectrogram imaging time was 40 ms; while the calculation time for an FFT transform was approximately 1.14 ms, which is appropriate for real-time running. These results are significant for data collection systems based on microcontrollers and are a premise for deploying TinML networks on embedded systems. [ABSTRACT FROM AUTHOR]

To enhance the sensitivity, signal-to-noise ratio and durance of electrospray mass spectrometer, an off-axis ion guide combining a traveling-wave (TW) stacked-ring and a shaped ion funnel has been designed, which is capable of filtering out the neutral contaminants and charged droplets entrained in the electrospray plume. According to its structural characteristics, the corresponding TW and radio frequency (RF) coupling power supply and measurement as well as control system were designed. Customizable Ethernet communication protocol was used to control the field-programmable logic gate array (FPGA) for full-circuit signal control and generation, and an 8-channel traveling-wave amplitude monitoring was achieved through a 12-bit analog-to-digital converter (ADC) and a 16-bit digital-to-analog converter (DAC). In addition, dual-plane transformer coupling circuit was designed. The use of traveling wave changed the central reference frame of the RF, achieving the purpose of programmed RF and the effect of TW in the stacked-ring to provide axial kinetic energy. The stability and accuracy of the electrical parameters of the hardware system on the off-axis transmission structure were tested. The results showed that the controllable voltage range of TW power supply is 0.1-100 V and the controlled DC power supply’s full range detection and control absolute error are less than 0.04 V. The frequency of TW up to 400 kHz, both rising edge and falling edge are less than 30 ns. Furthermore, the waveforms of TW, RF and post-coupling waveform are sufficiently smooth. The test results also showed that the performance of the power supply and measurement and control system are stable and reliable, and their accuracy and range can satisfy the design requirements. Then, the performance of off-axis structure was tested under rough vacuum using reserpine ions. It was found that the reference voltage difference between the upper and lower traveling-waves (the voltage which the ions were extracted), the voltage of the upper traveling-waves, and the traveling-wave duty cycle of the off-axis ion transmitter have more significant effects on the off-axis transmission of ions than other electrical parameters. The experimental results provide a fundamental understanding of ion transport and off-axis separation of traveling-wave stacked-ring structures, which is valuable for the development of high signal-to-noise mass spectrometry system. In the future, this novel traveling-wave off-axis transmitter and its coupling power supply system will be applied to homemade mass spectrometry instruments. Besides, we will compare the developed device with the mainstream ion transmission devices in the market so as to further improve the device structure and power supply parameters, and deeply explore the role of traveling-wave off-axis transmitter in different ionization sources and different detectors. [ABSTRACT FROM AUTHOR]

This paper presents an analog delay-locked loop (DLL) with a digital coarse lock and error compensation, designed to enhance locking speed in duty-cycled operation while ensuring reliability. To accelerate coarse locking speed and prevent coarse lock failure, the proposed DLL combines a low-resolution digital-to-analog converter (DAC) with an analog method for accurate lock range identification, efficiently handling scenarios where the DAC's limited resolution could lead to failure. Additionally, it enables the rapid control of voltage adjustments by disconnecting a loop filter during the coarse lock, eliminating the need for a buffer. The DLL improves the coarse lock process reliability by compensating for potential false lock errors caused by circuit non-idealities, such as residual RC delay and amplifier offset. Furthermore, it reuses the previously identified DAC input for the duty-cycled operation to significantly reduce relock time. To mitigate the risk of potential false lock resulting from changes in locking conditions, it can update the previous DAC input upon relocking, ensuring more reliable relocking. The proposed DLL, implemented in a 28 nm CMOS process, reduces initial lock and relock times by an average of 49.3% and 65.9% at a supply voltage of 0.5 V, and 42.4% and 70.2% at 1 V, respectively, compared to the conventional analog DLL. [ABSTRACT FROM AUTHOR]

Due to the nature of the public channel, designing authentication techniques suitable for wireless sensor networks (WSNs) that satisfy the dedicated considerations is critical. In 2022, Liu et al. presented an authentication protocol that employs dynamic authentication credentials (DACs) and Intel software guard extensions (SGX) to guarantee security in WSNs. Then, they proved that it is secure by formal and informal security analysis. This paper shows that it is not secure against desynchronization and offline guessing attacks for long-term random numbers of users. In addition, it suffers from the known session-specific temporary information attack. Then, an improved authentication scheme using DAC and Intel SGX will be presented to address these vulnerabilities. We show that it is secure against the aforementioned attacks by employing formal and informal analysis and has a reasonable communication and computation overhead. It should be highlighted that our proposal’s communication and computation overheads are increased negligibly, but it provides more security features compared to the baseline protocol. [ABSTRACT FROM AUTHOR]

Each application of neurostimulators requires unique stimulation parameter specifications to achieve effective stimulation. Balancing the current magnitude with stimulation resolution, waveform, size, and channel count is challenging, leading to a loss of generalizability across broad neural interfaces. To address this, this paper proposes a highly scalable, programmable neurostimulator with a System-on-Chip (SOC) capable of 32 channels of independent stimulation. The compliance voltage reaches up to ±22.5 V. A pair of 8-bit current-mode DACs support independent waveforms for source and sink operations and feature a user-selectable dual range for low-current intraparenchymal microstimulation with a resolution of 4.31 μ A/bit, as well as high current stimulation for spinal cord and DBS applications with a resolution of 48.00 μ A/bit, achieving a wide stimulation range of 12.24 mA while maintaining high-resolution biological stimulation. A dedicated communication protocol enables full programmable control of stimulation waveforms, effectively improving the range of stimulation parameters. In vivo electrophysiological experiments successfully validate the functionality of the proposed stimulator. This flexible stimulator architecture aims to enhance its generality across a wide range of neural interfaces and will provide more diverse and refined stimulation strategies. [ABSTRACT FROM AUTHOR]

Photonic integrated circuits (PIC) devices are impacted by fabrication tolerances and therefore, prior knowledge of such variations could improve the PIC fabrication process and overall yield. This paper presents a method for predicting the fabrication impacts on a telecommunication optical digital to analog converter (oDAC)-based pulse amplitude modulator level four (PAM-4) transmitter as a case study where the certainty of this passive device is subjected to random variation. Our findings allow us to estimate the production yield in a fabrication scenario using the symbol error rate (SER) benchmark and this contributes to the study of the viability of oDAC PAM-4 transmitters to replace conventional electrical digital to analog converter (eDAC) PAM-4 transmitters. [ABSTRACT FROM AUTHOR]

The article discusses the research conducted on high precision borehole temperature measurement technology at the China Seismic Experimental Site. The study involved the integration of various sensors and equipment to measure temperature with a resolution better than 30 μK/ Hz1/ 2 at 300 m underground. The research findings can be utilized for seismic scientific investigations post-earthquakes, showcasing the potential applications of the measuring system. [Extracted from the article]