A Low-Power 10-Bit 2GS/s Hybrid Time-Interleaved Digital-to-Analog Converter with a New Neutrolized-Glitch Unit Current Cell in 65 nm CMOS Technology.

This work presents a novel 10-bit 2GS/s time-interleaved digital-to-analog converter (TI-DAC). The presented TI-DAC benefits from a combination of two 1 GHz hybrid sub-DACs and bootstrapped switches to multiplex the output voltage of each sub-DAC. In the presented TI-DAC, the dynamic non-idealities of each sub-DAC do not propagate to the main DAC output, making the design of each sub-DAC simpler. Also, using hybrid sub-DACs lead to a considerable reduction in the occupied area and power consumption. Besides, a new glitch neutralizer in the unit current cells is proposed to improve the DAC linearity. The design and post-layout simulations of this TI-DAC are carried out using Cadence Virtuoso tools in 65 nm CMOS technology. The achieved integral non-linearity and differential non-linearity parameters are better than 0.8 least significant bit (LSB) and 0.2 LSB, respectively. The proposed TI-DAC consumes 18.2 mW from a supply voltage of 1.2 V. Additionally, the spurious-free dynamic range of above 59 dB across the entire Nyquist band for the designed 2GS/s TI-DAC is achieved, considering only 0.034 mm2 of area occupation. [ABSTRACT FROM AUTHOR]