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Quantum Dot Cellular Automata (QCA) and reversible logic have emerged as promising alternatives to conventional CMOS technology, offering several advantages, such as ultra-dense structures and ultra-low-power consumption. Among the crucial components of processors, the Arithmetic Logic Unit (ALU) has witnessed significant advancements in reversible computing, leading to energy-efficient and high-speed computing systems, particularly beneficial for Digital Signal Processing (DSP) applications. Conventional ALUs, reliant on irreversible logic, encounter energy inefficiencies due to information loss during computations, resulting in increased power consumption. Moreover, they may face limitations in processing speed, impacting real-time processing capabilities, especially for complex DSP tasks involving intensive arithmetic and logic operations. In response to these challenges, a research paper presents a pioneering approach, proposing a novel reversible ALU design using QCA nanotechnology. The proposed design ingeniously incorporates Modified Fredkin (MF) gates, and a coplanar reversible full adder based on the HNG gate, skillfully leveraging the unique features of QCA nanotechnology to optimize the ALU's energy-efficient and high-speed performance for DSP applications. This revolutionary QCA reversible ALU comprises 330 QCA cells arranged in a compact 0.41 μm2 area, skillfully realized through the coplanar clock-zone-based crossover approach. Its core computational elements, the three MF gates, and the innovative coplanar reversible full adder empower the ALU to execute a remarkable array of 20 distinct arithmetic and logic operations, showcasing its versatility in handling diverse DSP tasks. The proposed structure undergoes extensive simulations utilizing QCADesigner version 2.0.3 to confirm its performance. The evaluation results manifest substantial improvements compared to previous designs, boasting a 30% reduction in area occupancy, a 20% decrement in cell count, a 10% reduction in latency, and a 10% decrease in quantum cost compared to the best-known previous structure. These compelling outcomes solidify the potential of the proposed reversible ALU as a transformative advancement in energy-efficient and high-speed computing for DSP applications. [ABSTRACT FROM AUTHOR]

This study focuses on the analytical identification and quantification of one type of spurious responses in the context of response history analysis. The spurious response is caused by linear interpolation of input loads. Through analytical derivations and numerical simulations, it is shown that the identified spurious response is fully caused by the interpolation and can significantly affect both damping and inertial forces. Furthermore, the spurious response is not bounded, thus, resistance-based designs could potentially be non-conservative. The findings are applicable to (non-)linear MDOF systems. To address this issue and improve the quality of numerical results, remedies and recommendations are proposed. [ABSTRACT FROM AUTHOR]

In order to improve the measurement accuracy of near-bit apparent resistivity and its measurement range, this paper excites the underground transmitting antenna by a sinusoidal pulse-width modulated (SPWM) current excitation method, which can improve the response of the receiving antenna and circuit in the resistivity measurement system under the usual square wave excitation, thus improving the measurement accuracy of near-bit apparent resistivity. In this paper, the effect of square wave, SPWM wave and sine wave excitation on resistivity measurement was studied, and the modulation algorithm and hardware control are programmed by DSP (Digital Signal Processor), and the SPWM signal is output by full-bridge inverter circuit and tuned antenna. The indoor experimental results show that the near-bit apparent resistivity measurement method based on the SPWM wave pulse excitation can achieve the measurement in the range of formation equivalent resistor value of less than 600kΩ. There is a high trend matching between near-bit apparent resistivity LWD curve and RT resistivity curve of well completion electrical logging in field tests of formation resistivity less than 2000Ω·m, which proves that the method can improve the accuracy of near-bit apparent resistivity measurement. [ABSTRACT FROM AUTHOR]

Introduction: Multi-channel electrophysiology systems for recording of neuronal activity face significant data throughput limitations, hampering real-time, data-informed experiments. These limitations impact both experimental neurobiology research and next-generation neuroprosthetics. Methods: We present a novel solution that leverages the high integration density of 22nm fully-depleted silicon-on-insulator technology to address these challenges. The proposed highly integrated programmable System-on-Chip (SoC) comprises 68-channel 0.41 μW/Ch recording frontends, spike detectors, 16-channel 0.87–4.39 μW/Ch action potentials and 8-channel 0.32 μW/Ch local field potential codecs, as well as a multiply-accumulate-assisted power-efficient processor operating at 25 MHz (5.19 μW/MHz). The system supports on-chip training processes for compression, training, and inference for neural spike sorting. The spike sorting achieves an average accuracy of 91.48 or 94.12% depending on the utilized features. The proposed programmable SoC is optimized for reduced area (9 mm2) and power. On-chip processing and compression capabilities free up the data bottlenecks in data transmission (up to 91% space saving ratio), and moreover enable a fully autonomous yet flexible processor-driven operation. Discussion: Combined, these design considerations overcome data-bottlenecks by allowing on-chip feature extraction and subsequent compression. [ABSTRACT FROM AUTHOR]

The rapid growth of online services and the global transition to digital platforms, accelerated by the COVID-19 pandemic and the emergence of AI-based services, have led to a surge in demand for high-capacity optical communication networks (OCNs). However, this transition exacerbates the issue of fiber nonlinearity, notably four-wave mixing (FWM), which can significantly impact signal integrity in long-distance OCN transmissions with multiple channels. To address this challenge, this paper presents a novel approach leveraging a convolutional neural network (CNN)-based digital signal processing (DSP) model to mitigate the nonlinear effects of FWM on signal quality. The proposed CNN model, designed with three convolutional layers and trained on a comprehensive dataset of simulated OCN transmissions, demonstrates significant improvement in reducing nonlinear distortions caused by FWM. Our method is compared with traditional compensation techniques, such as digital back-propagation and Volterra series-based equalizers, showing a reduction in power penalties by 1 dB and an enhancement in the power budget by 2 dB. Simulation results indicate that the bit error rates (BERs) remain consistently below the critical threshold of 10−9 across various transmission distances, outperforming conventional methods. The simulation analysis, conducted on a 100 km multi-channel OCN testbed, confirms the CNN equalizer's efficacy in reducing crosstalk and improving power efficiency, with a demonstrated 15% reduction in required launch power. Moreover, the analytical models used to evaluate the CNN-based DSP model show high accuracy in predicting performance, underscoring the model's capability to achieve high-quality transmission with lower power requirements. These findings advocate for the integration of our CNN-based DSP model into OCNs, offering a fruitful solution for managing multi-channel, long-distance, and high-data-rate optical transmissions in real-world systems. [ABSTRACT FROM AUTHOR]

The residue number system is widely used in cryptography, digital signal processing, image processing systems, and other areas where high-performance computing is required. One of the main tools used in the residue number system is the Akushsky core function. However, its use is limited due to the existence of so-called critical cores. This study aims to develop Akushsky core functions that effectively eliminate the occurrence of critical cores, thereby enhancing their applicability in real-world scenarios. We introduce a fundamental approach to critical core detection that reduces the average time for critical core detection by 99.48% compared to the brute force algorithm. The results of our analysis indicate not only a substantial improvement in the speed of core detection but also an enhancement in the overall performance of systems utilizing the Akushsky core function. Our findings provide important insights into optimizing residue number systems and encourage further exploration into advanced computational techniques within this domain. [ABSTRACT FROM AUTHOR]

Fast algorithms for type-five discrete cosine transform (DCT-V) for sequences of input data of short length in the range of two to eight are elaborated in the paper. A matrix–vector product representation of the DCT-V is the starting point for designing the algorithms. In each specific case, the DCT-V matrices have remarkable structural properties that follow from the localization of identical entries within the matrices. Each matrix of the DCT-V has only a few distinct entries that are repeated at different positions in its structure. Using simple transformations such as permutations of the rows and/or columns of this matrix or its favorable decomposition into two or more matrix components, it is possible to obtain efficient matrix structures that lead to useful factorization schemes. Based on the suitable factorization schemes we obtained, we developed fast algorithms that reduce the number of arithmetic operations when calculating the DCT-V. The correctness of the obtained algorithmic solutions was justified theoretically using a strict mathematical background of each of them. The developed algorithms were then further tested using MATLAB R2023b software to finally confirm their correctness. Finally, an evaluation of the computational complexity for each obtained solution is presented. The evaluation results were compared with the computational complexity of the direct calculation of matrix–vector products. The resulting factorizations of the matrices of the DCT-V reduce the average number of multiplications by 57% but increase the number of additions by 29%. [ABSTRACT FROM AUTHOR]

A Field Programmable Gate Array (FPGA) is a semiconductor device based around a Configurable Logic Blocks (CLB) matrix connected by programmable interconnects. FPGA has numerous applications in biomedical signal processing due to its flexible programming and low power consumption. An Electrocardiogram (ECG) is a medical test used to determine heart rates, cardiac activity, and classify arrhythmias. All pass filters have Low Pass Filter (LPF), High Pass Filter (HPF), Band Stop Filter (BSF), and Band Pass Filter (BPF) to produce the exact amplitude in peak detection. However, the separate coefficient for individual filters increases the area in traditional all-pass filters. To overcome this issue, a Reconfigurable All-Pass Filter (RAPF) which considers a single coefficient for all filters and minimizes memory usage, consuming less area and power is employed. The LPF coefficient is utilized to perform the LPF operation, and then the two's complement of this LPF coefficient is computed to produce the HPF coefficient. Next, the two's complement is fed into the Hilbert Transform (HT) to produce the BSF coefficient and determine BSF operations. A RAPF is designed to perform these operations effectively. The RAPF performance is determined using Register, Look Up Table (LUT), Global Buffer (BUFG), Digital Signal Processing (DSP), Power, and Flip Flop (FF). RAPF consumes lesser power of 34 mW for Artix 7 XC7A200TFBG676-2 FPGA device, as opposed to the existing technique, Single Node Reservoir Computing (SNRC) using cumulative mean filter. [ABSTRACT FROM AUTHOR]

Nonlinear signal distortions are one of the main reasons limiting the throughput and length of modern fiber-optic communication lines. One of the developed approaches to nonlinear distortion compensation is based on the application of perturbation theory methods to the nonlinear Schrödinger equation, and allows one to obtain a relationship between transmitted and received symbols. Gradient methods that minimize the standard deviation between symbols are usually used to find the perturbation coefficients. However, the main parameter characterizing the data transmission quality is the bit error rate. We propose a modification of this approach in the form of a two-stage scheme for calculating the perturbation coefficients. At the first stage, the coefficients are calculated using the least squares method by minimizing the standard deviation, and at the second stage, the obtained solution is used as an initial approximation to minimize the error coefficient using the particle swarm method. In a numerical experiment, using the algorithm for compensating for received signal distortions based on the proposed scheme, a 0.9 dB gain in the signal-to-noise ratio is obtained for a multi-span line 20 × 100 km long and a 16QAM signal with a channel rate of 267 Gbit/s. An improvement in the accuracy of the algorithm (compared to a single-stage scheme) is shown, estimates of the computational complexity of the algorithm are obtained, and the relationship between its complexity and accuracy is presented. [ABSTRACT FROM AUTHOR]

In recent years, the automotive industry has made significant progress in integrating multifunctional sensors to improve vehicle performance, safety, and efficiency. As the number of integrated sensors keeps increasing, there is a growing interest in alternative energy sources. Specifically, self‐powered sensor systems based on energy harvesting are drawing much attention, with a main focus on sustainability and reducing reliance on typical batteries. This paper demonstrates the use of triboelectric nanogenerators (TENGs) in a computer mouse for efficient energy harvesting and in automobile braking systems for safety applications using SrBi2Ta2O9 (SBTO) perovskite, blended PDMS composite operating in free‐standing mode with an interdigitated patterned aluminum electrode. This self‐powered sensor is capable of distinguishing between normal and abnormal braking patterns using digital signal processing techniques. It is noteworthy that the addition of 15% wt. of the SBTO in PDMS composite‐based TENG delivered 13.5 V, 45 nA, and an output power of 0.98 µW. This new combination of energy harvesting and safety applications enables real‐time monitoring and predictive maintenance in the automotive industry. [ABSTRACT FROM AUTHOR]

In an ever expanding railway network all around the world, the need for track maintenance grows steadily. Traditionally, one major part of track maintenance is ramming large vibrating steel picks into the gravel between and under railway sleepers to compress the gravel and generate a safe substructure. Even today, maintenance personnel still have to manually locate the sleepers if they cannot be detected by computer vision systems or visually by the operator. Here we developed a first of its kind magnetic sleeper detector, even able to find sleepers, buried in gravel, undetectable by vision based systems. Our approach of magnetic detection is based on a DC magnetic field excitation and a detector moving with respect to the rail system, including the sleepers and fasteners for mounting the rails. Due to railway application constraints a large air gap between the sensor and the sleeper structure is required, which significantly complicates the magnetic sensing task for robust sleeper detection. The design and optimization of the magnetic circuit was based on extensive 3D simulation studies to ensure highest possible variation in magnetic flux density at the sensor locations for absence and presence of a sleeper. Furthermore, a low noise and high sensitivity electronic circuit has been realized to cope with sensor signal offsets from unknown or changing sensor orientations with respect to the earth's magnetic field, or magnetic interferences from other trains potentially passing by during active measurements. Since we only want to detect sleepers in close vicinity of the moving sensor system, digital signal processing of the acquired signals can easily compensate for disturbing slowly changing or static field components within real world application scenarios. We demonstrate that magnetic detection of even buried sleepers on railway tracks is possible for distances of up to 172 mm between the sensor and the sleeper. This enables an even higher level of railway maintenance automation previously impossible in certain scenarios. [ABSTRACT FROM AUTHOR]

Sparse Ramanujan Sequences (SRS) are periodic series derived from Ramanujan Sums (RS). RS is an exponential summation used to derive infinite series expansions for arithmetic functions, whose application pervades different fields of study from classical mathematics to digital signal processing. SRS has properties similar to RS such as periodicity and orthogonality. SRS transforms allow the sparse representation of signals, hence they have many potential applications, such as denoising and compression. The application of SRS transform to reduce the Peak to Average Power Ratio (PAPR) in Orthogonal Frequency Division Multiplexing (OFDM) is proposed in this paper. The Complementary Cumulative Distribution Function (CCDF) and Bit Error Rate (BER) are used to assess the PAPR reduction performance of the proposed system. The results show that the proposed SRS transform-based OFDM system significantly reduces PAPR and BER with reduced computational complexity in comparison with the existing systems. [ABSTRACT FROM AUTHOR]

FinFET technology is an alternative to CMOS technology as in this technology device has higher drive current, speed, and low-power consumption. FinFET has better mobility and scaling than CMOS technology. A dedicated Squaring circuit is needed by many digital signal processors (DSP) and arithmetic and logical units (ALU). So fast, power-efficient, and compact squaring circuits can be designed with Vedic sutras. Vedic mathematics has 16 sutras and 13 sub-sutras that touch almost all different chapters of mathematics. Out of these sutras, Dwandwayoga has a duplex property that is used to find a square of an N-bit number. Also, Yavadunam is a special case for finding the square of a number that is closer to the base. This work targets a comparative analysis of these two square circuits having a Vedic approach with a conventional array multiplier. The proposed designs are implemented in micro-wind 3.9 electronic design automation tool (EDA) with 14 nm deep submicron technology post-layout. The values of model parameters are used from the current Berkeley 4 short channel model (BSIM4). It is observed that the proposed square architecture design using the Dwandwayog sutra and Yavadunam sutra achieves 185%, 272.45% delay depletion and a 122.22%, and 46.52% reduction in transistor requirements compared to the conventional array multiplier, respectively. [ABSTRACT FROM AUTHOR]

This work aims to design a simple and powerful optimal observer for electric vehicles (EV) propelled by permanent magnet synchronous motor (PMSM) using synergetic theory. The development of suggested synergetic observer (SynO) based on the selected two manifolds of the back-EMF method which are the special merit of SynO is insensible of parametric and nonparametric deviations. The system is modeled by using small signal method with 99.35% accuracy. Moreover, to optimize the coefficients of observers, the bat algorithm optimization is executed in this work. The proposed SynO are compared with SMO by experimental tests on 0.4 kW, 3-phase PMSM using a TI F28335 digital signal processor board considering various dynamic operating conditions. The experimental results reveal that the performance of optimal SynO for accurate speed estimation of EV are better than the SMO, as well as good robustness against measurement noise, and reduced the chattering phenomena. [ABSTRACT FROM AUTHOR]

Compared to quaternions, reduced biquaternions satisfy the multiplication commutative rule and are widely employed in applications such as image processing, fuzzy recognition, image compression, and digital signal processing. However, there is little information available regarding reduced biquaternion tensors; thus, in this study, we investigate some properties of reduced biquaternion tensors. Firstly, we introduce the concept of reduced biquaternion tensors, propose the real and complex representations of reduced biquaternion tensors, and prove several fundamental theorems. Subsequently, we provide the definitions for the eigenvalues and eigentensors of reduced biquaternion tensors and present the Ger s ˇ gorin theorem as it applies to their eigenvalues. Additionally, we establish the relationship between the reduced biquaternion tensor and its complex representation. Notably, the complex representation is a symmetry tensor, which significantly simplifies the process and complexity of solving for eigenvalues. Corresponding numerical examples are also provided in the paper. Furthermore, some special properties of eigenvalues of reduced biquaternion tensors are presented. [ABSTRACT FROM AUTHOR]

A coherent optical receiver digital signal processing (DSP) scheme is proposed based on spectral clustering, which utilises spectral clustering to cluster the signals outputted by the DSP. Compared to existing blind DSP algorithms for coherent optical receivers operating at over 100Gbps with PM‐mQAM, the proposed scheme effectively suppresses various physical impairments, achieving lower bit error rates (BERs) at the same transmission distance, thus enabling longer transmission distances under the same forward error correction threshold. Furthermore, simulations of the proposed scheme on a 14GBaud PM‐16QAM coherent optical transmission system show that, at a BER of 1.9E‐2, the maximum transmission distance increases from 1700 to 2000 km, and at a BER of 3.8E‐3, it increases from 700 to 900 km. [ABSTRACT FROM AUTHOR]

Time series data often display complex, time-varying patterns, which pose significant challenges for effective classification due to data variability, noise, and imbalance. Traditional time series classification techniques frequently fall short in addressing these issues, leading to reduced generalization performance. Therefore, there is a need for innovative methodologies to enhance data diversity and quality. In this paper, we introduce a method for the extraction of features for time series classification using noise injection to address these challenges. By employing noise injection techniques for data augmentation, we enhance the diversity of the training data. Utilizing digital signal processing (DSP), we extract key frequency features from time series data through sampling, quantization, and Fourier transformation. This process enhances the quality of the training data, thereby maximizing the model's generalization performance. We demonstrate the superiority of our proposed method by comparing it with existing time series classification models. Additionally, we validate the effectiveness of our approach through various experimental results, confirming that data augmentation and DSP techniques are potent tools in time series data classification. Ultimately, this research presents a robust methodology for time series data analysis and classification, with potential applications across a broad spectrum of data analysis problems. [ABSTRACT FROM AUTHOR]

Healthcare researchers are increasingly utilizing smartphone sensor data as a scalable and cost-effective approach to studying individualized health-related behaviors in real-world settings. However, to develop reliable and robust digital behavioral signatures that may help in the early prediction of the individualized disease trajectory and future prognosis, there is a critical need to quantify the potential variability that may be present in the underlying sensor data due to variations in the smartphone hardware and software used by large population. Using sensor data collected in real-world settings from 3000 participants' smartphones for up to 84 days, we compared differences in the completeness, correctness, and consistency of the three most common smartphone sensors—the accelerometer, gyroscope, and GPS— within and across Android and iOS devices. Our findings show considerable variation in sensor data quality within and across Android and iOS devices. Sensor data from iOS devices showed significantly lower levels of anomalous point density (APD) compared to Android across all sensors (p  <  1 × 10−4). iOS devices showed a considerably lower missing data ratio (MDR) for the accelerometer compared to the GPS data (p  <  1 × 10−4). Notably, the quality features derived from raw sensor data across devices alone could predict the device type (Android vs. iOS) with an up to 0.98 accuracy 95% CI [0.977, 0.982]. Such significant differences in sensor data quantity and quality gathered from iOS and Android platforms could lead to considerable variation in health-related inference derived from heterogenous consumer-owned smartphones. Our research highlights the importance of assessing, measuring, and adjusting for such critical differences in smartphone sensor-based assessments. Understanding the factors contributing to the variation in sensor data based on daily device usage will help develop reliable, standardized, inclusive, and practically applicable digital behavioral patterns that may be linked to health outcomes in real-world settings. [ABSTRACT FROM AUTHOR]

The work is devoted to the consideration of methods for determining the strain of objects using fiber Bragg gratings under a high-frequency vibration or pulsed mechanical action, which is difficult to perform using widespread methods and devices. The methods are based on numerical processing of the time dependence of the radiation power reflected from the fiber Bragg grating at various wavelengths, which makes it possible to measure strain parameters in a wide range of magnitude and frequencies. The efficiency of the proposed methods is demonstrated by numerical simulation. It is shown that it is possible to restore the strain dependence on time in the range ± 1000   μ ϵ or more from simultaneously measured power dependencies reflected by the fiber Bragg grating using common fiber-optic components. The case of sequential registration of reflected radiation power at different wavelengths to determine the probability density of the distribution of the strain values is also considered. The results of signal processing obtained both by numerical simulation and experimentally for the case of a linear vibration are presented. The technical problems of using the proposed methods are discussed. [ABSTRACT FROM AUTHOR]

This study proposes a cost‐effective, small‐size, and portable impedance analyzer using the AD5941 Analog Front End (AFE) that makes frequency sweep measurement for various applications. The design utilizes a microcontroller and an AD5941 circuit for impedance measurement. The AD541 is a high precision impedance converter system that consists of a 16‐bit, 1.6 MSPS, analog to digital converter (ADC), an integrated waveform generator, and a digital signal processing (DSP) block. The AD5941 has many advantages over the AD5933 which was used in numerous studies in the past decade. Also, the device implements the four‐wire impedance method which is an impedance measuring technique that reduces the effect of electrodes to achieve higher accuracy. A supporting Graphic User Interface (GUI) software is employed to control the Impedance Analyzer device and to visualize the measurement. This impedance analyzer achieves a frequency resolution of 0.015 Hz and can generate sinusoid up to 200 kHz. In frequency range from 10 kHz to 150 kHz, the device can measure impedance in the range of 10 Ω–100 kΩ with less than 4.3% of error in comparison with benchtop impedance analyzer, Microtest 6632. Moreover, our impedance measurement device has undergone testing involving human calf measurements and electrochemical quantification, particularly for estimating Sodium Chlorite. The experimental outcomes demonstrate that our design not only fulfills the criteria of an impedance analyzer device but also performs effectively across diverse applications. © 2024 Institute of Electrical Engineers of Japan and Wiley Periodicals LLC. [ABSTRACT FROM AUTHOR]

Multi-level inverters have characteristics suitable for high-voltage and high-power applications through various topology configurations. These reduce harmonic distortion and improve the quality of the output waveform by generating a multi-level output voltage waveform. In particular, an active neutral-point-clamped topology is one of the multi-level inverters advantageous for high-power and medium-voltage applications. It has the advantage of controlling the output waveform more precisely by actively clamping the neutral point using an active switch and diode. However, it has a problem, which is that an unwanted zero-crossing current may occur if an inaccurate switching signal is applied at the time when the polarity of the output voltage changes. In this paper, a control strategy to suppress the zero-crossing current of a single-phase half-bridge three-level active neutral-point-clamped inverter is proposed. The operating principle of a single-phase half-bridge three-level active neutral-point-clamped inverter is identified through an operation mode analysis. In addition, how the switching signal is reflected in an actual digital signal processor is analyzed to determine the situation in which the zero-crossing current occurs. Through this, a control strategy capable of suppressing zero-crossing current is designed. The proposed method prevents a zero-crossing current by appropriately modifying the update timing of reference voltages at the point where the polarity of the output changes. The validity of the proposed method is verified through simulation and experiments. Based on the proposed method, the total harmonic distortion of the output current is significantly reduced from 12.15% to 4.59% in a full-load situation. [ABSTRACT FROM AUTHOR]

In this paper, we skillfully utilize the discriminative ability of the discriminator to construct a conditional generative adversarial network, and propose a scheme that uses few symbols to achieve high accuracy recognition of modulation formats under low signal-to-noise ratio conditions in coherent optical communication. In the one thousand kilometres G.654E optical fiber transmission system, transmission experiments are conducted on the PDM-QPSK/-8PSK/-16QAM/-32QAM/-64QAM modulation format at 8G/16G/32G baud rates, and the signal-to-noise ratio parameters are traversed under experimental conditions. As a key technology in the next-generation elastic optical networks, the modulation format recognition scheme proposed in this paper achieves 100% recognition of the above five modulation formats without distinguishing signal transmission rates. The optical signal-to-noise ratio thresholds required to achieve 100% recognition accuracy are 12.4 dB, 14.3 dB, 15.4 dB, 16.2 dB, and 17.3 dB, respectively. [ABSTRACT FROM AUTHOR]

Security postulates of visible light communication (VLC) is a paramount area of consideration due to its deployment in military, businesses, and residential establishments. Optical code division multiplexing (OCDMA) is prominent multiples access technique to serve multiple users and offer better security as compared to other available techniques such as wavelength and time division multiplexing (TDM). Wavelength conversion, multicode keying, optical logic gates, and quantum key distribution are some of the widely used security enhancement techniques but come at high cost and greater complexity. Zero cross correlation codes (ZCC) with integration of time dimension is an ultimate solution to the complex security improvement techniques but conventional two dimensional (2D) ZCC codes has an utmost issue of adjacent weights (W) and time (t) in the code which can be easily decoded by eavesdropper. Therefore, in this work, a novel weight managed ZCC (WMZCC) OCDMA code is presented with the non-adjacent W and t in the code matrix for making authentic information decoding difficult. Proposed 2D-WMZCC codes are investigated for 5 users at 100 Gbps over VLC link length of 5 m using polarization division multiplexed (PDM) quadrature phase shift keying (QPSK) and digital signal processing in terms of log symbol error rate (log SER), Q factor and bit error rate (BER). Further, a detailed comparison of 2D-WMZCC codes is performed with existing 2D diagonal identity matrix (DIM) codes and results revealed that former one exhibits better security than later OCDMA code. [ABSTRACT FROM AUTHOR]

This article introduces a paradigm shift in radar technology with field programmable gate array (FPGA)-driven Phase estimation using floating point arithmetic (FPA). Leveraging FPGA's parallel processing and the precision of FPA, this work promises enhanced accuracy and efficiency. The proposed system's key performance metrics include the following: number of slices: 20,941, number of look-up tables (LUTs): 22,371, number of digital signal processing (DSP) blocks: 2, delay: 112.9 ns, and power consumption: 7.2 mw. A comparative analysis showcases advantages in area utilization, LUT, and DSP blocks despite a trade-off with delay. The presented methodology and results demonstrate the feasibility of real-time phase estimation at GHz rates, positioning this approach as transformative for next-gen radar systems. [ABSTRACT FROM AUTHOR]

Sudden movements during the start and stop of electric elevators, known as jerks, can cause discomfort for passengers and negatively affect the performance and lifespan of their mechanical and electrical subsystems. Modern drives cannot directly regulate jerk, necessitating the development of methods to mitigate its effects. This study focuses on designing optimal S-curve motion profiles to reduce jerk in elevator systems driven by an induction motor. The motor operates according to these profiles when integrated with a TMS320F28335 Digital Signal Processor (DSP) under Direct Torque Control (DTC). Precise motor control is achieved using an incremental rotary encoder, current sensors, and voltage sensors, while an accelerometer sensor connected to an Arduino Nano measures the jerk. This comprehensive approach ensures precise regulation, smooth performance, and minimal sudden changes in acceleration, highlighting the effectiveness of DTC combined with S-curve profiles in enhancing elevator system performance. The results demonstrate that integrating S-curve profiles into the DTC algorithm significantly improves ride comfort by mitigating jerk during acceleration and deceleration phases by up to 57.2% compared to systems without S-curve integration. [ABSTRACT FROM AUTHOR]

Heart murmurs are abnormal heart sounds that can indicate various heart diseases. Although traditional auscultation methods are effective, they depend more on specialists' knowledge, making it difficult to make an accurate diagnosis. This paper presents a machine learning-based framework for the classification of acoustic sounds and heart murmurs using digital signal analysis. Using advanced machine learning algorithms, we aim to improve the accuracy, speed, and accessibility of heart murmur detection. The proposed method includes feature extraction from digital auscultatory recordings, preprocessing using signal processing techniques, and classification using state-of-the-art machine learning models. We evaluated the performance of different machine learning algorithms, such as convolutional neural networks (CNNs), random forests (RFs) and support vector machines (SVMs), on a selected heart noise dataset. The results show that our framework achieves high accuracy in differentiating normal heart sounds from different types of heart murmurs and provides a robust tool for clinical decision-making. [ABSTRACT FROM AUTHOR]

Designing high-speed and energy-efficient blocks for image and digital signal processing (DSP) architecture is an evolving research field. This work designs a high-speed and energy-efficient multiply-accumulate (MAC) unit to augment the performance of field-programmable gate array (FPGA)-based accelerators and softcore processors. In this work, three discrete 32-bit fixed-point signed MAC architectures were designed in Verilog and synthesized for the Zynq 7000 ZedBoard to obtain efficient MAC architecture. The ultimate goal of this work is to design a fast and energy-efficient MAC unit that can achieve speed up to the DSP48 block to reduce the latency of IoT edge computing. Energy efficiency was achieved in PPG and partial product addition (PPA) for the proposed Booth radix-4 Dadda (BR4D)-based MAC. At PPG, the width of the partial product (PP) terms was optimized with Bewick's signed extension to reduce the power consumption. At PPA, the number of PP rows reduces the critical path delay (CPD) with Dadda-based PPA. The proposed BR4D MAC unit offers a reduction in dynamic power, CPD, power-delay product (PDP) and energy-delay product (EDP) by 22%, 9%, 29% and 36%, respectively, compared to standard Booth radix-4 Wallace tree (BR4WT) based MAC. Furthermore, hybrid MACs (BR4WT and BR4D) were compared with the current state-of-the-art (SoA) designs, and it was found that the proposed BR4D MAC is 47% faster compared to the same design in SoA. The proposed BR4D was tested for frequency scaling technique by reducing the frequency in steps of 10 MHz from a maximum usable frequency (MUF) of 64 MHz to 10 MHz to evaluate the performance for low-power applications. Reducing clock frequency by 84% will reduce the power consumption at the same proportion and speed by 38%. Additionally, the proposed design helps to improve the battery life of IoT end nodes with a reduction in energy consumption and EDP by 76% and 61%, respectively. [ABSTRACT FROM AUTHOR]

In many industries and telecommunication system there is a need for digital signal processing for fast transfer of data between two points or devices with low power consumption and considerable hardware resources (circuit size and speed). Finite Impulse Response (FIR) filters play an important role in many signal processing applications and telecommunication systems. This paper propose the design and implementation of 4-bit FIR Filter using Distributed Arithmetic (DA) Algorithms, which substitute, multiply and accumulate operation with series of Look Up Table (LUT). The proposed FIR filter is implemented in high-density field programmable logic devices (FPGAs) and designed using very high-speed integrated circuit hardware description language (VHDL) and verified using Xilinx ISE 14.7 tool and simulator. The proposed, modified and optimized DA provided the multiplication and accumulation free calculation of inner product data of FIR filter and this consecutively reduces the size and power dissipation of circuit. DA is one of the methods to implement FIR filters that impact the storage resource and the calculating speed, which make the memory size smaller and the operation speed faster. The simulated proposed structure required nearly 40% less cells, 35% less LUT pairs and 4% less power consumption with existing structure. [ABSTRACT FROM AUTHOR]

This study introduces a novel deep learning-based approach for classifying poultry audio signals, incorporating a custom Burn Layer to enhance model robustness. The methodology integrates digital audio signal processing, convolutional neural networks (CNNs), and the innovative Burn Layer, which injects controlled random noise during training to reinforce the model's resilience to input signal variations. The proposed architecture is streamlined, with convolutional blocks, densely connected layers, dropout, and an additional Burn Layer to fortify robustness. The model demonstrates efficiency by reducing trainable parameters to 191,235, compared to traditional architectures with over 1.7 million parameters. The proposed model utilizes a Burn Layer with burn intensity as a parameter and an Adamax optimizer to optimize and address the overfitting problem. Thorough evaluation using six standard classification metrics showcases the model's superior performance, achieving exceptional sensitivity (96.77%), specificity (100.00%), precision (100.00%), negative predictive value (NPV) (95.00%), accuracy (98.55%), F1 score (98.36%), and Matthew's correlation coefficient (MCC) (95.88%). This research contributes valuable insights into the fields of audio signal processing, animal health monitoring, and robust deep-learning classification systems. The proposed model presents a systematic approach for developing and evaluating a deep learning-based poultry audio classification system. It processes raw audio data and labels to generate digital representations, utilizes a Burn Layer for training variability, and constructs a CNN model with convolutional blocks, pooling, and dense layers. The model is optimized using the Adamax algorithm and trained with data augmentation and early-stopping techniques. Rigorous assessment on a test dataset using standard metrics demonstrates the model's robustness and efficiency, with the potential to significantly advance animal health monitoring and disease detection through audio signal analysis. [ABSTRACT FROM AUTHOR]

Herein, the load power control of the stand‐alone photovoltaic‐battery hybrid power system (HPS) has been investigated. The underlying HPS consists of a boost DC‐DC converter, a non‐isolated bidirectional half‐bridge converter, a photovoltaic (PV) panel, and a battery pack. On the PV side, a disturbance observer‐based finite‐time terminal sliding mode control (FTSMC) is used to regulate the DC bus to the desired voltage, in the presence of irradiation variation and load changes. On the battery side, the load power control system is constructed, based on a model predictive control (MPC) algorithm, with constraints on state‐of‐charge (SOC) and maximum current value of the battery to improve the battery life cycle and high reliability of the system. To highlight the benefits of the closed‐loop system, the analytical proofs and numerical analysis are presented from a comparative viewpoint. The experimentally derived results, by implementation on TMS320F28335 digital signal processing (DSP), are also presented and discussed for practical justification. [ABSTRACT FROM AUTHOR]

Background: The aim is to investigate induced higher-order aberrations (HOA)s and astigmatism as a result of non-toric ortho-k lens decentration and utilise artificial intelligence (AI) to predict its magnitude and direction. Methods: Medmont E300 Video topographer was used to scan 249 corneas before and after ortho-k wear. Custom-built MATLAB codes extracted topography data and determined lens decentration from the boundary and midpoint of the central flattened treatment zone (TZ). An evaluation was carried out by conducting Zernike polynomial fittings via a computer-coded digital signal processing procedure. Finally, an AI-based machine learning neural network algorithm was developed to predict the direction and magnitude of TZ decentration. Results: Analysis of the first 21 Zernike polynomial coefficients indicate that the four low-order and four higher-order aberration terms were changed significantly by ortho-k wear. While baseline astigmatism was not correlated with lens decentration (R = 0.09), post-ortho-k astigmatism was moderately correlated with decentration (R = 0.38) and the difference in astigmatism (R = 0.3). Decentration was classified into three groups: ≤0.50 mm, reduced astigmatism by −0.9 ± 1 D; 0.5~1 mm, increased astigmatism by 0.8 ± 0.1 D; >1 mm, increased astigmatism by 2.7 ± 1.6 D and over 50% of lenses were decentred >0.5 mm. For lenses decentred >1 mm, 29.8% of right and 42.7% of left lenses decentred temporal-inferiorly and 13.7% of right and 9.4% of left lenses decentred temporal-superiorly. AI-based prediction successfully identified the decentration direction with accuracies of 70.2% for right and 71.8% for left lenses and predicted the magnitude of decentration with root-mean-square (RMS) of 0.31 mm and 0.25 mm for right and left eyes, respectively. Conclusions: Ortho-k lens decentration is common when fitting non-toric ortho-k lenses, resulting in induced HOAs and astigmatism, with the magnitude being related to the amount of decentration. AI-based algorithms can effectively predict decentration, potentially allowing for better control over ortho-k fitting and, thus, preferred clinical outcomes. [ABSTRACT FROM AUTHOR]

Atomic-scale imaging using scanning probe microscopy is a pivotal method for investigating the morphology and physico-chemical properties of nanostructured surfaces. Time resolution represents a significant limitation of this technique, as typical image acquisition times are on the order of several seconds or even a few minutes, while dynamic processes—such as surface restructuring or particle sintering, to be observed upon external stimuli such as changes in gas atmosphere or electrochemical potential—often occur within timescales shorter than a second. In this article, we present a fully redesigned field programmable gate array (FPGA)-based instrument that can be integrated into most commercially available standard scanning probe microscopes. This instrument not only significantly accelerates the acquisition of atomic-scale images by orders of magnitude but also enables the tracking of moving features such as adatoms, vacancies, or clusters across the surface ("atom tracking") due to the parallel execution of sophisticated control and acquisition algorithms and the fast exchange of data with an external processor. Each of these measurement modes requires a complex series of operations within the FPGA that are explained in detail. [ABSTRACT FROM AUTHOR]

Optical-based sensing techniques and instruments, such as fluorometric systems, absorbance-based sensors, and photoacoustic spectrometers, are important tools for detecting food fraud, adulteration, and contamination for health and environmental purposes. All the aforementioned optical equipments generally require one or more low-frequency Lock-In Amplifiers (LIAs) to extract the signal of interest from background noise. In the cited applications, the required LIA frequency is quite low (up to 1 kHz), and this leads to a simplification of the hardware with consequent good results in portability, reduced size, weight, and low-cost characteristics. The present system, called ENEA DSP Box Due, is based on a very inexpensive microcontroller proto-board and can replace four commercial LIAs, resulting in significant savings in both cost and space. Furthermore, it incorporates a dual-channel oscilloscope and a sinusoidal function generator. This article outlines the architecture of the ENEA DSP Box Due, its electrical characterization, and its applications within a project concerning laser techniques for food and water safety. [ABSTRACT FROM AUTHOR]

In this paper, a novel discrete flux-controlled generalized memristor is proposed to be used in Electromagnetic Radiation (EMR) KTz neuron. The introduction of flux-controlled memristor can simulate the behavior changes of the neuron under EMR. The stability of flux-controlled memristor EMR KTz Neuron (EKN) map is discussed, and the fixed point of the system is characterized. With the change of parameters, the complex and rich dynamical characteristics of the EKN map are demonstrated. The firing patterns under different initial values are also investigated, and discharge waveforms similar in general shape and structure to human heart and brain disease phenomena are analyzed. Finally, the hardware implementation is verified on the Digital Signal Processing (DSP) platform. The results show that these findings are of great value for the practical applications of neural networks, with a theoretical basis provided. [ABSTRACT FROM AUTHOR]

In embedded applications and digital signal processing systems, multipliers are crucial components. In these applications, there is an increasing need for energy-efficient circuits. We use an approximate adder for error tolerance in the computational process to improve performance and reduce power consumption. Due to human perceptual constraints, computational errors do not significantly affect applications like image, audio, and video processing. Adiabatic logic (AL), which recycles energy, can also be used to build circuits that require less energy. In this work, we propose a carry save array multiplier employing an approximate adder based on CMOS logic and clocked CMOS adiabatic logic (CCAL) to conserve power. Additionally, using a precise full adder, multiplier parameters like average power and power delay product are calculated and compared with the multiplier. We performed simulations using 180 nm technology in Cadence Virtuoso. [ABSTRACT FROM AUTHOR]

Coherent optics has profoundly impacted diverse applications ranging from communications, LiDAR to quantum computations. However, developing coherent systems in integrated photonics comes at great expense in hardware integration and energy efficiency. Here we demonstrate a high-coherence parallelization strategy for advanced integrated coherent systems at minimal cost. By using a self-injection locked microcomb to injection lock distributed feedback lasers, we achieve a record high on-chip gain of 60 dB with no degradation in coherence. This strategy enables highly coherent channels with linewidths down to 10 Hz and power over 20 dBm. The overall electrical-to-optical efficiency reaches 19%, comparable to that of advanced semiconductor lasers. This method supports a silicon photonic communication link with an unprecedented data rate beyond 60 Tbit/s and reduces phase-related DSP consumption by 99.99999% compared to traditional III-V laser pump schemes. This work paves the way for realizing scalable, high-performance coherent integrated photonic systems, potentially benefiting numerous applications. Researchers demonstrate the high-coherence parallelization in integrated photonics. Their high-coherence, high-power, multiwavelength light source drives a silicon photonic link with a 60 Tbit/s data rate and significantly reduces digital signal processing consumption. [ABSTRACT FROM AUTHOR]

This manuscript presents a novel control approach for Permanent Magnet Synchronous Motors (PMSMs) by integrating the widely used Direct Torque Control (DTC) method with Deep Reinforcement Learning (DRL), specifically the Twin Delayed Deep Deterministic Policy Gradient (TD3) algorithm. The TD3 algorithm is well-suited to address the challenges posed by high-dimensional state and action spaces in PMSM drives. The conventional Proportional–Integral (PI) controller in the outer loop of DTC is replaced with the DRL based TD3 agent to overcome the limitations of traditional PI controllers, such as model dependency and complex parameter tuning. The DRL technique allows the agent to learn optimal control policies from experience, making it suitable for complex and nonlinear control problems. Extensive simulation studies demonstrate the effectiveness of the TD3-based control in achieving accurate speed tracking under varying operating conditions. Real-time experimental validation using a TMS320F28379D digital signal processor confirms the feasibility of the proposed DRL based approach. The research offers new insights into improving the performance of PMSM drives and paves the way for future advancements in electric drive control. [ABSTRACT FROM AUTHOR]

Multiplication, division, and square root operations introduce significant challenges in digital signal processing (DSP) systems, traditionally requiring multiple operations that increase execution time and hardware complexity. This study presents a novel approach that leverages binary logarithms to perform these operations using only addition, subtraction, and shifts, enabling a unified hardware implementation—a marked departure from conventional methods that handle these operations separately. The proposed design, involving logarithm and antilogarithm calculations, exhibits an algebraically symmetrical pattern that further optimizes the processing flow. Additionally, this study introduces innovative log-domain correction terms specifically designed to minimize computation errors—a critical improvement over existing methods that often struggle with precision. Compared to standard hardware implementations, the proposed design significantly reduces hardware resource utilization and power consumption while maintaining high operational frequency. [ABSTRACT FROM AUTHOR]

Clinical fetal monitoring devices can only be operated by medical professionals and are overly costly, prone to detrimental false positives, and emit radiation. Thus, highly accurate, easily accessible, simplified, and cost-effective fetal monitoring devices have gained an enormous interest in obstetrics. In this study, a cost-effective and user-friendly wearable home fetal movement and distress detection device is developed and assessed for early-stage design progression by facilitating continuous, comfortable, and non-invasive monitoring of the fetus during the final trimester. The functionality of the developed prototype is mainly based on a microcontroller, a single accelerometer, and a specialized fetal phonocardiography (fPCG) acquisition board with a low-cost microphone. The developed system is capable of identifying fetal movement and monitors fetal heart rhythm owing to its considerable sensitivity. Further, the device includes a Global System for Mobile Communication (GSM)-based alert system for instant distress notifications to the mother, proxy, and emergency services. By incorporating digital signal processing, the system achieves zero false negatives in detecting fetal movements, which was validated against an open-source database. The acquired results clearly substantiated the efficacy of the fPCG acquisition board and alarm system, ensuring the prompt identification of fetal distress. [ABSTRACT FROM AUTHOR]

This document contains abstracts from the Journal of Neonatal - Perinatal Medicine, covering a range of topics related to neonatal encephalopathy (NE) and its associated complications. The studies explore the efficacy of AI-based seizure-detection algorithms, the feasibility of EEG recordings in emergency transport, the validation of neonatal encephalopathy scores using neurophysiology measures, and the use of an automated seizure detection algorithm for neonatal EEG. Additionally, the document discusses the development and achievements of the HRB Neonatal Encephalopathy PhD Training Network (HRB NEPTuNE) research program, which aims to improve understanding, diagnosis, and management of NE. The text also includes studies on somatosensory evoked potentials (SEPs), red reflex assessment, catecholamine therapy, and neonatal ventriculitis. [Extracted from the article]

The automated guided vehicle (AGV) is currently used in a wide range of industries. The control system is the core of the AGV, responsible for task assignment, localization, path planning, motion planning, vehicle management, etc. In previous AGV implementations, personal computer, embedded computer, digital signal processor for computing, and programmable logic controller, micro control unit, field programmable gate array for control have been combined to form the whole control system. These solutions can solve common control problems, but they are complex to implement. To simplify the implementation complexity, the following work is presented in this study: (1) a new real-time operating system (RTOS), called Student RTOS, is developed. The RTOS includes memory management, task management, message queue, semaphore, synchronization, and timer, etc.; (2) a control system based on the newly designed RTOS is presented on a single processor; (3) the RTOS and the control system are tested on a newly designed AGV. From the actual test results, the newly designed RTOS and control system can meet the requirements of real-time, functionality, etc., and can effectively replace the original control system composed of multiple device combinations. In addition to running on the ARM Cortex-A processor used in the AGV control system, the RTOS also runs on the ARM Cortex-M and the STM8S (8-bit) processors for more low-end applications. [ABSTRACT FROM AUTHOR]

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Sync word-based frame synchronization is an established method of frame synchronization that is employed in many low-resource applications because of its simplicity, and it involves the attachment of sync words (digital binary sequences) to the frames, which are then used for detection. Despite its simplicity, the method is underutilized today because there is no available hardware scheme that can perform correlation-based sync word frame synchronization with long sync words (>80 bits) efficiently. For this reason, the sync word methods that are used typically employ sync words of shorter lengths (<50 bits) with limited accuracy. This article introduces a highly modifiable, minimalist hardware architecture that performs correlation-based sync word frame synchronization using long sync words with evident accuracy gains over existing methods. As a bonus, the architecture not only detects the frame but also captures its payload regardless of size. Its low complexity allows for its deployment at a low cost in terms of hardware resources and power while providing high bit rates. Its flexibility is demonstrated by using a low-cost FPGA for implementation. [ABSTRACT FROM AUTHOR]

The You Only Look Once (YOLO) object detection network has garnered widespread adoption in various industries, owing to its superior inference speed and robust detection capabilities. This model has proven invaluable in automating production processes such as material processing, machining, and quality inspection. However, as market competition intensifies, there is a constant demand for higher detection speed and accuracy. Current FPGA accelerators based on 8-bit quantization have struggled to meet these increasingly stringent performance requirements. In response, we present a novel 4-bit quantization-based neural network accelerator for the YOLOv5 model, designed to enhance real-time processing capabilities while maintaining high detection accuracy. To achieve effective model compression, we introduce an optimized quantization scheme that reduces the bit-width of the entire YOLO network—including the first layer—to 4 bits, with only a 1.5% degradation in mean Average Precision (mAP). For the hardware implementation, we propose a unified Digital Signal Processor (DSP) packing scheme, coupled with a novel parity adder tree architecture that accommodates the proposed quantization strategies. This approach efficiently reduces on-chip DSP utilization by 50%, offering a significant improvement in performance and resource efficiency. Experimental results show that the industrial object detection system based on the proposed FPGA accelerator achieves a throughput of 808.6 GOPS and an efficiency of 0.49 GOPS/DSP for YOLOv5s on the ZCU102 board, which is 29% higher than a commercial FPGA accelerator design (Xilinx's Vitis AI). [ABSTRACT FROM AUTHOR]

In order to solve the problem of duplicate data entry between construction management platform systems in construction engineering, the author proposes to apply RPA intelligent process robots to replace manual data collection, operation, entry, and verification. The design of the system is divided into overall architecture, instruction program loading process, human-machine interaction system level services, and other levels. An end-to-end procedural instruction transmission control method is adopted, establish a low-level control command output module for the online calibration system of the flight path, using a basic service architecture system, implement human-machine interactive control of the online calibration system for flight paths on the B/S architecture system. Build a record controller module for the inspection trajectory correction of RPA intelligent process robots, and perform feedback control during the trajectory correction process in LOG-CONTROL-BLOCK, using the RPA feedback correction algorithm, achieve adaptive correction and error feedback tracking of the inspection trajectory of RPA intelligent process robots. Implement calibration system development and design in an integrated DSP (Digital Signal Processing) information processing platform. The experimental results show that good economic benefits have been achieved through application, and the problem of duplicate data entry between the employer's IFS system and the ENPOWER document management system has been solved, greatly reducing error rates and personnel costs. It can replace manual data collection, entry, verification, and business operations; It has the characteristics of low error rate, low cost, high accuracy, compliance, and 24/7 standby; In 2021, 108000 yuan was saved, in 2022, 432000 yuan was saved, and in 2023, 432000 yuan was saved, demonstrating the labor hour cost savings achieved by utilizing RPA intelligent process robots. [ABSTRACT FROM AUTHOR]

Electroencephalography (EEG) is a medical engineering technique aimed at recording the electric activity of the human brain. Brain signals derived from an EEG device can be processed and analyzed through computers by using digital signal processing, computational statistics, and machine learning techniques, that can lead to scientifically-relevant results and outcomes about how the brain works. In the last decades, the spread of EEG devices and the higher availability of EEG data, of computational resources, and of software packages for electroencephalography analysis has made EEG signal processing easier and faster to perform for any researcher worldwide. This increased ease to carry out computational analyses of EEG data, however, has made it easier to make mistakes, as well. And these mistakes, if unnoticed or treated wrongly, can in turn lead to wrong results or misleading outcomes, with worrisome consequences for patients and for the advancements of the knowledge about human brain. To tackle this problem, we present here our ten quick tips to perform electroencephalography signal processing analyses avoiding common mistakes: a short list of guidelines designed for beginners on what to do, how to do it, and what not to do when analyzing EEG data with a computer. We believe that following our quick recommendations can lead to better, more reliable and more robust results and outcome in clinical neuroscientific research. [ABSTRACT FROM AUTHOR]