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Confinement in two-dimensional transition metal dichalcogenides is an attractive platform for trapping single charge and spins for quantum information processing. Here, we present low-temperature e...

The bid for scalable physical qubits has attracted many possible candidate platforms. In particular, spin-based qubits in solid-state form factors are attractive as they could potentially benefit from processes similar to those used for conventional semiconductor processing. However, material control is a significant challenge for solid-state spin qubits as residual spins from substrate, dielectric, electrodes or contaminants from processing contribute to spin decoherence. In the recent decade, valleytronics has seen a revival due to the discovery of valley-coupled spins in monolayer transition metal dichalcogenides. Such valley-coupled spins are protected by inversion asymmetry and time-reversal symmetry and are promising candidates for robust qubits. In this report, the progress toward building such qubits is presented. Following an introduction to the key attractions in fabricating such qubits, an up-to-date brief is provided for the status of each key step, highlighting advancements made and/or outstanding work to be done. This report concludes with a perspective on future development highlighting major remaining milestones toward scalable spin-valley qubits.

The ability to manipulate electron spins with voltage-dependent electric fields is key to the operation of quantum spintronics devices, such as spin-based semiconductor qubits. A natural approach to electrical spin control exploits the spin–orbit coupling (SOC) inherently present in all materials. So far, this approach could not be applied to electrons in silicon, due to their extremely weak SOC. Here we report an experimental realization of electrically driven electron–spin resonance in a silicon-on-insulator (SOI) nanowire quantum dot device. The underlying driving mechanism results from an interplay between SOC and the multi-valley structure of the silicon conduction band, which is enhanced in the investigated nanowire geometry. We present a simple model capturing the essential physics and use tight-binding simulations for a more quantitative analysis. We discuss the relevance of our findings to the development of compact and scalable electron–spin qubits in silicon. Weak spin–orbit effects in silicon can be exploited to electrically drive electron-spin resonance in a silicon nanowire quantum dot device with low-symmetry confinement potential. Andrea Corna and colleagues at Grenoble’s CEA and University Grenoble Alpes achieved this by fabricating a silicon nanowire device over a silicon-on-insulator wafer, on which the gate accumulation voltages can define two corner quantum dots. Quantum confinement allows the coupling of spin and valley degrees of freedom via spin–orbit coupling, despite its inherent weakness in silicon, when the energy splitting between the valley energy eigenstates matches the magnetic field-induced Zeeman spin splitting. The observation of electric-dipole spin-valley resonance demonstrates the potential of spin–orbit coupling for realizing electric-field-mediated spin control, which will be crucial for large-scale integration of silicon-based spin qubits.

We study field effect transistor characteristics in etched single layer MoS2 nanoribbon devices of width 50nm with ohmic contacts. We employ a SF6 dry plasma process to etch MoS2 nanoribbons using low etching (RF) power allowing very good control over etching rate. Transconductance measurements reveal a steep sub-threshold slope of 3.5V/dec using a global backgate. Moreover, we measure a high current density of 38 uA/um resulting in high on/off ratio of the order of 10^5. We observe mobility reaching as high as 50 cm^2/V.s with increasing source-drain bias., 4 pages, 3 figures

In a semiconductor spin qubit with sizable spin-orbit coupling, coherent spin rotations can be driven by a resonant gate-voltage modulation. Recently, we have exploited this opportunity in the experimental demonstration of a hole spin qubit in a silicon device. Here we investigate the underlying physical mechanisms by measuring the full angular dependence of the Rabi frequency as well as the gate-voltage dependence and anisotropy of the hole $g$-factors. We show that a $g$-matrix formalism can simultaneously capture and discriminate the contributions of two mechanisms so far independently discussed in the literature: one associated with the modulation of the $g$ factors, and measurable by Zeeman energy spectroscopy, the other not. Our approach has a general validity and can be applied to the analysis of other types of spin-orbit qubits., Comment: Letter format (4 pages, 4 figures). Detailed theory in Supplemenatl Material

We study ballistic hole transport through Ge/Si core/shell nanowires at low temperatures. We observe Fabry-P$\acute{e}$rot interference patterns as well as conductance plateaus at integer multiples of 2e$^2$/h at zero magnetic field. Magnetic field evolution of these plateaus reveals large effective Land$\acute{e}$ g-factors. Ballistic effects are observed in nanowires with silicon shell thicknesses of 1 - 3 nm, but not in bare germanium wires. These findings inform the future development of spin and topological quantum devices which rely on ballistic subband-resolved transport., 8 pages, 4 figures

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal–oxide–semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform., Silicon is a promising material for realization of quantum processors, particularly as it could be naturally integrated with classical control hardware based on CMOS technology. Here the authors report a silicon qubit device made with an industry-standard fabrication process on a CMOS platform.

We report on dual-gate reflectometry in a metal-oxide-semiconductor double-gate silicon transistor operating at low temperature as a double quantum dot device. The reflectometry setup consists of two radio-frequency resonators respectively connected to the two gate electrodes. By simultaneously measuring their dispersive response, we obtain the complete charge stability diagram of the device. Charge transitions between the two quantum dots and between each quantum dot and either the source or the drain contact are detected through phase shifts in the reflected radio-frequency signals. At finite bias, reflectometry allows probing charge transitions to excited quantum-dot states thereby enabling direct access to the energy level spectra of the quantum dots. Interestingly, we find that in the presence of charge transport across the two dots the reflectometry signatures of interdot transitions display a dip-peak structure containing quantitative information on the charge relaxation rates in the double quantum dot., 7 pages, 4 figures

We report the first quantum bit (qubit) device implemented on a foundry-compatible Si CMOS platform. The device, fabricated using SOI NanoWire MOSFET technology, is in essence a compact two-gate pFET. The qubit is encoded in the spin degree of freedom of a hole Quantum Dot (QD) defined by one of the Gates. Coherent spin manipulation is performed by means of an RF E-Field signal applied to the Gate itself. By demonstrating qubit functionality in a conventional transistor-like layout and process flow, this result bears relevance for the future up-scaling of qubit architectures, including the opportunity of their co-integration with “classical” Si CMOS control circuitry.

The first few decades of the previous century have witnessed a revolution in the physical sciences due to the advent of quantum mechanics. Now, a hundred years later, quantum mechanics is about to drive a new revolution in technology. As a matter of fact, quantum mechanical phenomena have already found numerous applications in different areas (metrology, sensing, imaging, etc.). Atomic clocks and superconducting quantum interference devices (used for magnetometry), are just a few examples of commercial quantum devices. Yet these examples can be regarded as basic-level quantum technology. The next step is to exploit the inherent complexity of quantum systems, whose origin lies in the basic principle of superposition, namely the property of a quantum object to be simultaneously in two or more possible states. If we consider the simplest case of a quantum particle, e.g. an electron, with two possible states, say state ‘0’ and state ‘1’, the superposition principle allows for that particle to be in both 0 and 1 at the same time (see Fig. 1 and corresponding caption). In a way, a quantum particle can thus encode much more information than a classical device (e.g. a transistor) with only two possible states. A second key property of quantum particles is their ability to couple among each other without necessarily requiring reciprocal interaction. This property, known as quantum entanglement together with the principle of superposition, forms the key elements of quantum information processing. They result in a naturally built-in parallelism that could be exploited to achieve computational powers unaffordable by any classical computer.

We present recent progress towards the implementation of a scalable quantum processor based on fully-depleted silicon-on-insulator (FDSOI) technology. In particular, we discuss an approach where the elementary bits of quantum information - so-called qubits - are encoded in the spin degree of freedom of gate-confined holes in p-type devices. We show how a hole-spin can be efficiently manipulated by means of a microwave excitation applied to the corresponding confining gate. The hole spin state can be read out and reinitialized through a Pauli blockade mechanism. The studied devices are derived from silicon nanowire field-effect transistors. We discuss their prospects for scalability and, more broadly, the potential advantages of FDSOI technology., Comment: 4 pages, 13 figures, Invited contribution at IEDM 2016

Low temperature electron transport measurements of single electron transistors fabricated in advanced CMOS technology with polysilicon gates not only exhibit clear Coulomb blockade behavior but also show a large number of additional conductance fluctuations in the nonlinear regime. By comparison with simulations these features are quantitatively attributed to the effects of discretely charged islands in the polysilicon gates.

We report electronic transport on n-type silicon Single Electron Transistors (SETs) fabricated in Complementary Metal Oxide Semiconductor (CMOS) technology. The n-MOSSETs are built within a pre-industrial Fully Depleted Silicon On Insulator (FDSOI) technology with a silicon thickness down to 10 nm on 200 mm wafers. The nominal channel size of 20 $\times$ 20 nm$^{2}$ is obtained by employing electron beam lithography for active and gate levels patterning. The Coulomb blockade stability diagram is precisely resolved at 4.2 K and it exhibits large addition energies of tens of meV. The confinement of the electrons in the quantum dot has been modeled by using a Current Spin Density Functional Theory (CS-DFT) method. CMOS technology enables massive production of SETs for ultimate nanoelectronics and quantum variables based devices., Comment: 4 Figures

It is very important to study variability of nanodevices because the inability to produce large amounts of identical nanostructures is eventually a bottleneck for any application. In fact variability is already a major concern for CMOS circuits. In this work we report on the variability of dozens of silicon single-electron transistors (SETs). At room temperature their variability is compared with the variability of the most advanced CMOS FET i.e. the ultra thin Silicon-on-Insulator Multiple gate FET (UT SOI MuGFET). We found that dopants diffused from Source –Drain into the edge of the undoped channel are the main source of variability. This emphasizes the role of extrinsic factors like the contact junctions for variability of any nanodevice.