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Optical Character Recognition (OCR) is an indispensable tool for technology users nowadays, as our natural language is presented through text. We live under the need of having information at hand in every circumstance and, at the same time, having machines understand visual content and thus enable the user to be able to search through large quantities of text. To detect textual information and page layout in an image page, the latter must be properly oriented. This is the problem of the so-called document deskew, i.e., finding the skew angle and rotating by its opposite. This paper presents an original approach which combines various algorithms that solve the skew detection problem, with the purpose of always having at least one to compensate for the others' shortcomings, so that any type of input document can be processed with good precision and solid confidence in the output result. The tests performed proved that the proposed solution is very robust and accurate, thus being suitable for large scale digitization projects. [ABSTRACT FROM AUTHOR]

Optical Character Recognition (OCR) is an indispensable tool for technology users nowadays, as our natural language is presented through text. We live under the need of having information at hand in every circumstance and, at the same time, having machines understand visual content and thus enable the user to be able to search through large quantities of text. To detect textual information and page layout in an image page, the latter must be properly oriented. This is the problem of the so-called document deskew, i.e., finding the skew angle and rotating by its opposite. This paper presents an original approach which combines various algorithms that solve the skew detection problem, with the purpose of always having at least one to compensate for the others’ shortcomings, so that any type of input document can be processed with good precision and solid confidence in the output result. The tests performed proved that the proposed solution is very robust and accurate, thus being suitable for large scale digitization projects.

This paper addresses the research area of Document Image Skew Detection and Correction. The problem is of critical importance in the automated content conversion systems domain, making libraries digitalization projects possible. The paper at hand consists in a comparison between the main types of skew detection algorithms and presents the reader with a study on their advantages and disadvantages, as well as proposed improvements. [ABSTRACT FROM AUTHOR]

In this paper, we present novel techniques to handle the complexity and challenges in clock distribution for 3-D integrated circuit. First, we propose a novel active deskew technique to adaptively mitigate the cross-tier variations and the 3-D wiring asymmetry. The new deskew technique neither relies on an accurate through-silicon-vias model nor an accurate reference clock distribution. Second, we design a phase-mixer-based tunable-delay-buffer (TDB), which can be linearly tuned in 360° and tolerant to process-voltage-termperature (PVT) variations. Third, based on the new deskew technique and TDB design, we propose an efficient clock distribution network topology, which can be realized without a need of balanced H-tree. Moreover, a thermal profile-based optimization flow is developed to further improve the power efficiency and reduce design overhead. A case study shows that the proposed techniques are able to largely improve the clock skews. The optimization flow is capable of reducing the design cost to achieve a better tradeoff of the skew performance and the design overhead. [ABSTRACT FROM AUTHOR]

Skew detection for scanned documents is an important field of research, of great interest for both academic and commercial environments. The Hough transform has been established as the standard for accurate skew detection, thanks to its high accuracy and mathematical soundness. Unfortunately, this high accuracy comes with a high time penalty, and thus the search for speed improvements that do not reduce accuracy is on. The present article will present an impartial comparison of the proposed methods and point out each method strong and weak points. [ABSTRACT FROM AUTHOR]

A 2-Gb/s point-to-point intrapanel interface for thin-film-transistor liquid crystal display (TFT-LCD) is proposed by using only clock and data lines. Extra control lines are eliminated by sending the VSYNC code through the clock line at the start of the VBLANK time period and by sending the control commands through the data line at the end of the VBLANK time period. To reduce electromagnetic interference, the slew rate of the clock driver is reduced, and the frequency of clock signals is set to the subpixel (R/G/B) frequency (1/10 of the data rate). The clock line is cascaded between two adjacent receiver (RX) chips for a point-to-point interface. To generate an internal clock synchronized (deskewed) to the subpixel (R/G/B) boundary of incoming data at each RX, a single all-digital delay-locked loop (DLL) circuit is proposed to perform the combined operation of a DLL and a phase interpolator. This deskew operation is performed during the VBLANK period with periodic preamble data input (‘1111100000’). At the RX, a multiphase DLL follows the deskew DLL to generate 20-phase clocks for data sampling. 2-Gb/s data are transmitted through a series connection of a 100-cm-long flat flexible cable and a 50-cm-long FR4 microstrip line with a bit error rate less than 1e–12. The image test was successfully performed with a 42-in full-high definition 120-Hz LCD panel at 1.5 Gbps. The area and power consumption of RX chip is 0.35 \mm^2 and 52.4 mW at 2 Gbps with a 0.18- \mu\m complementary metal–oxide–semiconductor process and a 1.8-V supply. [ABSTRACT FROM PUBLISHER]

A Dual-mode 2\,\times\,21.5–22.3 Gb/s DQPSK or 1\,\times\,39.8–44.6 Gb/s NRZ to 4\,\times\,9.95–11.2 Gb/s SFI5.2-compliant two-chip SerDes for a family of 40 Gb/s optical transponders has been fabricated in 65 nm 12-metal CMOS. By demultiplexing to 16\,\times\,2.5 Gb/s internally, all logic and testability functions could be implemented in standard-cell CMOS, resulting in total power consumption of 3 W, 75% lower than commercial BiCMOS SFI5 40 Gb/s SerDes ICs. Chip area is 4\,\times\,4 mm, and the ICs are flip-chip mounted into a quad flat-pack package. [ABSTRACT FROM PUBLISHER]

Active deskewing is an important technique for managing variability in clock distributions but introduces latency and power-supply-noise sensitivity into the resulting networks. In this paper, an adaptively deskewed resonant clock network, based on an injection-locked distributed differential oscillator, is described, in which the delay lines required for deskewing are incorporated into the injection-lock source, dramatically improving jitter immunity. A power management system based on automatic amplitude control of the resonant grid further enhances energy efficiency. A prototype system operates at a nominal 2-GHz frequency in a 0.18 μm technology with on-chip jitter and skew measurement circuits and with more than 25 pF/mm² of clock loading. [ABSTRACT FROM AUTHOR]