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March algorithms are widely used in Memory Built-In Self-Test (MBIST) on-chip memory testing, providing linear test complexities that reduce the test time and cost. However, studies show that March algorithms with complexities lower than 18N have poor coverages of faults that have emerged with the advent of the nanometer process technologies and are more relevant to nowadays memories. New March AZ1 and March AZ2 algorithms, with 13N and 14N complexities, respectively, were introduced to provide optimum coverage of those faults and to produce a shorter test than an 18N-complexity test algorithm with a lesser area overhead, thus reducing chip manufacturing costs. This paper presents the implementation and validation of MBIST controllers that applied the March AZ1 and March AZ2 algorithms in a Field-Programmable Gate Array (FPGA) device. They were implemented in the Intel Max 10 DE10-Lite FPGA Development Board. A test generator was built in FPGA, as an alternative to the external tester, to provide test vectors required in initiating the test on the memory model using the implemented MBIST. The FPGA experimental tests demonstrated that they function correctly as the expected test sequences were observed. In addition, their fault detection abilities were also validated through tests on a fault-injected memory model, which shows that the implemented March AZ1 and March AZ2 provide 80.6% and 83.3% coverage of the intended faults, respectively, which outperform any other existing 14N-complexity March algorithms. [ABSTRACT FROM AUTHOR]

DFT is a technique that converts the design into testable after manufacturing. As technology is shrinking, the complexity of inserting the DFT is becoming high. When it comes to DFT timing, controlling clocks in test mode is become a challenge nowadays. To achieve the high scan shift speed and to reduce the tester time, a new architecture is proposed in this work. The objective of this work is to propose a new design for clock controlling in DFT timing and working of the proposed block by configuring the different Test Data Registers. The proposed clock provides the clock intercepts for scan and debug modes along with features such as a single clock entry point per tile, clock stop using TDR, capture clock path same as functional mode path, and staggering pulse generation for LOS and LOC. The scannable logic in any tile must receive a clock from the clock control block. The tile level clock can be gated inside this block. A pulse generation logic is used to control the Gater inside the proposed design. The dynamic power consumption of the proposed architecture is compared with different clock architectures. The dynamic Power consumption is calculated as 60 mW which is less compared to already existing on-chip clock controllers in the DFT.

This study introduces a novel algorithm for the detection of three-cell coupling faults, March ML3C, along with a simulator, TCFS. The March ML3C algorithm targets the detection of single-port, static, and unlinked three-cell coupling faults within bit-oriented random access memory (RAM). March ML3C improves the coverage of three-cell coupling faults to 100%, with a complexity of only 58n (n is the number of memory cells), which is lower than that of most similar algorithms. Furthermore, to solve the problem of none of the existing tools supporting the simulation of three-cell coupling faults, this study designs and implements TCFS, which can quickly simulate all March-type algorithms and calculate the coverages for three-cell coupling faults, thus achieving the purpose of software simulation of the algorithms. The simulation results of March ML3C and other similar algorithms using TCFS are also presented in this paper.

Design for testability (DFT) is a technique, which facilitates a design to become testable after fabrication. As the technology node is shrinking, complexity of the system-on-chip (SoC) becomes high and inserting DFT and verifying its timing becomes complex. For these complex SoC, generating DFT timing constraints becomes difficult in shift mode and the time required for the generation of these timing constraints is also more. A new methodology proposed to overcome these issues. The main objective of this work is to propose the flow for generating DFT timing constraints for the complex SoC in shift mode, by dividing the design blocks into scan blocks and non-scan blocks. To target the whole design without getting all paths reported, relaxation of the setup, and hold time for non-scan blocks plays crucial role. If not, the time taken to generate DFT timing constraints would be more. Implemented methodology of this paper includes design setup, timing exceptions, and synopsys design constraints (SDC) generation for DFT timing. Design setup consists of all pre-requisites for design such as netlists, timing libraries, and exceptions. Synopsys primetime (PT Shell) is used for all the timing-related checks. Compared to conventional methods, the proposed flow reduces the overall time by 40% to generate constraints. [ABSTRACT FROM AUTHOR]

Oscillation-based testing (OBT) and Oscillation-based built-in self-testing (OBIST) circuits enable detection of catastrophic faults in analogue and RF circuits, but both are sensitive to process, voltage and temperature (PVT) variation. This paper investigates 15 OBT and OBIST feature extraction strategies, and four approaches to threshold selection, by calculating figure-of-merit (FOM) across PVT variation. This is done using a 2.4 GHz LNA in $0.35 \mu \mathrm{m}$ CMOS as DUT. Of the 15 feature extraction approaches, the OBT approaches are found more effective, with some benefit gained from switched-state detection. Of the four approaches to threshold selection (nominal-ranged static thresholds, extreme-range static thresholds, temperature dynamic thresholds, and simple noise-filtered tone detection), dynamic thresholds resulted in the highest average FoM of 0.919, with the best FoM of 0.952, with a corresponding probability of test escape $P\left(T_E\right)$ and yield loss $P\left(Y_L\right)$ of $5 \cdot 10^{-2}$ and $1.89 \cdot 10^{-2}$ respectively but requires accurate temperature measurement. Extreme static threshold selection resulted in a comparable average FoM of 0.912, but with less susceptibility to process variation and without the need for temperature measurement. Binary detection of a noise-filtered oscillating tone is found the least complex approach, with an average FoM of 0.891.

Test management is a critical problem for in-time correction-based testability growth test. For the existing testability growth model, they are either too complex to be implemented in practice, or do not have the ability to draw a smooth test planning/projecting curve. This paper proposes a unified model for in-time correction-based testability growth test and presents its application on the test planning. Firstly, a simple model with only three parameters is developed, and its compatibility with the original Markov model is proved. The revised model only has three parameters, which can reduce the complexity of parameters estimation and increase the certainty of the test planning. Secondly, the paper incorporates the simplified transition probability model with the test cost model and studies the optimal test planning method with the minimum test cost criterion. To illustrate the efficacy of the proposed model, an application of the model to an attitude control system of a helicopter available in the open literature is given. The simulation demonstrates that the model and the method proposed in this paper are reasonable, and they are useful for effectively managing the testability growth test planning problem during system maturation. [ABSTRACT FROM AUTHOR]

A new architecture of 4-bit reversible multiplier with scalability factor of order 4 N is presented in this paper. The design procedure is based on a unique method of gates placement, which produces parity preserving circuits. This property facilitates graceful testing and full coverage of single-bit faults at lower overhead. The circuit is designed and implemented on the top of reversible analyser for obtaining operating costs in terms of number of wires, gate cost, quantum cost, garbage output and ancilla input. Testable implementation of recently reported multiplier circuits has also been performed using the existing method of testing under the same platform. This work achieved a reduction of up to 33% in operating costs when all the parameters are combined together. [ABSTRACT FROM AUTHOR]

Abstract Integrated circuits (ICs) design plays a significant role in the embedded‐system performance, reliability and security. Thus, the constant advances in very large‐scale integration technology have led to design and manufacture of very complex ICs based on the System on a Chip (SoC) approach design. Therefore, the embedded system testing is considered earlier during the design process and testability is used as one of the objectives for evaluating safety‐critical embedded system designs. On the other hand, embedded systems used in critical applications execute security‐critical commands and collect sensitive data protected by cryptographic keys and authentication codes. The data and the unauthorised access of these embedded devices is an obvious target for attackers in order to obtain control or extract internal data. In this paper we consider that by using Design for Testability (DFT) approaches an attacker can control and affect a security‐critical embedded system. Thus, the authors focus on the DFT approach, as a means of violation of the security and confidentiality of embedded systems with security‐critical goals. In addition, with or without insertion of DFT circuitry, the crypto‐core is always exposed to the powerful differential fault analysis (DFA) attack. Here, a 32‐bit AES crypto‐core is used as a case study in order to analyse the DFA‐ and the DFT‐based Hacking techniques. A countermeasure was performed in order to avoid any scan or even DFA attack attempt.

High-Level Synthesis (HLS) tools help engineers to deal with the complexity of building heterogeneous embedded systems that make it use of reconfigurable technology. Also, HLS opens up a way for introducing, into the development flow of custom hardware components, techniques well known in the software industry such as Test-Driven Development (TDD). However, the support provided by HLS tools for verification activities is limited, and it is usually focused on the initial steps of the design process. In this paper, a hardware testing framework is introduced as an enabler for effortless on-board verification of components by applying the Unit Testing Paradigm and, hence, realizing TDD on reconfigurable hardware. The proposed solution comprises a hardware/software introspection infrastructure to verify modules of a system at different stages, spawning multiple abstraction levels without extra effort nor redesigning the component. Our solution has been implemented for the Xilinx ZynQ FPGA-SoC architecture and applied to the verification of C-kernels within the CHStone Benchmark. Effortless integration into the Xilinx Vivado design flow and tools is supported by a set of automatic generation scripts developed for this end. Experimental results show a considerable speedup of the verification time and unveils inaccuracies concerning the co-simulation estimation obtained by Xilinx tools when compared with the on-board latency measured by our framework.

The application diversity and evolution of AI accelerator architectures require innovative DFT solutions to address issues such as test time, test power, performance and area overhead. Full scan DFT, because of its enhanced controllability and observability, is an industrial de facto test strategy. However, it may not yield an optimal test solution with stringent design constraints of edge-based AI accelerators. In this paper, a novel test architecture based on selective-partial scan is proposed for performance, power and area (PPA) overhead constrained edge-based systolic AI accelerator. In this architecture, the structural test patterns are applied partly in functional manner, which reduces the testability problem of an array to that of a single processing element (PE); thus, resulting in reduced test time and test data volume. Moreover, a delay fault testing method based on Launch-on-Capture is presented for the partial scan based proposed architecture. Experimental results show that proposed architecture is efficient in terms of test power and test time when compared to full scan DFT.

Scan-based logic built-in self-test (LBIST) is widely used for supporting the in-system test in automotive systems. Although this technology has the advantage of low-cost testing, it suffers from low fault coverage and high switching activity during the test. This can lead to many undetected defects, excessive heat dissipation, and IR drop, inducing catastrophic risks to functional safety. Therefore, improving these two key factors is crucial to alleviate reliability problems in the automotive domain. Most previous works have focused on controlling the enormous toggling level of random patterns; however, one of the main disadvantages of these approaches is low fault coverage. Unfortunately, additional hardware costs associated with memory elements or test points are required for detecting the remaining faults. We propose a novel LBIST scheme based on weight-aware scan grouping and scheduling (WGS) to overcome these difficulties. Since the required test time of each automotive product is limited, the proposed scheme freezes the test time and focuses on improving both aforementioned factors significantly. Our approach divides scan cells into two categories: the coverage-efficient scan group and power-efficient scan group, and then it conducts weight-based scan cell reordering. Biased random patterns are fed to enhance fault coverage for the first category. For the second category, scheduling and disabling are performed to reduce switching activity. Finally, physical-aware reordering based on an inverter is performed to reduce routing overhead. Experimental results demonstrate the feasibility of the WGS methodology on the ITC’99 and OpenRISC benchmark circuits.

Scan chain diagnosis is essential to solving yield-reduction problem caused by the miniaturization of manufacturing process. The accurate diagnosis of scan chain faults that frequently occur in the initial process is vital for rapidly improving yield. Moreover, the importance of scan chain diagnosis with a high resolution for the multiple faults is increasing because multiple faults occur in the early stages of the process, further increasing the cost of physical failure analysis. Although multiple faults can be diagnosed with existing methods, a high diagnostic resolution is difficult to achieve in the early stages of the process (where many faults occur) due to the rapid increase in the number of diagnosed fault candidates as the number of actual faults in the circuit increases. In this paper, a novel reconfigurable scan architecture that reconfigures the diagnosis paths and a test algorithm that uses this scan architecture are proposed to reduce the number of diagnosed fault candidates in the scan chain diagnosis with multiple circuit faults. Experimental results indicate that the proposed method achieves the higher diagnostic resolution for multiple faults than conventional methods. In addition, the proposed method reduces the routing overhead by scan partitioning.

The power consumption of modern highly complex chips during scan test is significantly higher than the power consumed during functional mode. This leads to substantial heat dissipation, excessive IR drop, and unrealistic timing failures of the integrated circuits (ICs) under test. In this brief, a ByPassable Scan Data Retention Flip-Flop (BPS-DRFF) is proposed for low-power IC test. The proposed flip-flop contains two secondary latches. The output of the “function” secondary latch goes to the following combinational circuits, while the other “shadow” secondary latch is used to shift test vectors during scan test. By gating the output of the function secondary latch, the redundant switching activity in the combinational circuits is eliminated during scan shift, thereby reducing the test power consumption significantly. The suppressed switching activity also leads to lower IR drop across the chip, increasing the chip manufacturing yield. Furthermore, the shadow latch is reused for data retention in the sleep mode while performing power gating, thereby alleviating the area cost of the shadow latch. The proposed BPS-DRFF also eases the hold time sign-off in the test mode due to the elongated clock-to-Q contamination delay that is brought in by the shadow latch. The proposed design is applied to an AES-128 crypto core in a UMC 55-nm low power CMOS technology. Experiment results show that 68.5% power is saved during scan test with the proposed BPS-DRFF, compared to the standard scan retention flip-flop. [ABSTRACT FROM AUTHOR]

Test time, test data volume, and test power have been a major concern in Serial Access Scan (SAS) based manufacturing test. Alternatively, the Random Access Scan (RAS) architecture has been proposed to mitigate some of these problems. However, some of the drawbacks, particularly the area and routing congestion of RAS puts a limit on its industry adoption. In this work, we propose a framework of a new scan architecture which we name as Joint-scan that aims to combine both the SAS and RAS to harness the best out of each of the architectures. The principle is to harness the advantage of the area from SAS architecture and the advantage of test power from RAS architecture. The other two parameters, test time and test data volume, are minimized by fine-tuning the proposed scan architecture. The architecture is also configurable to take the design constraints into consideration. Effectiveness of the architecture is experimentally demonstrated on the scaled ISCAS 89 circuits. [ABSTRACT FROM AUTHOR]

This work presents an efficient test technique for detecting resistive short defects in STT-MRAM arrays. The proposed technique is based on monitoring the current mismatch flowing into and out of the cell caused by a weak or strong short defect. This technique is used to propose a low area overhead Design-for-Testability (DFT) circuit to employ in STT-MRAM arrays to distinguish defect-free cells from faulty ones. The operation of the proposed test approach is resilient to the parameter uncertainties of the array circuit induced by process variations. The variations, however, may lower defect detection ranges. The efficacies of the proposed DFT technique under the nominal and the process variation cases are studied. Simulation results indicate that the proposed DFT circuit reduces the number of test escapes and improves the fault coverage by a factor of at least $10 \times $ ($5 \times $) under short defect to ground (short defect to ${V}_{DD}$) cases compared to the corresponding maximum ones detected by conventional test schemes. The technique works through a single read operation with a negligible area overhead, especially, in large size arrays. [ABSTRACT FROM AUTHOR]

It is a real challenge to test asynchronous circuits since there is no clock signal, and there are many non-scan state-holding elements. In this paper, we first propose an Asynchronous Circuit Scan (A-SCAN) latch, which can flip between Valid and Empty states so that we can shift in and out without any clock. Experimental results show that our DFT area and power overhead are 28% and 104% smaller than previous synchronous DFT, respectively. The timing overhead of DFT is nearly two times smaller than previous asynchronous DFT. Based on A-SCAN, we propose the Asynchronous Built-in Self Test (A-BIST), which has no clock. Experimental results show that our BIST area and power overhead are 30% and 116% smaller than previous synchronous counterpart, respectively. Our test coverage is similar to that of ATPG. With A-SCAN and A-BIST, we can easily integrate synchronous and asynchronous testing on the same chip. [ABSTRACT FROM AUTHOR]

The IEEE Std. 1687 (IJTAG) facilitates access to on-chip instruments in complex system-on-chip designs. However, a major security vulnerability in IJTAG has yet to be addressed. IJTAG supports the integration of tapped and wrapped instruments at the IP provider with hidden test-data registers (TDRs). The instruments with hidden TDRs can alter and steal the data that is shifted through them. These attacks are called “data-alteration” and “data-sniffing” attacks, respectively. We propose the addition of shadow TDRs (STDRs) and information-flow tracking logic to protect the shifted in test data from illegitimate alteration and leakage by malicious third-party IPs. We present two security architectures for IJTAG. The first architecture secures the IJTAG against data alteration and incurs no timing overhead. However, it does not secure IJTAG against data-sniffing attacks (DS). The second architecture is an upgrade to the first architecture where we repurpose the use of the STDRs and information-tracking logic to secure the IJTAG against both data-alteration and DS. However, it incurs timing overhead. We present security proofs, simulation results, and the overheads associated with these countermeasures for various benchmarks. We also discuss the tradeoffs in security and overhead between the two proposed architectures. [ABSTRACT FROM AUTHOR]

Design solutions of domestic VLSI were obtained as a result of the application of computeraided design tools of a foreign supplier (CAD Synopsys, Cadence Design Systems and Mentor Graphics), based on standard libraries of PDK elements (Project Design KIT) of factories and IC-modules also supplied mainly by foreign companies. As a rule, the developer does not have its own production facilities, using the services provided by foreign factories (fablesscompanies). Due to this fact, relevant are the studies aimed at the development of a complex of measures, excluding the possibility of unauthorized changes into IC, i.e. protection of projects against intentional hardware and technology violations made during the formation of the control information for handing it over to the production facility and/or in case of IC manufacture at the factory. This paper considers this task from the standpoint of the analysis of the methodology of design for testability (DFT), i.e., a complex of measures that provide obtaining solutions at the design stage. The solutions include the verification of the correct performance of the manufactured chip by means of external tests and/or self-testing procedures. It was proposed, inter alia: 1) to analyze the libraries of standard elements used in the project with full disclosure of their specifications; 2) to create nodes with the physical non-cloning function in the projects on the basis of the libraries of standard elements in models and analysis programs; 3) to analyze IP modules used in the project with the maximum disclosure of structure, methods and algorithms for providing test coverings; 4) to provide for the development in projects of special test kits and methods of their generation at the design stage of functions in order to detect malicious nodes and programs both within SoC cores and at the level of system buses; 5) to develop at the design stage and to apply during tests a technique of special hardware measurements of parameters of the manufactured circuits and analysis of their results, inter alia, according to measurements of delays in distribution of signals and/or buses current consumption.

Cryptographic cores integrated with self-test ability fulfill both data security and reliability requirements of the Internet of Things (IoT) network. However, from the IoT perspective where most devices are resource constrained, a fundamental problem associated with most of the self-test architectures is high hardware overhead due to the additional circuit for self-test operation. This paper presents the design of a low-cost self-test architecture and its integration with the PRESENT cipher core. The hardware overhead of the proposed low-cost self-test architecture is reduced by adopting two key strategies: 1) using hardware-efficient X-Compactor technique for test response compaction and 2) reusing the PRESENT cipher core as a Test Pattern Generator (TPG). The proposed self-test architecture is implemented on different Xilinx Field Programmable Gate Array (FPGA) platforms and devices. Analysis of the implementation results shows that the proposed self-test method occupies 23% less hardware area overhead and provides 14% higher throughput per slice performance with the fault coverage of over 99% compared with the existing self-test designs. The resulting analysis indicates that the proposed self-test design is one of the most viable testing solutions for resource-constrained IoT devices.

Reversible circuits have been extensively investigated because of their applications in areas of quantum computing or low-power design. A reversible circuit is composed of only reversible gates and allow computations from primary inputs to primary outputs and vice-versa. In the last decades, synthesis of reversible circuits received significant interest. Additionally, testing of these kinds of circuits has been studied which included different fault models and test approaches dedicated for reversible circuits only. The analysis of testability issues in a reversible circuit commonly involves the detection of the missing gate faults that may occur during the physical realizations of the reversible gates. In this paper, we propose a design for testability (DFT) technique for reversible circuits in which the gates of a circuit are clustered into different sets and the gates from each cluster are then connected to an additional input line where, the additional line acts as an extra control input to the corresponding gate. Such arrangement makes it possible to achieve 100% fault detection in any reversible circuit with a small increase in quantum cost. Experimental evaluations confirm that the proposed DFT technique incurs less quantum cost overhead with 100% fault detection compared to existing DFT techniques for reversible circuits. [ABSTRACT FROM AUTHOR]

A built-in self-test (BIST) system with a 72-dB carrier-to-noise ratio (C/N) and less than 1-ppm frequency tolerance of down-converted BIST tone for a multi-channel radar application is presented. The BIST consists of a frequency doubler, an up-conversion mixer (UPMIX), a variable gain amplifier, a phase shifter, an eight-way splitter, and an RF PAD coupler for BIST signal distribution. The proposed BIST system can operate from 76 to 81 GHz, mixing with arbitrary offset frequencies from 600 kHz to 42.7 MHz generated by a fully-synchronized phase locked loop (PLL). The proposed UPMIX can generate zero or non-zero offset frequencies by switching between two modes flexibly implemented in the same layout area. The measured relative phase among all eight channels was less than 2° from −25 °C to 150 °C through on-chip 12-bit analog-to-digital converters (ADCs). The proposed BIST was fabricated using a 40-nm CMOS process and assembled with a wafer-level chip-sized package (WLCSP). Also, state-of-the-art BIST beamformer analyses were demonstrated as one of the future methods for self-diagnosis with a null-depth monitoring for a multi-channel radar application. [ABSTRACT FROM AUTHOR]

This article describes a defect-oriented test (DOT) approach, which enables a complete physical defect-based automatic test pattern generation (ATPG) for the digital logic area of CMOS-based designs. Total critical area (TCA)-based methods are presented for the generation of needed DOT views to enable the generation of complete DOT-based patterns for detecting all cell-internal and as well all cell-external physical defects. The major aim of these new methods and patterns is to further reduce the defect rate of manufactured ICs, in addition to what is already achieved with traditional and cell-aware test (CAT) fault models. We present test results, including achieved defect rate reduction in defective parts per million (DPPM), from a large 14-nm FinFET design, including a correlation to system-level-test (SLT) fails. For a second, mature 160-nm automotive mixed-signal sensor we present high-volume production test results, again measured in DPPM, and we provide test coverage figures moving away from counting detected faults to calculating detected TCA which is reported as the chip level TCA coverage. [ABSTRACT FROM AUTHOR]

As VLSI design moves into ultra-deep-submicron technologies, timing margins added to the clock period are mandatory, to ensure correct circuit behavior under worst-case conditions. Timing resilient architectures emerged as a promising solution to alleviate these worst-case timing margins. These architectures allow improving system performance and reducing energy consumption. Asynchronous systems, on the other hand, have the potential to improve energy efficiency and performance. Blade is an asynchronous timing resilient template that leverages the advantages of both asynchronous and timing resilient techniques. However, Blade still presents challenges regarding its testability, which hinders its commercial or large-scale application. This paper demonstrates that scan chains can be prohibitive for Blade due to their high silicon costs., which can reach more than 100%. Then, it proposes an alternative test approach that allows concurrent testing, stuck-at, and delay testing. The test approach is based on the reuse the Blade features to provide testability, with silicon area overheads between 4 and 7%. [ABSTRACT FROM AUTHOR]

This article presents a next-generation test data compression scheme. It builds on the isometric compression paradigm, but makes it more flexible and elevates encoding efficiency to values unachievable through state-of-the-art sequential compression schemes. Furthermore, its programmable selection of full-toggle scan chains ensures high test coverage and virtually eliminates compression aborts. The presented approach follows from a fundamental observation that among test cube care bits, only a very few have a status of necessary assignments (their locations cannot be changed), whereas the remaining ones have alternative sites. These test cubes are used to form circular test templates which synergistically control a decompressor and guide back ATPG to find assignments yielding highly compressible test patterns. A redesigned low-silicon-area decompressor is also capable of reducing switching rates in scan chains with a new test power control scheme. The experimental results obtained for large industrial designs and other benchmark circuits confirm the superiority of the proposed scheme over existing techniques and are reported herein. [ABSTRACT FROM AUTHOR]

This paper proposes a channel model to be applied to the communications systems of CubeSats. The model considers the low earth orbit geometry when a satellite is passing over a ground station, and the propagation surrounding multiple paths of the ground station location in urban areas. The geometry was used to define the deterministic factors, which contribute to the fading of the communication signal, such as Doppler effect and loss in free space. These are parameters that change as a function of time and elevation angle. Thus, a complete digital communication system, at the link layer level, is presented, using Markov Chains to model the previously cited effects in the form of a finite-state Markov channel. The proposed model was used as an uplink channel between a ground station and a CubeSat, both implementing a protocol stack, following the consultative committee for space data systems (CCSDS) recommendations. The ground station and the proposed communication channel were implemented through a functional simulation model and a telecommand and telemetry unit, implemented in hardware, was used as a case study for the CubeSat. Through the analysis of the simulated system, with telecommands sent by the station and responses sent by the hardware unit (in a hardware-in-the-loop setup), it was possible to demonstrate the operation of the proposed channel together with the retransmission mechanism suggested in the CCSDS recommendations, in order to mitigate communication issues. [ABSTRACT FROM AUTHOR]

In this brief, we first introduce a process-variation-aware test-point generation method. With this method, faults are not obscured by process variations and we are able to generate new test points by measuring a very limited number of current values on-chip and estimating values of the remaining currents. We furthermore introduce a multiple-fault diagnosis procedure where we use the process-variation aware test-point generation method. The proposed methods can also be used for structural test. For the application, we have used a thermometer coded current steering digital to analog converter, as they are widely used due to their suitability for high speed applications and the symmetric design is suitable for the application of our method. We introduce a design-for-test hardware for the diagnosis cost reduction, while implementing our methods. Experimental results show that parametric errors as small as 20% can be diagnosed with up to 97.8% accuracy.

Through-silicon vias (TSVs) technology has attracted industry interest as a way to achieve high bandwidth, and short interconnect delays in nanometer three-dimensional integrated circuits (3-D ICs). However, TSVs are critical elements susceptible to undergoing defects at steps, such as fabrication and bonding or during their lifetime. Resistive open defects have become one of the most frequent failure mechanisms affecting TSVs. They include microvoids, underfilling, misalignment, pinholes in the oxide, or misalignment during bonding, among others. Although considerable research effort has been made to improve the coverage of TSV testing, little attention has been paid to weak (resistive) open defects causing small delays. In this work, a postbond oscillation test strategy to detect such small delay defects is proposed. Variations in the duty cycle of transmitted signals after unbalanced logic gates are shown to help in the detection of weak open defects in TSVs. HSPICE simulations, including process parameter variations, have been considered, and results show the effectiveness of the method in the detection of weak open defects above 1 $\text{k}\Omega $. Experimental work on a 65-nm IC also corroborates the detection capability of the proposal. [ABSTRACT FROM AUTHOR]

Memristor is an attractive candidate to replace the present computation and storage devices due to its novel features namely nanoscale size, low power, non-volatility, high compatibility with CMOS, and multi-bit operations. However, the memristor memories need to overcome the design challenges such as process variations, non-deterministic switching characteristics, and unreliable operation. This study suggests a built-in self-configurable architecture to detect the weak (unstable) cells of the memristor-based memories. The proposed techniques were validated by "voltage threshold adaptive memristor" (VTEAM) model by injecting various resistive faults. Additionally, this study presents the necessary mathematical analysis for the methodology. The results confirm that the investigated architecture is capable to differentiate unstable and stable memory cell. [ABSTRACT FROM AUTHOR]

High-Level Synthesis (HLS) provides a simple way to implement complex applications using Field Programmable Gate Array (FPGA) devices. Unfortunately, this technology introduces non-negligible problems related to verification: speed, accuracy and behavior mismatch between co-simulation and implementation. This paper presents RC-Unity , a heterogeneous unit testing framework that integrates FPGA-in-the-loop devices in order to extend the scope and capabilities of current HLS tools. Verification engineers can focus on the design of the tests while the framework automates the generation of the underlying verification infrastructure, making the testbed reusable across different stages of the design flow as the experiments show. • Simplification of the pre-silicon verification activities by a single test suite across the different flow stages. • A hardware testing framework that enables the grey-box verification strategy. • Bring closer some parameters from the physical dimension into the verification flow. • A library of verification overlays that can be customized at run-time. • A remote testing mode that offers the library of verification overlays and the testing framework as a service. [ABSTRACT FROM AUTHOR]

A concurrent error detectable adder with easy testability is proposed. The proposed adder is based on a multi-block carry select adder. Any erroneous output of the adder caused by a fault modeled as a single stuck-at fault can be detected by comparing the predicted parity of the sum with the parity of the sum, i.e., the XORed value of the sum bits, and comparing the duplicated carry outputs. The adder is also testable with only 10 input patterns under single stuck-at fault model. This property eases detection of a fault before the occurrence of a second fault. Both the concurrent error detectability to detect erroneous results and the easy testability to find a fault during operation are important for realizing reliable systems. Both the concurrent error detectability and the easy testability of the proposed adder are proven. A 32-bit adder has been designed. Its hardware overhead is about 70 percent. Its concurrent error detectability and 100 percent test coverage through the 10 patterns has been confirmed by fault simulation. [ABSTRACT FROM AUTHOR]

Process control and yield of spin torque transfer-magnetoresistive random access memory (STT-MRAM) array are of crucial importance in fabrication. While yield depends on the CMOS process variability, quality of the deposited MTJ film, and other process nonidealities, test platform can enable a parametric optimization and verification process using the CMOS-based design-for-testability (DFT) circuits. In this paper, we develop a DFT algorithm and implement a DFT circuit for parametric testing and prequalification of the critical circuits in the CMOS wafer. The DFT circuit successfully replicates the electrical characteristics of MTJ devices and captures their spatial variation across the wafer with an error of less than 4%. We estimate the yield of the read sensing path by implementing the DFT circuit, which can replicate the resistance-area product variation up to 50% from its nominal value. The yield data from the read sensing path at different wafer locations are analyzed, and a usable wafer radius up to 75 mm has been estimated. Our DFT scheme can provide quantitative feedback based on in-die measurement, enabling fabrication process optimization through iterative estimation and verification of the calibrated parameters. [ABSTRACT FROM AUTHOR]

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Logic built-in self-test (LBIST) is now increasingly used with on-chip test compression as a complementary solution for in-system test, where high quality, low power, low silicon area, and most importantly short test application time are key factors affecting ICs targeted for safety-critical systems. Test points, common in LBIST-ready designs, can help to reduce test time and the overall silicon overhead so that one can get desired test coverage with the minimal number of patterns. Typically, LBIST test points are dysfunctional when enabled in an ATPG-based test compression mode. Similarly, test points used to reduce ATPG pattern counts (PCs) cannot guarantee desired random testability. In this paper, we present a hybrid test point technology designed to reduce deterministic PCs and to improve fault detection likelihood by means of the same minimal set of test points. The hybrid test points are subsequently deployed in a scan-based LBIST scheme addressing stringent test requirements of certain application domains such as the automotive electronics market. These requirements, largely driven by safety standards, are met by significantly reducing test application time while preserving the high fault coverage. The new scheme is a combination of pseudorandom test patterns delivered in a test-per-clock fashion through conventional scan chains and per-cycle-driven hybrid observation test points that capture faulty effects every shift cycle into dedicated scan chains. Their content is gradually shifted into a compactor shared with the remaining chains that deliver responses once a test pattern has been shifted-in. Experimental results obtained for industrial designs confirm feasibility of the new schemes, and they are reported herein. [ABSTRACT FROM AUTHOR]

Since the VLSI chips were invented, as predicted by Moore’s law, the performance, the power, and the cost of the VLSI chips have been improved, which brought a significant benefit to the economy. However, some of the analog circuits do not get a full benefit from the scaling, due to the increased device variability with transistors in smaller dimension. Under such circumstance, the calibration and trimming techniques are essential to overcome the sensitivity to the process variation. This paper presents the trimming technique to correct the direct current (dc) offset error of the bandgap voltage reference circuit, which complies with the high-volume manufacturing (HVM) requirements. The proposed trimming method consists of the combination of two different sequences, the coarse and fine trimming. The accuracy of the dc offset trimming is evaluated by the newly invented method that complies with the HVM requirements. With a compact silicon area of only 700 $\mu \text{m}^{2}$ , the dc offset trimming circuit achieved an accuracy of ±5 mV ($4\sigma$) as a result of the coarse and fine trimming operations. [ABSTRACT FROM AUTHOR]

Testability dramatically enhances the operating cost in reversible logic circuits as it increases the cost metrics such as gate count, quantum cost, number of wires and garbage output. This increase also affects the utilization of resources, which further enhances overall cost of testing. This paper presents a new design for testability methodology for reversible circuits by exploring the properties of multiple controlled Toffoli and Fredkin gates, to produce online testable circuits at lower cost metrics. The method includes simplification and modification of Toffoli circuits to form parity-preserving Toffoli–Fredkin cascades. The testability in these cascades can be achieved by comparing the parity of inputs and outputs using controlled-NOT gates on an additional wire. Single-point failures in reversible logic circuits are targeted by means of detecting bit faults. In contrast to the existing work, the present model is robust, low cost and has lesser design complexity. Experiments are conducted on a set of benchmark circuits to prove the efficacy of the present work. The results show an average reduction by 15.9 % in gate cost and 11.0 % in total operating cost when compared to the most recent existing work formulated on the same platform. [ABSTRACT FROM AUTHOR]

Abstract Array Signal Processor (ASP) is widely used in antenna-array beamforming applications, such as RADAR, SONAR, Medical Ultrasound, Multiple-Input-Multiple-Output (MIMO) etc. In this paper, architecture and Field Programmable Gate Array (FPGA) Prototype of a Cycle Steeling Direct Memory Access (DMA) Digital Beamformer (DBF) for Ultrasound Sector Imaging Systems is proposed. The architecture is based on delay and sum and it requires Fine Delay (FD) and Coarse Delay (CD) values to steer and dynamically focus the array, and apodization weights to improve the directivity. To improve the Fine delay accuracy Minimum Mean Square Error (MMSE) interpolation filter is proposed and implemented. To support wide Field of View (FOV) steering, immense delay values are required and real-time computations are hard for high sampling rate systems. Also, the precomputed delay values require huge memory, which causes a significant increase in the ASP area. To solve this problem, a cycle stealing DMA controller based on Quad Serial Peripheral (QSPI) interface to load delay values from external flash without disturbing ASP processing has been proposed and realized. Moreover, for debuggability,the architecture supports custom JTAG debug interface logic and lock-up latch based Design for Testability (DFT) Scan chain for multiple clock domains. The paper also presents the design and implementation of an Ultrasound Sector Imaging System Prototype setup to emulate the ASP. Most of the existing research work in this area supports ultrasound echo acquisition to PC and processing. However, the designed prototype helps researchers to validate computationally complex Ultrasound signal processing algorithms like ASP on FPGA and further processing on PC. [ABSTRACT FROM AUTHOR]

Growing reverse-engineering attempts to steal or violate a design intellectual property (IP), or to identify the device technology in order to counterfeit integrated circuits (ICs), raise serious concerns in the IC design community. As the information derived from these practices can be used in a number of malicious ways, various active techniques have been proposed and deployed to protect IP, of which logic locking is a vital part. It allows inserting certain gates in a circuit’s data path to lock outputs to fixed logic values, if a wrong unlocking key is applied. This paper demonstrates that test points—industry-proven design-for-test technology used primarily to enhance the overall design testability–can also be reused in the mission mode to lock the circuit, and thus to improve the hardware security against IP piracy. In particular, it is shown that test points can facilitate the hiding of design functionality from adversaries. As a result, not only is the overall design testability improved, but also effective protection against piracy through unauthorized excess production and other forms of IP theft is ensured. Experimental results on industrial designs with test points demonstrate that the proposed scheme is effective in achieving a desired degree of hardware obfuscation. [ABSTRACT FROM AUTHOR]