Back to Search Start Over

Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits.

Authors :
Chen, Tsai-Chieh
Pai, Chia-Cheng
Hsieh, Yi-Zhan
Tseng, Hsiao-Yin
Chien-Mo, James
Liu, Tsung-Te
Chiu, I-Wei
Source :
Journal of Electronic Testing. Aug2021, Vol. 37 Issue 4, p453-471. 19p.
Publication Year :
2021

Abstract

It is a real challenge to test asynchronous circuits since there is no clock signal, and there are many non-scan state-holding elements. In this paper, we first propose an Asynchronous Circuit Scan (A-SCAN) latch, which can flip between Valid and Empty states so that we can shift in and out without any clock. Experimental results show that our DFT area and power overhead are 28% and 104% smaller than previous synchronous DFT, respectively. The timing overhead of DFT is nearly two times smaller than previous asynchronous DFT. Based on A-SCAN, we propose the Asynchronous Built-in Self Test (A-BIST), which has no clock. Experimental results show that our BIST area and power overhead are 30% and 116% smaller than previous synchronous counterpart, respectively. Our test coverage is similar to that of ATPG. With A-SCAN and A-BIST, we can easily integrate synchronous and asynchronous testing on the same chip. [ABSTRACT FROM AUTHOR]

Subjects

Subjects :
*ASYNCHRONOUS circuits
*SELF

Details

Language :
English
ISSN :
09238174
Volume :
37
Issue :
4
Database :
Academic Search Index
Journal :
Journal of Electronic Testing
Publication Type :
Academic Journal
Accession number :
153556833
Full Text :
https://doi.org/10.1007/s10836-021-05963-z