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In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased W eff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported at L g =12nm and aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules. We demonstrate work function metal (WFM) replacement and multiple threshold voltages, compatible with aggressive sheet to sheet spacing for wide stacked sheets. Stiction of sheets in long-channel devices is eliminated. Dielectric isolation is shown on standard bulk substrate for sub-sheet leakage control. Wrap-around contact (WAC) is evaluated for extrinsic resistance reduction.

CVD-Ru represents a critically important class of materials for BEOL interconnects that provides Cu reflow capability. The results reported here include superior gap-fill performance, a solution for plausible integration issues, and robust EM / TDDB properties of CVD-Ru / Cu reflow scheme, by iterative optimization of process parameters, understanding of associated Cu void generation mechanism, and reliability failure analysis, thereby demonstrating SRAM operation at 10 nm node logic device and suggesting its use for future BEOL interconnect scheme.

We fabricated firstly body-tied triple-gate NMOSFETs that have fin top width of 30 nm, fin bottom width of 61 nm, fin height of 99 nm, and gate length of 116 nm. Fabrication process steps of the devices are compatible with that of conventional bulk planar channel MOSFET technology and explained in detail in this paper. This MOSFET shows excellent transistor characteristics, such as very low subthreshold swing, Drain Induced Barrier Lowering (DIBL) of 24 mV/V, almost no body bias effect, and orders of magnitude lower I SUB / I D than planar channel DRAM cell transistors. By optimizing process further, it is expected that cost effective body-tied triple-gate MOSFETs can be applied to real Integrated Circuits (ICs).

This paper describes thermal desorption silicon etching (TDSE)/channel-epi transistor, which has improved the profile and the electrical characteristics of channel-epi transistor. Thermal desorption silicon etching (TDSE) process is introduced before Si channel-epi growth using ultrahigh vacuum system to improve transistor performance at dynamic random access memory (DRAM) device. TDSE process for etching active silicon was carried out using Cl2 gas at 700°C in UHV chamber. Following the TDSE process, in-situ Si channel-epi was grown at the same chamber. We evaluated the electrical characteristics of TDSE/channel-epi transistor, and also measured the reliability of gate oxide. Compared with the conventional channel-epi which shows the degradation of transistor characteristics due to the raised active profile, TDSE process with channel-epi presents superior transistor performance in terms of transistor hump characteristics and inverse narrow width effect (INWE). TDSE induced interface and junction leakages, however, are observed. To solve these problems, H2 added TDSE process or H2 anneal process after TDSE has been developed.

A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um 2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limit. Multi-workfunction (WF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by channel dopants.

It is possible to overcome Cu void issues beyond 10nm node device by adapting CVD-Ru liner instead of conventional PVD Ta liner. However, CVD Ru liner integration degrades TDDB performance without optimizing its scheme. In this paper, superior gap-fill performance without TDDB performance degradation will be described in our optimized integration scheme along with a proposal for the mechanism of TDDB degradation in the Ru integration scheme. CVD-Ru liner is the prime candidate for Cu metallization at 10nm node and beyond.

Ion implantation into amorphous carbon has been initiated to investigate the possibility of superhard carbon-nitride formation. Studies of implantation-temperature effects by 100 keV N+ or 80 keV C+ ions at 50 μA show a narrow temperature window at approximately −100 °C for the optimum surface hardness and elastic modulus (measured by nanoindentation), both values much higher than those for the unimplanted amorphous carbon. No distinguishable properties are found between nitrogen and self (carbon) implantations. At a dose rate of 5 μA, however, the optimum hardness and modulus are found at a lower implantation temperature, with a broader temperature window. The enhanced strengths are well correlated with the asymmetric diffuse peak at around 1500 cm−1 in Raman spectroscopy, and the increased ratio of sp3- over sp2-bonded carbon sites observed by electron energy loss spectroscopy.

This paper describes SRAM scaling for 32 nm low power bulk technology, enabled by high-K metal gate process, down to 0.149 mum2 and 0.124 mum2. SRAM access stability and write margin are significantly improved through a 50% Vt mismatch reduction, thanks to HK-MG Tinv scaling. Cell read current is increased by 70% over Poly-SiON process. Ultra dense cell process window is expanded with optimized contact process. A dual-ground write assist option can additionally enable ultra dense 0.124 mum2 cell to meet low power application requirements.

FinFET, the milestone for sub-50 nm DRAM cell transistor has been successfully demonstrated by a unique fabricating method with novel concept. We obtained a core solution of front-end-of-line process and structure, focusing on short channel behavior, off-state leakage, and saturation current. We have developed the scheme that is able to suppress off-state leakage current below 1 fA/cell with p+ poly-Si gate. We have also examined mobility and parasitic engineering techniques to maximize the cell performance (DeltaIon > 48 %). In conclusion, we propose the effective guideline for highly manufacturable FinFET for DRAM application at the sub-50 nm node.

We demonstrate a highly manufacturable substrate-induced strained Si device, which is compatible with the conventional Si bulk process. It utilizes ultra-thick-strained Si (UTSS) layer thicker than 3000 /spl Aring/ and relaxed SiGe layer with low Ge content less than 10%. The UTSS n-MOSFET gives 6 /spl sim/ 12% increase in I/sub on/ according to the gate length without the cost of increase in I/sub off/. In addition, more than 5% increase in I/sub on/ for p-MOSFET can be obtained by hybrid stress of UTSS and SiGe source/drain process. We also emphasize the importance of the ratio of channel resistance (R/sub CH/) to source-drain resistance (R/sub SD/) for performance enhancement.

Nano scale body-tied FinFETs have been firstly fabricated. They have fin top width of 30 nm, fin bottom width of 61 nm, fin height of 99 nm, and gate length of 60 nm. This Omega MOSFET shows excellent transistor characteristics, such as very low subthreshold swing, Drain Induced Barrier Lowering (DIBL) of 24 mV/V, almost no body bias effect, and orders of magnitude lower I/sub SUB//I/sub D/ than planar type DRAM cell transistors.

Fully metal embedded cell technologies, including poly-Si/W/sub x/N/W gate, Co salicide with elevated source/drain using UHV-selective epitaxial growth and CVD-W cell pad has been integrated successfully for the first time for 100 nm design rule DRAM devices. Each key technology exhibits excellent performance.

Manufacturable embedded CMOS 6T-SRAM with the HfO/sub 2/-Al/sub 2/O/sub 3/ dielectric for system-on-chip (SoC) applications is successfully demonstrated for the first time in the semiconductor industry. The possibility of the high-k gate dielectric in low power SoC applications is suggested. 0.11/spl mu/m NFET and PFET devices with thin high-k gate dielectric have 470 and 150/spl mu/A//spl mu/m at Ioff=0.1nA/um and Vdd=1.2V, respectively. Inversion thickness of NFET and PFET are 2.4nm and 2.7nm, respectively. Gate leakage current of the high-k is 1000 times lower than that of the oxynitride at the accumulation region. Static noise margin of 2.14/spl mu/m/sup 2/ 6T-SRAM bit cell is about 300mV at Vdd=1.2V. 6T-SRAM chip yield of the high-k is comparable to that of the oxynitride. The post nitridation after high-k film deposition is very important to the yield of the SRAM chips due to the suppression of the PFET boron penetration. Stand-by current of the SRAM chips with the high-k is shown to be a decreases of 60% compared with the oxynitride.

A 90 nm generation logic technology with Cu/low-k interconnects is reported. 50 nm transistors are employed using gate oxide 1.3 nm in thickness and operating at 1.0 V. High speed transistors have drive currents of 870 /spl mu/A/pm and 360 /spl mu/A//spl mu/m for NMOS and PMOS respectively, while generic transistors have currents of 640 /spl mu/A//spl mu/m and 260 /spl mu/A//spl mu/m respectively. Low power process using high-k gate dielectrics and SOI process are also provided in this technology. The low-k SiOC material with 2.9 in the k value is used for 9 layers of dual damascene Cu/low-k interconnects. The effective k (k/sub eff/) value of interconnect is about 3.6. Fully working 6-T SRAM cell with an area of 1.1 /spl mu/m/sup 2/ and SNM value of 330 mV is obtained. For MIM capacitor, voltage coefficient of capacitance is less than 20 ppm/V.

With W/TiN stack gate deposited at high temperature, excellent time-dependent dielectric breakdown (TDDB) characteristics of the gate oxide were obtained in MOS capacitors. In the case of negative gate bias where thin oxide reliability becomes critical, the TiN gate provides a much longer time to breakdown than that of n/sup +/-poly gate due to a larger barrier height and less F-N tunneling current. In spite of skipping the conventional reoxidation process, a breakdown field larger than 10 MV/cm could be obtained in MOS transistors by undercutting TiN with boiling H/sub 2/SO/sub 4/. With a double spacer and undercutting scheme, the short channel effect of NMOS and PMOS transistors could be suppressed up to L/sub gate//spl sim/0.3 /spl mu/m.

W/TiN stack gate has been investigated as a new gate electrode in ULSI CMOSFETs. With the combination of low resistivity of W and Si-midgap workfunction of TiN, very low sheet resistance and the proper characteristics of both types of transistors could be obtained simultaneously. With the deposition of TiN film at high substrate temperature, the breakdown characteristics of gate oxide could be improved considerably. The proper condition of dry etching on this structure has been also obtained.

This study is aimed at making index with series of experiments in order to adjust the change occurring by an area effect in architectural color design. The basic experiment was performed to find the change of color regularly in the condition of fixing regular area and viewpoint.

Los Alamos National Laboratory is actively researching a surface modification technique called plasma immersion ion processing (PIIP). PIIP is the latest innovation of the plasma source ion implantation (PSII) approach to surface modification. Like PSII, PIIP allows the modification of large areas and non-planar surface geometries, however PIIP is primarily a coating deposition technology rather than solely an ion implantation technology. PIIP utilizes a pulsed-bias on a target to extract ions out of plasma for ion implantation and coating deposition. Plasmas can be made by capacitive or inductive radio frequency sources or by initiating a glow discharge during each pulse of high voltage. Plasmas of hydrocarbon gases have been used to deposit adherent diamond-like carbon (DLC) coating son a variety of ferrous and non-ferrous materials. Instead of sputter depositing interlayers to improve the adhesion of DLC, PIIP uses ion implantation to create a graded interface between the metallic substrate and the DLC coating. Demonstrating the scaleability of PIIP, a 3 m2 area has been simultaneously coated with an adherent DLC coating approximately 7 micrometers thick. Plasmas of diborane and acetylene mixtures are being used to develop deposition processes for boron-carbide coatings. Through the use of organometallics and inorganic gases, other coatings are possible. The PIIP deposition conditions, composition and tribological properties of DLC and boron-carbide coatings will be highlighted.© (1998) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

We investigated the formation and thermal stability of Co-silicide films using Co–Ta alloy films on (100) Si substrates. Co–Ta alloy films were deposited by direct current (DC) magnetron sputtering using Co and Ta targets. The content of Ta in the films was controlled at 8 at.%. The Co-silicide films were formed through a rapid thermal annealing (RTA) process in N2 ambient. Compared with the Co/Si systems, the formation of CoSi2 occurs at higher temperatures in Co0.92Ta0.08/Si systems. X-Ray diffractometry (XRD) analyses showed the presence of strong (200)-preferred orientation in the Co-silicide films formed from Co0.92Ta0.08/Si systems. We observed that Co-silicide films formed from Co0.92Ta0.08/Si systems maintained low sheet resistance values upon annealing at 950°C, while those of Co-silicide from Co/Si systems increased significantly. The improvement of the thermal stability of the Co-silicide films from Co0.92Ta0.08/Si systems is due to the formation of Ta-compounds such as the TaSi2 phase at the grain boundaries or at the surface of the CoSi2 films.