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Further miniaturization of complementary metal oxide semiconductor devices based on impurity‐doped semiconductors is limited due to statistical fluctuation of the impurity concentration in very small volumes and dopant deactivation, increasing the resistance and power consumption. Based on density functional theory calculations and backed by experimental data, the nanoscale electronic structure shift induced by anions at surfaces (NESSIAS) has been described recently. It explains the structure shift of low‐doped single‐crystalline Si nanowells (Si‐NWs) with thicknesses ≤3 nm embedded in SiO2 (Si3N4) toward n‐type (p‐type) behavior. The influence of the anions is on the scale of a few nanometers, allowing for very steep p–n junctions without the drawbacks of impurity doping. The process to fabricate crystalline silicon (c‐Si) NWs embedded in SiO2 and Si3N4, starting with silicon on insulator (SOI) across 15 × 15 mm2 samples, is described. Four possible methods to fabricate Si‐NWs by thinning down single‐crystalline top‐Si of an SOI substrate are evaluated in terms of reproducibility and surface roughness. [ABSTRACT FROM AUTHOR]

Abstract During deep reactive ion etching (DRIE), microscale etch masks with small opening such as trenches or holes suffer from limited aspect ratio because diffusion of reactive ions and free radicals become progressively difficult as the number of DRIE cycle increases. For this reason, high aspect ratio structures of microscale trenches or holes are not readily available with standard DRIE recipes and microscale holes are more problematic than trenches due to omnidirectional confinement. In this letter, we propose an optimization for fabrication of high aspect ratio microscale hole arrays with an improved cross-sectional etch profile. Bias voltage and inductively coupled plasma power are considered as optimization parameters to promote the bottom etching of the high aspect ratio hole array. In addition, flow rates of octafluorocyclobutane (C $$_{4}$$ 4 F $$_{8}$$ 8 ) and sulfur hexafluoride (SF $$_{6}$$ 6 ) for passivation and depassivation steps, respectively, are considered as optimization parameters to reduce the etch undercut. As a result of optimization, the aspect ratio of 20 is achieved for 1.3 μm-diameter hole array and etch area reduction at the bottom relative to the top is improved to 21%.

• Flat oxide layers are fabricated on silicon substrates by seed-guided laser processing. • Defect is firstly generated on silicon substrate, function as a high optical absorption. • Laser oxidation mechanisms are analyzed to tune the oxide layer morphology. • The flat oxide layers serve as an etch stop layers. • Three-dimensional silicon gratings are fabricated by deep reactive ion etching. Laser oxidation provides a flexible maskless functional three-dimensional silicon structure fabrication strategy. Here, oxide layers are fabricated on silicon substrates by high-repetition-rate femtosecond laser irradiation. Formation mechanisms of the femtosecond laser oxidation are analyzed to tune the oxide layer morphology. When the laser fluence is high, the oxidation process is accompanied by laser ablation, so the oxide layer is always on top of laser ablated groove. To obtain the flat oxide layer, defect is firstly generated on silicon substrate by the laser irradiation at a high laser fluence of 126 mJ/cm2, function as a high optical absorption. It is called seed as it can assist to achieve lower fluence laser oxidation at 38 mJ/cm2 and result in a flat oxide layer. Full width at half-maximum of the oxide layer is also reduced. The laser fabricated oxide layers are used as etching masks. Three-dimensional silicon gratings are fabricated by deep reactive ion etching, which demonstrate desirable beam diffraction properties. [ABSTRACT FROM AUTHOR]

Abstract Out-of-plane microneedle structures are widely used in various applications such as transcutaneous drug delivery and neural signal recording for brain machine interface. This work presents a novel but simple method to fabricate high-density silicon (Si) microneedle arrays with various heights and diverse cross-sectional shapes depending on photomask pattern designs. The proposed fabrication method is composed of a single photolithography and two subsequent deep reactive ion etching (DRIE) steps. First, a photoresist layer was patterned on a Si substrate to define areas to be etched, which will eventually determine the final location and shape of each individual microneedle. Then, the 1st DRIE step created deep trenches with a highly anisotropic etching of the Si substrate. Subsequently, the photoresist was removed for more isotropic etching; the 2nd DRIE isolated and sharpened microneedles from the predefined trench structures. Depending on diverse photomask designs, the 2nd DRIE formed arrays of microneedles that have various height distributions, as well as diverse cross-sectional shapes across the substrate. With these simple steps, high-aspect ratio microneedles were created in the high density of up to 625 microneedles mm−2 on a Si wafer. Insertion tests showed a small force as low as ~ 172 µN/microneedle is required for microneedle arrays to penetrate the dura mater of a mouse brain. To demonstrate a feasibility of drug delivery application, we also implemented silk microneedle arrays using molding processes. The fabrication method of the present study is expected to be broadly applicable to create microneedle structures for drug delivery, neuroprosthetic devices, and so on.

During deep reactive ion etching (DRIE), microscale etch masks with small opening such as trenches or holes suffer from limited aspect ratio because diffusion of reactive ions and free radicals become progressively difficult as the number of DRIE cycle increases. For this reason, high aspect ratio structures of microscale trenches or holes are not readily available with standard DRIE recipes and microscale holes are more problematic than trenches due to omnidirectional confinement. In this letter, we propose an optimization for fabrication of high aspect ratio microscale hole arrays with an improved cross-sectional etch profile. Bias voltage and inductively coupled plasma power are considered as optimization parameters to promote the bottom etching of the high aspect ratio hole array. In addition, flow rates of octafluorocyclobutane (C 4 F 8 ) and sulfur hexafluoride (SF 6 ) for passivation and depassivation steps, respectively, are considered as optimization parameters to reduce the etch undercut. As a result of optimization, the aspect ratio of 20 is achieved for 1.3 μm-diameter hole array and etch area reduction at the bottom relative to the top is improved to 21%. [ABSTRACT FROM AUTHOR]

This paper presents a novel dielectric waveguide based G-band interconnect. By using a new transition of microstrip line to dielectric waveguide, the interconnect achieves low insertion loss and wide bandwidth. The measured minimum insertion loss is 4.9 dB with 9.7 GHz 1-dB bandwidth. Besides, the structure is based on standard micromachined processing and easy to integrate with conventional packaging.

The etching of high aspect ratio structures in silicon via the Bosch process is essential in modern technologies such as microelectromechanical systems (MEMS) and through‑silicon vias (TSV) fabrication. The process can be very demanding on the mask selectivity due to long etching times, and it has been shown that an Al2O3 hard mask is very suitable in this regard, as it offers significantly higher selectivity compared to the conventional SiO2 or resist masks. In this work, we employ a combination of Scanning Electron Microscopy (SEM), Spectroscopic Ellipsometry (SE) and X-Ray Photoelectron Spectroscopy (XPS) depth profiling to scrutinize the Al2O3 mask etching mechanism and therefore the origin of the extraordinary high selectivity. We demonstrate that by increasing the passivation step time, a thicker fluorocarbon polymer layer is formed on the Al2O3, and Al2O3 is then removed with a minuscule average etch rate of ~0.01 nm/min. XPS depth profiling reveals that during Deep Reactive Ion Etching (DRIE) using the Bosch process, an AlFx layer is formed between the polymer and Al2O3. As AlFx is non-volatile, it requires sputtering to be removed. If the polymer layer is thick enough to attenuate the incoming ions such that their energy is not sufficient to lead to desorption of AlFx, such as when using a longer passivation time, the mask is not eroded. By investigating the surface after different amounts of DRIE cycles, we also obtained information about the formation rate of AlFx and the changes in the Al2O3 and polymer thicknesses over the course of a DRIE process. These findings further expand the knowledge of DRIE and can help process engineers to tailor the processes accordingly.

We report a scalable and cost-effective fabrication approach for constructing bio-inspired micro/nanostructured surfaces. It involves silicon microstructure etching using a deep reactive ion etch (DRIE) method, nanowires deposition via glancing angle deposition (GLAD) process, and fluorocarbon thin film deposition. Compared with the smooth, microstructured, and nanostructured surfaces, the hierarchical micro/nanostructured surfaces obtained via this method showed the highest water contact angle of ∼161° and a low sliding angle of

Highlights: High-density out-of-plane microneedle arrays were fabricated with a single photolithography and two deep reactive ion etching (DRIE) steps in anisotropic and isotropic modes, respectively. Microneedles in various heights were monolithically created by the identical DRIE processes and scanning electron microscopy images showed extremely sharp sub-micron (~145-nm-wide) tip. Diverse cross-sectional shapes of microneedles were implemented by altering photomask patterns. Out-of-plane microneedle structures are widely used in various applications such as transcutaneous drug delivery and neural signal recording for brain machine interface. This work presents a novel but simple method to fabricate high-density silicon (Si) microneedle arrays with various heights and diverse cross-sectional shapes depending on photomask pattern designs. The proposed fabrication method is composed of a single photolithography and two subsequent deep reactive ion etching (DRIE) steps. First, a photoresist layer was patterned on a Si substrate to define areas to be etched, which will eventually determine the final location and shape of each individual microneedle. Then, the 1st DRIE step created deep trenches with a highly anisotropic etching of the Si substrate. Subsequently, the photoresist was removed for more isotropic etching; the 2nd DRIE isolated and sharpened microneedles from the predefined trench structures. Depending on diverse photomask designs, the 2nd DRIE formed arrays of microneedles that have various height distributions, as well as diverse cross-sectional shapes across the substrate. With these simple steps, high-aspect ratio microneedles were created in the high density of up to 625 microneedles mm−2 on a Si wafer. Insertion tests showed a small force as low as ~ 172 µN/microneedle is required for microneedle arrays to penetrate the dura mater of a mouse brain. To demonstrate a feasibility of drug delivery application, we also implemented silk microneedle arrays using molding processes. The fabrication method of the present study is expected to be broadly applicable to create microneedle structures for drug delivery, neuroprosthetic devices, and so on. [ABSTRACT FROM AUTHOR]

Deep reactive ion etching (DRIE) technology is one of the most important technologies in the processing of microelectronic devices and microelectromechanical system. As a necessary process in semiconductor integration, it has been widely studied in the past decades. It is known that the traditional DRIE process typically uses a plasma etching reactor equipped with inductively coupled plasma (ICP) sources to generate a high-density plasma so as to achieve high aspect ratio trenches with relatively small roughness. A cryogenic temperature control unit is typically employed as well. Here, however, we use a parallel plate RIE with rather simple structure, which is not usually used for DRIE, to obtain high aspect ratio silicon etching. With no ICP sources and no sophisticated temperature control unit, the system and experiment are now much more cost effective. Through the optimization of the processing, the etching rate of silicon can reach 440 nm/min. Finally, a 45 μm deep trench is etched in silicon with good perpendicularity. This method will greatly reduce the equipment related cost, especially for those applications that do not have extremely stringent requirement on the final etching accuracy. [ABSTRACT FROM AUTHOR]

Future instruments employing cryogenic detectors for millimeter and submillimeter astronomy applications can benefit greatly from silicon vacuum windows with broadband antireflection treatment. Silicon is an ideal optical material at these wavelengths due to numerous attractive properties, including low loss, high refractive index, and high strength. However, its high index ( n = 3.4 ) necessitates antireflection (AR) treatment, which has proven a major challenge, especially for the multilayer treatments required for wide spectral bandwidths. We address this challenge by developing a wide-bandwidth integral AR structure for silicon vacuum windows using a novel fabrication technique, tuning the effective refractive index of each AR layer using deep reactive ion etching (DRIE) and using wafer bonding to assemble the structure. We present the progress we have made in designing and fabricating such vacuum windows from 100-mm-diameter silicon wafers. We have previously demonstrated a two-layer AR structure for windows over a 1.6:1 bandwidth and are currently fabricating a four-layer coating designed for a 4:1 bandwidth. We have also converged on a design for a six-layer structure optimized to give − 20 dB reflection between 80 and 420 GHz (5.25:1 bandwidth), which will be useful for future multicolor Sunyaev–Zel'dovich (SZ) observations. [ABSTRACT FROM AUTHOR]

The Fraunhofer IMS has recently developed a technique for producing nanoelectrodes that are generated by atomic layer deposition (ALD) in a via deep reactive ion etching (DRIE) structured sacrificial layer. This method enables the fabrication of CMOS- and biocompatible nanoelectrodes with suitable ALD-materials. Improvements of the established fabrication processes and the electrochemical characterization of such electrodes are presented. In the frame of the Fraunhofer-Max-Planckcooperation project ZellMOS different types of nanoelectrodes are studied. Their diameter is in the range of 200 nm and thereby sufficiently small to be taken up by living cells. In addition, the electrodes are mechanically enforced by an oxide layer at the nanoelectrodes’ bottom.

Infrared (IR) imaging devices that convert IR irradiation (invisible to the human eye) to a visible signal are based on solid-state components. Here, we introduce an alternative concept based on light-addressable electrochemistry (i.e., electrochemistry spatially confined under the action of a light stimulus) that involves the use of a liquid electrolyte. In this method, the projection of a near-IR image (λ exc = 850 or 840 nm) onto a photoactive Si-based photoanode, immersed into a liquid phase, triggers locally the photoinduced electrochemiluminescence (PECL) of the efficient [Ru(bpy) 3 ] 2+ -TPrA system. This leads to the local conversion of near-IR light to visible (λ PECL = 632 nm) light. We demonstrate that compared to planar Si photoanodes, the use of a micropillar Si array leads to a large enhancement of local light generation and considerably improves the resolution of the PECL image by preventing photogenerated minority carriers from diffusing laterally. These results are important for the design of original light conversion devices and can lead to important applications in photothermal imaging and analytical chemistry.

We present a method to produce small pitch gratings for X-ray interferometric imaging applications, allowing the phase sensitivity to be increased and/or the length of the laboratory setup to be minimized. The method is based on fabrication of high aspect ratio silicon microstructures using deep reactive ion etching (Bosch technique) of dense grating arrays and followed by conformal electroplating of Au. We demonstrated that low resistivity Si substrates (

Deep reactive ion etching (DRIE) with the Bosch process is one of the key procedures used to manufacture micron-sized structures for MEMS and microfluidic applications in silicon and, hence, of increasing importance for miniaturisation in biomedical research. While guaranteeing high aspect ratio structures and providing high design flexibility, the etching procedure suffers from reactive ion etching lag and often relies on complex oxide masks to enable deep etching. The reactive ion etching lag, leading to reduced etch depths for features exceeding an aspect ratio of 1:1, typically causes a height difference of above 10% for structures with aspect ratios ranging from 2.5:1 to 10:1, and, therefore, can significantly influence subsequent device functionality. In this work, we introduce an optimised two-step Bosch process that reduces the etch lag to below 1.5%. Furthermore, we demonstrate an improved three-step Bosch process, allowing the fabrication of structures with 6 μm width at depths up to 180 μm while maintaining their stability.

• The deep reactive ion etching (DRIE) of in-plane silicon microneedles is presented. • A needle sharpening process is developed using sacrificial layers (remaining unetched silicon). • The wedge-shaped needle is sharpened to conical structure tapering from the base to the apex. • The sharp microneedles have been demonstrated to be sufficiently robust for skin penetration. The deep reactive ion etching (DRIE) of in-plane silicon microneedles with open capillary microfluidic network is presented. The in-plane needle design allows easy fabrication of long needles for accessing abundant dermal fluids and improves the correlation with blood biomarkers. However, the anisotropic DRIE yields wedge-shaped (not sharp) needle tip. We developed a sharpening process using the sacrificial layers (remaining unetched silicon layer below the needle shaft) to facilitate the buildup of the concentration gradient of the etching species during the wet etching sharpening process, resulting in the relatively fast etching rate at shaft top than the bottom. As a result, the wedge-shaped structure is sharpened to conical structure, tapering smoothly from the base to the apex. Such sharp microneedles have been demonstrated to be sufficiently robust to penetrate porcine skins, with needles being intact after repetitive penetrations. The fabricated silicon devices are treated with oxygen plasma for making the surface hydrophilic, such that the capillary fluid is introduced within the open microfluidic network. [ABSTRACT FROM AUTHOR]

Abstract High quality gratings are among the key elements for successful imaging with X-ray grating interferometry. Grating fabrication, specifically of absorption gratings, with high aspect ratio and large area, is a great challenge from a microfabrication point of view. In this paper the fabrication of absorption gratings by seedless electroplating of gold in high aspect ratio silicon moulds that are fabricated by deep reactive ion etching (Bosch process) is presented. We report on our latest results and discuss the possibility of reducing the grating period down to 1.3 μ m. In addition, the quality of the gratings is assessed by performing visibility measurements and imaging various samples on a compact in house X-ray grating interferometer. [ABSTRACT FROM AUTHOR]

Abstract Electron-beam lithography (EBL) possesses tremendous capabilities in terms of patterning ultra-small features, with very low line edge roughness and high overlay accuracy. In order to reduce write times and processing steps, hybrid lithography is an interesting alternative. Here, an approach combining EBL and ultraviolet lithography (UVL) was pursued in order to pattern multi-level 3D-structures by inductively coupled plasma deep reactive ion etching (ICP-DRIE). The substrate etched hereby consisted of a silicon nitride thin film and the underlying silicon. The correlation of UVL under- and overexposures with the resist layer height and sidewall taper after development, in combination with the optimization of the ICP-DRIE selectivity in dependence of the biasing conditions and the aspect ratio dependent etch lag for small features, allowed for the accurate prediction and therefore programming of the desired structures. Further, the selectivity was tailored by introducing an oxygen pulse after the breakthrough step. This facilitated the simultaneous etching of structures with an in-plane resolution of down to 250 nm (aspect ratio 1:22) and trench depths ranging from 200 nm to 25 μm. Graphical abstract Unlabelled Image Highlights • A 2D lithography approach to etch 3D structures in a single step was developed and characterized. • The combination of hybrid lithography and deep reactive ion etching enables the simultaneous structuring of features, in- and out-of-plane, spanning three orders of magnitude in size. • Pattern transfer rate and taper control of a Novolac based resist were obtained by introducing an additional oxygen pulse after the breakthrough step. [ABSTRACT FROM AUTHOR]

The research field of metasurfaces has attracted considerable attention in recent years due to its high potential to achieve flat, ultrathin optical devices of high performance. Metasurfaces, consisting of artificial patterns of subwavelength dimensions, often require fabrication techniques with high aspect ratios (HARs). Bosch and Cryogenic methods are the best etching candidates of industrial relevance towards the fabrication of these nanostructures. In this paper, we present the fabrication of Silicon (Si) metalenses by the UV-Nanoimprint Lithography method and cryogenic Deep Reactive Ion Etching (DRIE) process and compare the results with the same structures manufactured by Bosch DRIE both in terms of technological achievements and lens efficiencies. The Cryo- and Bosch-etched lenses attain efficiencies of around 39% at wavelength λ = 1.50 µm and λ = 1.45 µm against a theoretical level of around 61% (for Si pillars on a Si substrate), respectively, and process modifications are suggested towards raising the efficiencies further. Our results indicate that some sidewall surface roughness of the Bosch DRIE is acceptable in metalense fabrication, as even significant sidewall surface roughness in a non-optimized Bosch process yields reasonable efficiency levels.

We fabricated silicon (100) membranes of 3 mm in diameter on the surface of silicon-on-insulator (SOI) substrates and investigated the characteristics of the membranes. The handle layer of one SOI substrate was etched using deep reactive ion etching process with the buried oxide (BOX) layer that remained together with the device layer. The BOX layer of the other SOI substrate was removed using C4F8-based plasma etching after the handle layer etching. The surfaces of both silicon (100) membranes were observed using the scanning white light interferometer system at room temperature. Both silicon (100) membranes have dome-like deformations. The silicon (100) membranes are effectively flattened by etching the BOX layer under the device layer. Both silicon (100) membranes were cooled from room temperature to 4 K by a Gifford-McMahon refrigerator. Wrinkles appeared on the surfaces of both silicon (100) membranes when the temperature dropped to about 200 K. However, the wrinkles disappeared below about 180 K. This phenomenon indicates the wrinkles at low temperature would depend on the properties of the silicon (100) of the device layers and independent of the properties of the BOX layers under the silicon (100) membranes. [ABSTRACT FROM AUTHOR]

We introduced a microfluidic device for high-efficiency single cell capture and their subsequent extraction. It was fabricated by using a deep reactive ion etching process taking advantage of the lag effect. We accomplished single cell capture based on the least flow resistance path principle as well as independent extraction of individual captured cells to perform their subsequent analysis. The device was performed with >99% single cell capture efficiency. [ABSTRACT FROM AUTHOR]

This paper reports an advanced deep reactive ion etching (DRIE) process for realizing ultra-deep (>500- $\mu \text{m}$ ) and ultra-high aspect-ratio (UHAR) silicon structures (AR > 40 for 1-mm through-trench etch, $\text {AR}\approx 80$ for 500- $\mu \text{m}$ through-trench etch, and AR > 20 for 500- $\mu \text{m}$ through-hole etch), with straight sidewalls across a wide range of feature sizes. The challenges of making such structures are overcome by continuously ramping critical parameters of the Bosch DRIE process throughout the process, including the 380-kHz bias power during etch step, the etch/passivation step duration, and the chamber pressure. The masking material capable of enduring the long DRIE process is also discussed; 10- $\mu \text{m}$ and 25- $\mu \text{m}$ wide trenches are etched to a depth of >750- $\mu \text{m}$ and >1000- $\mu \text{m}$ , respectively, in 1-mm-thick silicon wafers with straight sidewall profiles and flat trench bottoms. Deeper trenches are expected to be etched beyond a 1-mm thick wafer with thicker and/or higher selectivity masking materials. We have also demonstrated etching of circular holes of diameters as small as 25- $\mu \text{m}$ to a depth of >500- $\mu \text{m}$ , and potentially with 10–15 $\mu \text{m}$ diameter holes. This advanced DRIE process offers opportunities for applications ranging from through-silicon via in 3-D CMOS integration to emerging micro- and meso-scale microelectromechanical system applications that demand ultra-deep and UHAR DRIE. [2017–0298] [ABSTRACT FROM AUTHOR]

SUMMARY: This paper describes development of self‐heated stage suitable for thermal reactive ion etching (TRIE) of the functional metals. TRIE was evaluated using both experiments and simulations for etching functional metals. The self‐heated stage was designed based on the simulation results. TRIE employs a self‐heated stage which is thermally insulated aluminum plate as the etching stage of a regular RIE apparatus. The stage temperature increases rapidly within 10 min and etch rate does not depend on process time. TRIE technique was used to etch various kinds of functional metals: Ti, Mo, Ta, Nb, and Ti alloy (Ti‐6Al‐4V). It did improve the etching rate of these materials greatly. [ABSTRACT FROM AUTHOR]

A three-dimensional topography simulation of deep reactive ion etching (DRIE) is developed based on the narrow band level set method for surface evolution and Monte Carlo method for flux distribution. The advanced level set method is implemented to simulate the time-related movements of etched surface. In the meanwhile, accelerated by ray tracing algorithm, the Monte Carlo method incorporates all dominant physical and chemical mechanisms such as ion-enhanced etching, ballistic transport, ion scattering, and sidewall passivation. The modified models of charged particles and neutral particles are epitomized to determine the contributions of etching rate. The effects such as scalloping effect and lag effect are investigated in simulations and experiments. Besides, the quantitative analyses are conducted to measure the simulation error. Finally, this simulator will be served as an accurate prediction tool for some MEMS fabrications. [ABSTRACT FROM AUTHOR]

Microelectrode array (MEA) is one of the representative platforms for recording and stimulating neurons to explore their populational electrophysiological activities. Due to the layered structures of the nervous system, various three-dimensional (3D) MEAs have been used to reach specific target depths of neuronal tissues. But it is still difficult to monolithically fabricate various heights of microelectrodes, particularly with optical transparency. Here, we present a 3D MEA with different heights fabricated by multi-step silicon deep reactive ion etching. The microelectrodes were embedded in reflowed glass for high transparency which enables both neural tissue observation and optical stimulation. The heights of microelectrodes were well controlled by our fabrication processes and electrical connections were made with through glass vias (TGVs) to the bottom side for individual addressing. To confine electric stimulation in a small area, we used microelectrodes neighboring a stimulation electrode as local returns. The feasibility of the fabricated MEA was demonstrated by stimulating the mouse retina and successfully recording spikes of ganglion cells located near the stimulation site. Consistent with our COMSOL simulation, the ex vivo experimental results showed the stimulation current confinement was effective. Our study provides a new tool for 3D nervous systems and its fabrication method. • Transparent three-dimensional (3D) microelectrode array (MEA) has been fabricated. • Simple steps with multi-step deep reactive ion etching and a self-alignment etching • COMSOL simulations showed the electrical stimulation can be effectively confined. • Our ex vivo experiments showed the focal stimulation of neurons was possible. [ABSTRACT FROM AUTHOR]

We present two simple methods, with parallel and serial gas flows, for the stacking of microfabricated silicon fuel cells with integrated current collectors, flow fields and gas diffusion layers. The gas diffusion layer is implemented using black silicon. In the two stacking methods proposed in this work, the fluidic apertures and gas flow topology are rotationally symmetric and enable us to stack fuel cells without an increase in the number of electrical or fluidic ports or interconnects. Thanks to this simplicity and the structural compactness of each cell, the obtained stacks are very thin (~1.6 mm for a two-cell stack). We have fabricated two-cell stacks with two different gas flow topologies and obtained an open-circuit voltage (OCV) of 1.6 V and a power density of 63 mW·cm−2, proving the viability of the design.

We report the design and implementation of a unique, wafer sized stretchable and bendable monolithic silicon matrix structure. The achieved stretchability allows for simultaneous omnidirectional folding, required to conform the structure to complex curved 3D surfaces. Moreover, it also enables dynamic mechanical deformation of the structure to cope with a moving environment, like e.g., the wall of the heart muscle. Due to the nature of the fabrication process, normal silicon wafer processing can be performed prior to rendering it stretchable. This is first demonstrated by the fabrication of two metal layers on top of silicon, which act as the electrical interconnects of a final flexible and stretchable LED-matrix. Currently, the possibility to postprocess an existing commercial CMOS process is investigated. This would lead to a revolutionary potential of new applications, especially in the medical field, by enabling complex silicon monitoring systems to be linked to organs without hindering them.

A three-dimensional topography simulation of deep reactive ion etching (DRIE) is developed based on the narrow band level set method for surface evolution and Monte Carlo method for flux distribution. The advanced level set method is implemented to simulate the time-related movements of etched surface. In the meanwhile, accelerated by ray tracing algorithm, the Monte Carlo method incorporates all dominant physical and chemical mechanisms such as ion-enhanced etching, ballistic transport, ion scattering, and sidewall passivation. The modified models of charged particles and neutral particles are epitomized to determine the contributions of etching rate. The effects such as scalloping effect and lag effect are investigated in simulations and experiments. Besides, the quantitative analyses are conducted to measure the simulation error. Finally, this simulator will be served as an accurate prediction tool for some MEMS fabrications.

The cryogenic process and the Bosch process are two widely used processes for reactive ion etching of high aspect ratio silicon structures. This paper focuses on the cryogenic deep etching of 400-nm pitch silicon gratings with various etching mask materials, including polymer, Cr, SiO2, and Cr-on-polymer. The undercut is found to be the key factor limiting the achievable aspect ratio for the direct hard masks of Cr and SiO2, while the etch selectivity responds to the limitation of the polymer mask. The Cr-on-polymer mask provides the same high selectivity as Cr and reduces the excessive undercut introduced by direct hard masks. By optimizing the etching parameters, we etched a 400-nm pitch grating to \approx 10.6~\mu \textm depth, corresponding to an aspect ratio of $\approx 53$ . [2016-0106] [ABSTRACT FROM AUTHOR]

Fabrication of 3-D microstructures is one of the most challenging aspects of silicon micromachining. In this paper, we present a novel microfabrication method using one single-step deep reactive ion etching process with gray-scale e-beam lithography mask that offers deeply etched (>350- \mu \textm deep) dual-angle 3-D microneedles with control over the height and shape of the structures. Moreover, we found that the shape of the e-beam lithography patterns can determine the general configuration and features of the final etched microneedles, and that the etching process parameters have the most impact on the microneedles’ shape, such as size and vertical base angle. Large arrays of $20\times 20$ microneedles with height uniformity of better than 3% are fabricated. [2014-0209] [ABSTRACT FROM PUBLISHER]

The effects of silicon etching and subsequent metallization during the fabrication of tungsten-lined open TSVs are examined using a combination of measurements and simulations. The total stress through a tungsten film deposited on a flat wafer is measured and finite element simulations are performed in order to identify the intrinsic and thermal stress components in the film. The data is then used to observe and model the stress through a TSV structure, which is etched using the DRIE process, resulting in scalloped inner sidewalls through the TSV opening. The scalloped structure is then compared to the ideal flat alternative with regard to the stress through the metal film and the TSV's electrical parameters, including resistance, capacitance, and inductance. It is found that the stress around the scallop varies significantly while the average stress through the tungsten in the flat TSV is only slightly higher than the stress observed through the scalloped structure. The resistance, capacitance, and inductance are all found to increase in the presence of scallops. [ABSTRACT FROM AUTHOR]

Electrical through-wafer interconnect technologies such as vertical through-silicon vias (TSVs) are essential in order to maximize performance, optimize usage of wafer real estate, and enable three-dimensional packaging in leading edge electronic and microelectromechanical systems (MEMS) products. Although copper TSVs have the advantage of low resistance, highly doped polysilicon TSVs offer designers a much larger range of processing options due to the compatibility of polysilicon with high temperatures and also with the full range of traditional CMOS processes. Large stresses are associated with both Cu and polysilicon TSVs, and their accurate measurement is critical for determining the keep-out zone (KOZ) of transistors and for optimizing downstream processes to maintain high yield. This report presents the fabrication and stress characterization of 400-µm deep, 20-Ω resistance, high aspect ratio (25:1) polysilicon TSVs fabricated by deep reactive ion etching (DRIE) followed by low-pressure chemical vapor deposition (LPCVD) of polysilicon with in-situ boron doping. Micro-Raman imaging of the wafer surface showed a maximum stress of 1.2 GPa occurring at the TSV edge and a KOZ of ~9 to 11 µm. For polysilicon TSVs, the stress distribution in the TSVs far from the wafer surface(s) was not previously well-understood due to measurement limitations. Raman spectroscopy was able to overcome this limitation; a TSV cross section was examined and stresses as a function of both depth and width of the TSVs were collected and are analyzed herein. An 1100░C postanneal was found to reduce average stresses by 40%. [ABSTRACT FROM AUTHOR]

• Micro-heat sink based on silicon nanowires formed by MACE. • Silicon nanowires with diameter of 100 nm and height of 9 µm. • Micro-heat sink effectiveness of heat transfer rate is enhanced by 8.3 times. • Improve performance of the micro-thermoelectric generator. • Other potential applications: micro-supercapacitor, micro-sensor, and biological processes. This work demonstrates the micro-heat sink based on silicon nanowires formed by metal-assisted chemical etching (MACE) for heat dissipation enhancement to improve the performance of the micro-thermoelectric generator (µ-TEG). The heat dissipation through the micro-heat sink is enhanced by increasing the surface-to-volume ratio, which can be achieved by combining deep reactive ion etching (RIE) and MACE. Silicon nanowires with a diameter of 100 nm and a height of 9 µm are successfully formed in both horizontal and vertical surface directions. The micro-heat sink effectiveness is 8.3 times better than that of without employing the micro-heat sink. In addition, the performance of the µ-TEG has been significantly enhanced by utilizing the micro-heat sink. The maximum output power of the µ-TEG with and without the micro-heat sink are 93 µW and 18.5 µW, respectively, under the same evaluation conditions. The findings in this work may be useful not only for the µ-TEG, but also other applications such as micro-supercapacitors, micro-sensors, chemical analysis, and biological processes, which require a large surface-to-volume ratio. [ABSTRACT FROM AUTHOR]