127 results on '"Debusschere, I."'
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2. Optimization of gate stack parameters towards 3D-SONOS application
3. Ionizing radiation hardening of a CCD technology
4. A 1006 element hybrid silicon pixel detector with strobed binary output
5. A Foveated Retina-Like Sensor Using CCD Technology
6. O2 post deposition anneal of Al2O3 blocking dielectric for higher performance and reliability of TANOS Flash memory
7. A low-cost 90 nm RF-CMOS platform for record RF circuit performance
8. Copper through silicon via induced keep out zone for 10nm node bulk FinFET CMOS technology
9. Standard cell level parasitics assessment in 20nm BPL and 14nm BFF
10. Impact of through silicon via induced mechanical stress on fully depleted Bulk FinFET technology
11. Ultra thin hybrid floating gate and high-k dielectric as IGD enabler of highly scaled planar NAND flash technology
12. Understanding of Trap-Assisted Tunneling Current - Assisted by Oxygen Vacancies in RuOx/SrTiO3/TiN MIM Capacitor for the DRAM Application
13. Hybrid Floating Gate Cell for Sub-20-nm NAND Flash Memory Technology
14. Highly Scaled Vertical Cylindrical SONOS Cell With Bilayer Polysilicon Channel for 3-D nand Flash Memory
15. (Invited) Plasma Enhanced Atomic Layer Deposited Ruthenium for MIMCAP Applications
16. Process Development of ALD-Rutile-TiO2/Ru(Ox) for DRAM MIMcap Application and its Leakage Mechanism Analysis
17. Impact of bottom electrode and SrxTiyOz film formation on physical and electrical properties of metal-insulator-metal capacitors
18. Advanced Capacitor Dielectrics: Towards 2x nm DRAM
19. Novel Bi-Layer Poly-Silicon Channel Vertical Flash Cell for Ultrahigh Density 3D SONOS NAND Technology
20. High Performance THANVaS Memories for MLC Charge Trap NAND Flash
21. A PEALD Tunnel Dielectric for Three-Dimensional Non-Volatile Charge-Trapping Technology
22. DEVELOPMENT OF SILICON MICROPATTERN PIXEL DETECTORS
23. RD19: status report on 1993 development of hybrid and monolithic silicon micropattern detectors
24. Impact of crystallization behavior of SrxTiyOz films on electrical properties of metal-insulator-metal capacitors with TiN electrodes
25. Investigation of rare-earth aluminates as alternative trapping materials in Flash memories
26. Optimization of the crystallization phase of Rare-Earth aluminates For blocking dielectric application in TANOS type flash memories
27. Impact of thinning and through silicon via proximity on High-k / Metal Gate first CMOS performance
28. Temperature dependent electrical characteristics of through-si-via (TSV) interconnections
29. RD19: status report and addendum. Development of hybrid and monolithic silicon micropattern detectors
30. 3D stacked ICs using Cu TSVs and Die to Wafer Hybrid Collective bonding
31. O2 post deposition anneal of Al2O3 blocking dielectric for higher performance and reliability of TANOS Flash memory
32. 3D stacked IC demonstration using a through Silicon Via First approach
33. RADIATION SENSITIVE SENSOR HAVING A PLURALITY OF RADIATION SENSITIVE ELEMENTS ARRANGED SUBSTANTIALLY CIRCULAR WITH RADIALLY DECREASING DENSITY
34. Optimization of HfSiON using a design of experiment (DOE) approach on 0.45V Vt Ni-FUSI CMOS transistors
35. FUSI Specific Yield Monitoring Enabling Improved Circuit Performance and Fast Feedback to Production
36. Development of hybrid and monolithic silicon micropattern detectors: status report RD19
37. Methodology for characterizing the impact of circuit layout, technology options, device engineering and temperature on the circuit power-delay characteristics
38. RADIATION-SENSITIVE MEAN OR SENSOR IN RETINA-LIKE CONFIGURATION
39. R&D proposal: development of hybrid and monolithic silicon micropattern detectors
40. An Ultra-Thin Hybrid Floating Gate Concept for Sub-20nm NAND Flash Technologies.
41. Exploration of rare earth materials for future interpoly dielectric replacement in Flash memory devices.
42. 90nm RF CMOS technology for low-power 900MHz applications [amplifier example].
43. Thin L-shaped spacers for CMOS devices.
44. Optimisation of a Pre-Metal-Dielectric with a contact etch stop layer for 0.18um and 0.13um technologies.
45. Importance of determining the polysilicon dopant profile during process development
46. Integration of CMOS-electronics and particle detector diodes in high-resistivity silicon-on-insulator wafers
47. Characterization of the ionizing radiation sensitivity of a CCD technology
48. Development of silicon micropattern (pixel) detectors
49. Optimizing and controlling the radiation hardness of a CCD process.
50. Characterization of the Ionizing Radiation Sensitivity of a CCD Technology.
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