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1. Main chain scission resists towards high-NA EUV lithography

2. Patterning optimization for single mask bit-line-periphery and storage-node-landing-pad DRAM layers using 0.33NA EUV lithography at the resolution limit

4. Holistic litho-etch approach towards high NA EUV challenges

11. Scaled-down deposited underlayers for EUV lithography

13. Recent advances in EUV patterning in preparation towards high-NA EUV

15. Patterning optimization for single mask bit-line-periphery and storage-node-landing-pad DRAM layers using 0.33NA EUV lithography at the resolution limit

19. Dry resist metrology readiness for high-NA EUVL

20. e-beam metrology of thin resist for high NA EUVL

27. Role of landing energy in e-beam metrology of thin photoresist for high-numerical aperture extreme ultraviolet lithography

33. Holistic litho-etch development to address patterning challenges towards high NA EUV

35. High-NA EUV photoresist metrology using high-throughput scanning probe microscopy

38. Metrology of thin resist for high NA EUVL

49. EUV based multi-patterning schemes for advanced DRAM nodes

50. Approaches to enable patterning of tight pitches towards high NA EUV

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