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Abstract In this work, a novel deep trench CSTBT (DT-CSTBT) features emitter trench and the P-layer is proposed and investigated by simulation. The self-biased pMOS, comprising an emitter trench, N-CS layer, P-layer, and P-well, demonstrates an excellent clamping effect potential. The proposed DT-CSTBT suppresses the saturation current and improves the heat dissipation, resulting in a 23.5% expansion of the short-circuit safe operating area (SCSOA). It ensures the better reliability of the gate due to the high electric field away from the gate. Furthermore, the tradeoff relationship between on-state voltage (V ON) and turn-off loss (E off) of the new structure is also improved by 23.2% compared with the conventional CSTBT.

Abstract In this work, a multi-stage material design framework combining machine learning techniques with density functional theory is established to reveal the mechanism of phase stabilization in HfO2 based ferroelectric materials. The ferroelectric phase fractions based on a more stringent relationship of phase energy differences is proposed as an evaluation criterion for the ferroelectric performance of hafnium-based materials. Based on the Boltzmann distribution theory, the abstract phase energy difference is converted into an intuitive phase fraction distribution mapping. A large-scale prediction of unknown dopants is conducted within the material design framework, and gallium (Ga) is identified as a new dopant for HfO2. Both experiments and density functional theory calculations demonstrate that Ga is an excellent dopant for ferroelectric hafnium oxide, especially, the experimentally determined variation trends of ferroelectric phase fraction and polarization properties with Ga doping concentration are in good agreement with the predictions given by machine learning. This work provides a new perspective from machine learning to deepen the understanding of the ferroelectric properties of HfO2 materials, offering fresh insights into the design and performance prediction of HfO2 ferroelectric thin films.

Abstract Hafnium oxide (HfO2)‐based devices have been extensively evaluated for high‐speed and low‐power memory applications. Here, the influence of aluminum (Al) and lanthanum (La) co‐doping HfO2 thin films on the ferroelectric characteristics of hafnium‐based devices is investigated. Among devices with different La/Al ratios, the Al and La co‐doped hafnium oxide (HfAlAO) device with 4.2% Al and 2.17% La exhibited the excellent remanent polarization and thermostability. Meanwhile, first principal analyses verified that hafnium‐based thin films with 4.2% Al and 2.17% La promoted the formation of the o‐phase against the paraelectric phase, providing theoretical support for supporting experimental results. Furthermore, a vertical ferroelectric HfO2 memory based on 3D macaroni architecture is reported. The devices show excellent ferroelectric characteristics of 22 µC cm−2 under 4.5 MV cm−1 and minimal coercive field of ≈1.6 V. In addition, the devices exhibit great memory performance, including the response speed of device can achieve 20 ns and endurance characteristic can achieve 1010 cycles.

Indium–gallium–zinc oxide (IGZO) as a star material has been broadly applied in multiple functional devices, including planar displays, flexible electronic devices, and photoelectronics. In recent years, the development of artificial intelligence and great data also extends the application of IGZO-based thin film transistors (TFTs) to memory, memristors, and neuromorphic computing. Thus, the research of high performance and reliable IGZO TFTs attracts tremendous attention worldwide. Herein, a high-quality IGZO thin film was deposited via atomic layer deposition, and a dual-gate (DG) IGZO TFT was fabricated. Comprehensive electrical characterization was conducted on the fabricated DG IGZO TFTs, revealing that DG IGZO TFTs exhibited good performance for reliability analysis. The reliability and degradation mechanism of the DG IGZO TFT was systematically investigated under bias stress at room temperature and elevated temperatures of 350, 400, and 450 K by the comprehensive electrical characterization. Results indicate that the defects of the dual gate insulators and the interfaces majorly influence the degradation under bias stresses, while the carrier scattering of the IGZO channel is the major degradation mechanism under elevated temperatures. These findings highlight the degradation mechanism of the DG IGZO TFT under bias stress and elevated temperatures from a novel viewpoint, which provides a utilizable reference to its application in circuits.

Abstract With the development of wearable devices and hafnium-based ferroelectrics (FE), there is an increasing demand for high-performance flexible ferroelectric memories. However, developing ferroelectric memories that simultaneously exhibit good flexibility and significant performance has proven challenging. Here, we developed a high-performance flexible field-effect transistor (FeFET) device with a thermal budget of less than 400 °C by integrating Zr-doped HfO2 (HZO) and ultra-thin indium tin oxide (ITO). The proposed FeFET has a large memory window (MW) of 2.78 V, a high current on/off ratio (ION/IOFF) of over 108, and high endurance up to 2×107 cycles. In addition, the FeFETs under different bending conditions exhibit excellent neuromorphic properties. The device exhibits excellent bending reliability over 5×105 pulse cycles at a bending radius of 5 mm. The efficient integration of hafnium-based ferroelectric materials with promising ultrathin channel materials (ITO) offers unique opportunities to enable high-performance back-end-of-line (BEOL) compatible wearable FeFETs for edge intelligence applications.

Research of artificial synapses is increasing in popularity with the development of bioelectronics and the appearance of wearable devices. Because the high-temperature treatment process of inorganic materials is not compatible with flexible substrates, organic ferroelectric materials that are easier to process have emerged as alternatives. An organic synaptic device based on P(VDF-TrFE) was prepared in this study. The device showed reliable P/E endurance over 104 cycles and a data storage retention capability at 80 °C over 104 s. Simultaneously, it possessed excellent synaptic functions, including short-term/ long-term synaptic plasticity and spike-timing-dependent plasticity. In addition, the ferroelectric performance of the device remained stable even under bending (7 mm bending radius) or after 500 bending cycles. This work shows that low-temperature processed organic ferroelectric materials can provide new ideas for the future development of wearable electronics and flexible artificial synapses.

Al-doped HfO2 (HAO) is regarded as one of the potential HfO2 ferroelectric materials owing to its compatibility with the front end of the line process in integration circuits. In this work, atomic layer deposited (ALD) HAO thin films with different Al-doping concentrations and the corresponding devices with Ti or W top electrodes have been explored. It is found that the HAO film properties and corresponding ferroelectric device performances depend greatly on the doping concentration. In the concentration range of 3.0%–5.0%, 4.5% is the most proper doping concentration to induce the ferroelectricity of the thin film. It is revealed by x-ray diffraction and photoelectron spectroscopy that the oxygen vacancies can be modulated by doping, thereby contributing to the formation of the ferroelectric orthorhombic phase. A high remnant polarization (2Pr) of 36.8 ± 0.7 μC/cm2 under 5 mV/cm sweeping is observed through electrical measurement in the device with a 4.5% HAO and W top electrode. In addition, it was found that the choice of W or Ti top electrodes would affect the leakage and breakdown characteristics of the device. This work reveals the mechanism of Al doping and electrode modulation of HfO2 device performance and promotes the development of HAO ferroelectric thin film devices.

Highlights A conductive, stretchable, adaptable, and self-healing, GaInSn/Ni--based composite hydrogel by incorporating a magnetic liquid metal into the hydrogel framework through crosslinking polyvinyl alcohol with sodium tetraborate. The multifunctional composite hydrogels showed outstanding performance for magnetic repair movement sensing, and EMI shielding.

Heterogeneous integration of $\beta $ -Ga2O3 with Si substrate is considered as an effective and low-cost technology for the thermal management of $\beta $ -Ga2O3 electrical devices. In this work, an isotype heterojunction of n-Ga2O3/n+-Si (Ga2O3/Si) was fabricated by surface activated bonding in which an amorphous layer was induced by ion beam bombardment. The current density of Ga2O3/Si Schottky barrier diodes (SBDs) are about two orders of magnitude lower than that of Ga2O3 bulk SBDs at 2.8 V due to the influence of amorphous layer. The results are consistent with the simulation results when $\beta $ -Ga2O3 Mole Fraction (MF $=\,\,\text{n}(\beta $ -Ga2O3)/[ $\text{n}(\beta $ -Ga2O3) + n(SiO2)]) and thickness of amorphous layers (Tox) are set at 0.83 and 3 nm, respectively. Furthermore, devices with different MF and ${\mathrm{ T}}_{\mathrm{ ox}}$ were simulated based on the nonlocal tunneling model by Sentaurus TCAD. The decrease of $\beta $ -Ga2O3 Mole Fraction and increase of amorphous layers thickness in the hetero-interface of Ga2O3/Si SBDs lead to a dramatic degeneration of current density and specific on-resistance in Ga2O3/Si SBDs. These results may provide some guidance for improvement of vertical heterogeneous integration $\beta $ -Ga2O3 devices performance.

The application of SiC-based strain-relaxed buffers (SRB) technology in gate-all-around (GAA) pMOS nanosheet transistors (NS-FETs) fabrication has been systematically investigated. TCAD simulation results show that SiC SRB can effectively enhance the p-channel stress, up to 3.8Gpa has been achieved without S/D parasitic RC degradation. Furthermore, introducing a wide-bandgap SiC layer underneath NS-FET can help suppress the bottom parasitic transistor. The SiC SRB technology presents a integrated and streamlined approach for addressing the major performance bottlenecks of NS-FETs and is a potential solution for developing future NS-FET based high-performance and low-power logic applications.

The low-dropout (LDO) regulator is an important component in power management IC (PMIC) chips and is widely utilized in electronic modules, such as mobile processors and Internet of Things (IoT) devices. To ensure the proper functionality of these modules, automatic test equipment (ATE) is typically used to test and calibrate LDO modules in the mass production stage. During the test process, the presence of pollutants in the test environment or inappropriate test settings can cause a discrepancy between the expected performance of the chip and its actual output. When conventional ATE test methods fail to identify these types of risks, this study proposes a novel self-adaptive screening method that enhances the possibility of screening out weak chips without the need for additional testing hardware or stages. This screening method accumulates and analyzes effective test data measured by ATE in real time, and derives a dynamic test limit to screen weak chips by performing systematic statistical analysis on the collected data, combined with the chip’s practical application requirements and tolerance. During the experimental stage, the author selected a chip lot and applied the proposed testing method. The results showed that 90.91% of escape defective chips were successfully screened, with a reasonable yield impact of 3.38%, compared to the traditional ATE test methodology which had a low capture rate.

Neuromorphic computing memristors are attractive to construct low-power- consumption electronic textiles. Here, authors report an ultralow-power textile memristor network of Ag/MoS2/HfAlOx/carbon nanotube with reconfigurable characteristics and firing energy consumption of 1.9 fJ/spike.

In this paper, we demonstrate a comprehensive study of NF3-based selective etching processes for inner spacer formation and for channel release, enabling stacked horizontal gate-all-around Si nanosheet transistor architectures. A cyclic etching process consisting of an oxidation treatment step and an etching step is proposed and used for SiGe selective etching. The cyclic etching process exhibits a slower etching rate and higher etching selectivity compared to the direct etching process. The cycle etching process consisting of Recipe 1, which has a SiGe etching rate of 0.98 nm/cycle, is used for the cavity etch. The process achieved good interlayer uniformity of cavity depth (cavity depth ≤ 5 ± 0.3 nm), while also obtaining a near-ideal rectangular SiGe etch front shape (inner spacer shape = 0.84) and little Si loss (0.44 nm@ each side). The cycle etching process consisting of Recipe 4 with extremely high etching selectivity is used for channel release. The process realizes the channel release of nanosheets with a multi-width from 30 nm to 80 nm with little Si loss. In addition, a selective isotropic etching process using NF3/O2/Ar gas mixture is used to etch back the SiN film. The impact of the O2/NF3 ratio on the etching selectivity of SiN to Si and the surface roughness of SiN after etching is investigated. With the introduction of O2 into NF3/Ar discharge, the selectivity increases sharply, but when the ratio of O2/NF3 is up to 1.0, the selectivity tends to a constant value and the surface roughness of SiN increases rapidly. The optimal parameter is O2/NF3 = 0.5, resulting in a selectivity of 5.4 and a roughness of 0.19 nm.

A novel high-speed and process-compatible carrier-stored trench-gate bipolar transistor (CSTBT) combined with split-gate technology is proposed in this paper. The device features a split polysilicon electrode in the trench, where the left portion is equipotential with the cathode. This design mitigates the impact of the anode on the trench gate, resulting in a reduction in the gate-collector capacitance (CGC) to improve the dynamic characteristics. On the left side of the device cell, the P-layer, the carrier-stored (CS) layer and the P-body are formed from the bottom up by ion implantation and annealing. The P-layer beneath the trench bottom can decrease the electric field at the bottom of the trench, thereby improving breakdown voltage (BV) performance. Simultaneously, the highly doped CS layer strengthens the hole-accumulation effect at the cathode. Moreover, the PNP doping layers on the left form a self-biased pMOS. In a short-circuit state, the self-biased pMOS turns on at a certain collector voltage, causing the potential of the CS-layer to be clamped by the hole channel. Consequently, the short-circuit current no longer increases with the collector voltage. The simulation results reveal significant improvements in comparison with the conventional CSTBT under the same on-state voltage (1.48 V for 100 A/cm2). Specifically, the turn-off time (toff) and turn-off loss (Eoff) are reduced by 38.4% and 41.8%, respectively. The short-circuit current is decreased by 50%, while the short-circuit time of the device is increased by 2.46 times.

Abstract With the rapid development of the Internet of Things, there is a great demand for portable gas sensors. Metal oxide semiconductors (MOS) are one of the most traditional and well-studied gas sensing materials and have been widely used to prepare various commercial gas sensors. However, it is limited by high operating temperature. The current research works are directed towards fabricating high-performance flexible room-temperature (FRT) gas sensors, which are effective in simplifying the structure of MOS-based sensors, reducing power consumption, and expanding the application of portable devices. This article presents the recent research progress of MOS-based FRT gas sensors in terms of sensing mechanism, performance, flexibility characteristics, and applications. This review comprehensively summarizes and discusses five types of MOS-based FRT gas sensors, including pristine MOS, noble metal nanoparticles modified MOS, organic polymers modified MOS, carbon-based materials (carbon nanotubes and graphene derivatives) modified MOS, and two-dimensional transition metal dichalcogenides materials modified MOS. The effect of light-illuminated to improve gas sensing performance is further discussed. Furthermore, the applications and future perspectives of FRT gas sensors are also discussed.

Abstract HfAlO film‐based ferroelectric memory is a strong contender for the next‐generation nonvolatile memories. However, the remanent polarization intensity of HfAlO films is small compared to other Hf‐based ferroelectric films at low annealing temperatures. In order to further improve the remnant polarization of the device, the ferroelectric memory with metal‐ferroelectric‐metal structure using ZrO2 as the regulating layer (RL) is designed and fabricated. Experimental results show that the device with the ZrO2 regulating layer exhibits triple enhancement, which may be due to the fact that ZrO2 RL has an effect on the enhancement of the ferroelectric phase. In addition, the device with ZrO2 regulating layer exhibits a superior ON/OFF conductance ratio, endurance, and retention characteristics, demonstrating potential for application to memory. This work provides an effective way to improve the ferroelectricity in HfAlO films at low annealing temperatures.

Abstract With the rapid development of artificial intelligence (AI), there is an urgent need for developing a biological sensory perception system that can simulate the human brain for information processing. Inspired by the biological vision system, photo‐responsive photonic synapses are ideal devices for constructing photosensitive artificial neural networks for neuromorphic computing tasks. This paper reports a stable photonic synaptic device in an array layout with adjustable synaptic plasticity under ultraviolet light pulses. Since the heterojunction has a photoconductivity effect and the trap layer provides superior charge carrier trapping capability, optical sensing, memory, and neuromorphic computing are integrated into a single device. Meanwhile, supervised learning of handwritten digitals is achieved by exploiting the multistate conductance by photoelectric co‐modulation and the specific decay law. The recognition rate reaches 90.6% and hardly changes with time. Additionally, the device can simplify the artificial neural network (ANN) and reduce its size to 3.78% of the original network while retaining strong fault tolerance and learning ability. The photonic artificial synapses based on ultraviolet light modulation provide a novel and effective approach for photosensory ANNs to perform in situ computation.

Abstract Deep-ultraviolet (DUV) phototransistors have shown great potential applications in UV imaging, artificial intelligence, and wearable optoelectronics. Among a large number of wide bandgap semiconductors, the quasi-two-dimensional β-Ga2O3 is considered as an ideal candidate for DUV photodetector applications. Herein, we report a high responsivity (R) and fully flexible Ta-doped β-Ga2O3 DUV phototransistor which exhibits outstanding optoelectrical properties with a high R of 1.32 × 106 A/W, a large detectivity of 5.68 × 1014 Jones, a great photo-to-dark current ratio of 1.10 × 1010%, a high external quantum efficiency of 6.60 × 108%, and an ultra-fast response time of ~3.50 ms. Besides, the flexible Ta-doped β-Ga2O3 device also displays high reliability and mechanical flexibility that can sustain well after over 1 × 104 bending cycles. Moreover, high-contrast imaging of UV light was obtained on the flexible DUV detector arrays, which can be efficiently trained and recognized by an artificial neural network. Our findings offer a perspective to develop wearable optoelectronics and UV imaging based on high-performance flexible β-Ga2O3 DUV phototransistors, providing an inspiration for the future work in artificial intelligence and bionic robot fields.

As the architecture of logic devices is evolving towards gate-all-around (GAA) structure, research efforts on advanced transistors are increasingly desired. In order to rapidly perform accurate compact modeling for these ultra-scaled transistors with the capability to cover dimensional variations, neural networks are considered. In this paper, a compact model generation methodology based on artificial neural network (ANN) is developed for GAA nanosheet FETs (NSFETs) at advanced technology nodes. The DC and AC characteristics of GAA NSFETs with various physical gate lengths (Lg), nanosheet widths (Wsh) and thicknesses (Tsh), as well as different gate voltages (Vgs) and drain voltages (Vds) are obtained through TCAD simulations. Subsequently, a high-precision ANN model architecture is evaluated. A systematical study on the impacts of ANN size, activation function, learning rate, and epoch (the times of complete pass through the entire training dataset) on the accuracy of ANN models is conducted, and a shallow neural network configuration for generating optimal ANN models is proposed. The results clearly show that the optimized ANN model can reproduce the DC and AC characteristics of NSFETs very accurately with a fitting error (MSE) of 0.01.

Flip chip bonding technology on gold–tin (Au-Sn) microbumps for MEMS (Micro Electro Mechanical Systems) and 3D packaging is becoming increasingly important in the electronics industry. The main advantages of Au-Sn microbumps are a low electrical resistance, high electrical reliability, and fine pitch. However, the bonding temperature is relatively high, and the forming mechanism of an intermetallic compound (IMC) is complicated. In this study, Au-Sn solid-state diffusion (SSD) bonding is performed using the thermal gradient bonding (TGB) method, which lowers bonding temperature and gains high bonding strength in a short time. Firstly, Au-Sn microbumps with a low roughness are prepared by using an optimized process. Then, Au-Sn bonding parameters including bonding temperature, bonding time, and bonding pressure are optimized to obtain a higher bonding quality. The shear strength of 23.898 MPa is obtained when bonding in the HCOOH environment for 10 min at the gradient temperature of 150 °C/250 °C with a bonding pressure of more than 10 MPa. The IMC of Au-Sn is found to be Au-Sn and Au5Sn. The effect of annealing time on the IMC is also investigated. More and more Au5Sn is generated with an increase in annealing time, and Au5Sn is formed after Sn is depleted. Finally, the effect of annealing time on the IMC is verified by using finite element simulation, and the bonding strength of IMC was found to be higher when the bonding temperature is 150 °C at the cold side and 250 °C at the hot side. The temperature in the bonding area can reach 200 °C, which proves that the Au-Sn bonding process is solid-state diffusion because the temperature gradient reaches 2500 °C/cm.

Abstract Advanced synaptic devices capable of neuromorphic data processing are widely studied as the building block in the next‐generation computing architecture for artificial intelligence applications. Due to its fast speed, low power, and excellent complementary metal‐oxide‐semiconductor (CMOS) compatibility, Zr‐doped HfO2 (HZO)‐based ferroelectric tunnel junction (FTJ) are promising candidates as a new type of non‐volatile memory for neuromorphic device applications. Here, an experimental approach is reported to enhance the tunneling efficiency and the electrical performance by engineering the dielectric stack of the FTJ device. By sandwiching the HZO ferroelectric layer with ZrO2 and Al2O3 layers, the FTJ tunneling current is greatly increased with lowered barrier, larger remnant polarization (Pr), and tunneling electrical resistance ratio as well as suppressed leakage current have been achieved. The optimized FTJ devices are further implemented emulating synaptic functions with demonstrated short/long‐term synaptic plasticity and spike‐timing‐dependent plasticity behaviors. Such engineering in HZO‐based FTJ devices can be promising and instructive for the realization of future ultra‐low‐power and CMOS‐compatible neuromorphic devices and systems.

Inorganic micro light-emitting diodes (micro-LEDs) based on III-V compound semiconductors have been widely studied for self-emissive displays. From chips to applications, integration technology plays an indispensable role in micro-LED displays. For example, large-scale display relies on the integration of discrete device dies to achieve extended micro-LED array, and full color display requires integration of red, green, and blue micro-LED units on the same substrate. Moreover, the integration with transistors or complementary metal-oxide-semiconductor circuits are necessary to control and drive the micro-LED display system. In this review article, we summarized the 3 main integration technologies for micro-LED displays, which are called transfer integration, bonding integration, and growth integration. An overview of the characteristics of these 3 integration technologies is presented, while various strategies and challenges of integrated micro-LED display system are discussed.

The complementary field-effect transistor (CFET) with N-type FET (NFET) stacked on P-type FET (PFET) is a promising device structure based on gate-all-around FET (GAAFET). Because of the high-density stacked structure, the self-heating effect (SHE) becomes more and more severe. Buried thermal rail (BTR) technology on top of the buried power rail (BPR) process is proposed to improve heat dissipation. Through a systematical 3D Technology Computer Aided Design (TCAD) simulation, compared to traditional CFET and CFET with BPR only, the thermal resistance (Rth) of CFET can be significantly reduced with BTR technology, while the drive capability is also improved. Furthermore, based on the proposed BTR technology, different power delivery structures of top-VDD–top-VSS (TDTS), bottom-VDD–bottom-VSS (BDBS), and bottom-VDD–top-VSS (BDTS) were investigated in terms of electrothermal and parasitic characteristics. The Rth of the BTR-BDTS structure is decreased by 5% for NFET and 9% for PFET, and the Ion is increased by 2% for NFET and 7% for PFET.

Here, the authors demonstrate the application of machine learning to optimize the device fabrication process for wafer-scale 2D semiconductors, and eventually fabricate digital, analog, and optoelectrical circuits.

With the development of artificial intelligence and the Internet of Things, the number of sensory nodes is growing rapidly, leading to the exchange of large quantities of redundant data between sensors and computing units. In-sensor computing schemes, which integrate sensing and processing, have provided a promising route to addressing the sensing/processing bottleneck by reducing power consumption, time delay and hardware redundancy. In this study, an in-sensor computing architecture involving a photoelectronic cell based on a wafer-scale two-dimensional MoS2 thin film was demonstrated. The MoS2 photodetector cell used a top-gate device structure with indium tin oxide (ITO) as the transparent gate electrode, which exhibited high air-stability and a high photoresponsivity (R) up to 555.8 A W–1 at an illumination power density (Pin) of 16.0 µW cm–2 (λ = 500 nm). Additionally, a MoS2 photodetector array with uniform photoresponsive characteristics was achieved. Furthermore, logic gates, including inverter, NAND, and NOR, were achieved based on MoS2 photodetector cells. Such multifunctional and robust in-sensor computing was ascribed to the uniform wafer-scale MoS2 film grown by atomic layer deposition (ALD) and the unique device structure. Because the detection of optical signals and logic operations were achieved through MoS2 photodetector cells with area efficiency, the proposed in-sensor computing device paves the way for potential applications in high-performance, integrated sensing and processing systems.

In standard computing architectures, memory and logic circuits are separated, a feature that slows matrix operations vital to deep learning algorithms. Here, the authors present an alternate in-memory architecture and demonstrate a feasible approach for analog matrix multiplication.

A novel atomic-level post-etch-surface-reinforcement (PESR) process is developed to recover the p-GaN etching induced damage region for high performance p-GaN gate HEMTs fabrication. This process is composed of a self-limited surface modification step with O2 plasma, following by an oxide removal step with BCl3 plasma. With PESR process, the AlGaN surface morphology after p-GaN etching was comparable to the as-epitaxial level by AFM characterization, and the AlGaN lattice crystallization was also recovered which was measured in a confocal Raman system. The electrical measurement further confirmed the significant improvement of AlGaN surface quality, with one-order of magnitude lower surface leakage in a metal-semiconductor (MS) Schottky-diode and 6 times lower interface density of states (Dit) in a MIS C-V characterization. The XPS analysis of Al2O3/AlGaN showed that the p-GaN etching induced F-byproduct and Ga-oxide was well removed and suppressed by PESR process. Finally, the developed PESR process was successfully integrated in p-GaN gate HEMTs fabrication, and the device performance was significantly enhanced with ~20% lower of on-resistance and ~25% less of current collapse at Vds,Q bias of 40 V, showing great potential of leverage p-GaN gate HEMTs reliability.

A systematic study of epi-AlGaN/GaN on a SiC substrate was conducted through a comprehensive analysis of material properties and device performance. In this novel epitaxial design, an AlGaN/GaN channel layer was grown directly on the AlN nucleation layer, without the conventional doped thick buffer layer. Compared to the conventional epi-structures on the SiC and Si substrates, the non-buffer epi-AlGaN/GaN structure had a better crystalline quality and surface morphology, with reliable control of growth stress. Hall measurements showed that the novel structure exhibited comparable transport properties to the conventional epi-structure on the SiC substrate, regardless of the buffer layer. Furthermore, almost unchanged carrier distribution from room temperature to 150 °C indicated excellent two-dimensional electron gas (2DEG) confinement due to the pulling effect of the conduction band from the nucleation layer as a back-barrier. High-performance depletion-mode MIS-HEMTs were demonstrated with on-resistance of 5.84 Ω·mm and an output current of 1002 mA/mm. The dynamic characteristics showed a much smaller decrease in the saturation current (only ~7%), with a quiescent drain bias of 40 V, which was strong evidence of less electron trapping owing to the high-quality non-buffer AlGaN/GaN epitaxial growth.

In this work, we demonstrated a low current collapse normally on Al2O3/AlGaN/GaN MIS-HEMT with in situ H-radical surface treatment on AlGaN. The in situ atomic pretreatment was performed in a specially designed chamber prior to the thermal ALD-Al2O3 deposition, which improved the Al2O3/AlGaN interface with Dit of ~2 × 1012 cm−2 eV−1, and thus effectively reduced the current collapse and the dynamic Ron degradation. The devices showed good electrical performance with low Vth hysteresis and peak trans-conductance of 107 mS/mm. Additionally, when the devices operated under 25 °C pulse-mode stress measurement with VDS,Q = 40 V (period of 1 ms, pulse width of 1 μs), the dynamic Ron increase of ~14.1% was achieved.

Abstract The demand of flexible neuromorphic computing electronics is increasing with the rapid development of wearable artificial intelligent devices. The flexible resistive random‐access memory (RRAM) is one excellent candidate of high‐density storage devices. However, due to the limitations of fabrication process, materials system and device structure, it is difficult to prepare flexible 3D high‐density network for neuromorphic computing. In this paper, a 3D flexible memristors network is developed via low‐temperature atomic layer deposition (ALD) at 130°C, with potential of extending to various flexible electronics. The typical bipolar switching characteristics are verified in RRAM units of 3D network, including first, second and third layers. Besides binary storage, the multibit storage in single unit is demonstrated and the storage density is further increased. As a connection link between binary storage and brain‐inspired neuromorphic computing, the multibit storage capability paves the way for the tunable synaptic plasticity, for example, long‐term potentiation/depression (LTP/LTD). The 3D memristors network successfully mimicked the typical neuromorphic functionality and realized ultra‐multi conductance states modulation under 600 spikes. The robust mechanical flexibility is further demonstrated via LTP/LTD emulation under bending states (radius = 10 mm). The 3D flexible memristors network shows significant potential of applications in high‐performance, high‐density and reliable wearable neuromorphic computing system.

The fast development in microcontroller unit (MCU) technology has urged continuous decreasing in power consumption by different assignment of operating status among devices. In this work, we focused on the ultra-high Vth (UHVT) transistor and used gate oxide thickness and Vth implantation co-optimization to minimize the gate leakage current towards low-power MCU applications. Based on the 55 nm node, it has been found both theoretically and experimentally that the leakage level has been significantly reduced at different temperature in n-FET, p-FET, data flip-flop (DFF) and inverter (INV). Upon MCU testing under active, sleep and deep sleep modes, obvious decrease in the power consumption is also achieved, providing a promising optimization approach towards a better balance between the speed and power in modern MCU technology.

Ferroelectric devices with dielectric layers to modulate channel conductance have limited endurance and miniaturization. Here, the authors demonstrate a 2D ferroelectric channel transistor that integrates memory and computation capabilities, that will support the development of memory and computing fusion systems.

There is growing interest in non-traditional materials for logic applications. Here, the authors demonstrate a domain device architecture based on ferroelectric LiNbO3 crystals with gate voltage controlled transistor without subthreshold swing and source voltage controlled nonvolatile transistor.

Abstract Field‐effect transistors (FETs) are the main building block of microelectronic devices. For most of the FETs, the conduction channel relies on either n‐type or p‐type semiconductor materials. Recent advances in 2D materials offer an opportunity to form van der Waals heterojunction‐based FETs with novel electrical performance. Here, a MoS2/WSe2 heterojunction–channel FET using h‐BN as insulating layer and Cr/Au metal as the gate, is demonstrated. Two asymmetric Schottky contacts are formed at both sides of MoS2, WSe2 due to electron tunneling effects, work function differences, and Fermi level pinning. Benefiting from that, the authors observe a forward current regulating diode behavior, where the drain current remains unchanged regardless of the drain voltage (VDS) fluctuations and can be modulated by the gate voltage, atmosphere temperature, vacuum pressure, and h‐BN layer thickness. In addition, under higher VDS, heterojunction–channel breakdown induced by the Fowler–Nordheim (F–N) tunneling at the WSe2/h‐BN/metal region, is observed. Furthermore, the transistor demonstrates a reverse rectification behavior with onset voltage linearly depending on the temperature (3 mV T−1). This work paves the way for the potential application of heterojunction–channel FETs for high‐performance current regulator and current rectifier.

A novel Performance Optimized Carrier Stored Trench Gate Bipolar Transistor (CSTBT) with Low Switching Loss has been proposed. By applying a positive DC voltage to the shield gate, the carrier storage effect is enhanced, the hole blocking capability is improved and the conduction loss is reduced. The DC biased shield gate naturally forms inverse conduction channel to speed up turn-on period. Excess holes are conducted away from the device through the hole path to reduce turn-off loss (Eoff). In addition, other parameters including ON-state voltage (Von), blocking characteristic and short circuit performance are also improved. Simulation results demonstrate that our device exhibits a 35.1% and 35.9% decrease in Eoff and turn-on loss (Eon), respectively, in comparison with the conventional shield CSTBT (Con-SGCSTBT). Additionally, our device achieves a short-circuit duration time that is 2.48 times longer. In high-frequency switching applications, device power loss can be reduced by 35%. It should be noted that the additional DC voltage bias is equivalent to the output voltage of the driving circuit, enabling an effective and feasible approach towards high-performance power electronics applications.

Concurrently achieving high energy storage density (ESD) and efficiency has always been a big challenge for electrostatic energy storage capacitors. In this study, we successfully fabricate high-performance energy storage capacitors by using antiferroelectric (AFE) Al-doped Hf0.25Zr0.75O2 (HfZrO:Al) dielectrics together with an ultrathin (1 nm) Hf0.5Zr0.5O2 underlying layer. By optimizing the Al concentration in the AFE layer with the help of accurate controllability of the atomic layer deposition technique, an ultrahigh ESD of 81.4 J cm−3 and a perfect energy storage efficiency (ESE) of 82.9% are simultaneously achieved for the first time in the case of the Al/(Hf + Zr) ratio of 1/16. Meanwhile, both the ESD and ESE exhibit excellent electric field cycling endurance within 109 cycles under 5~5.5 MV cm−1, and robust thermal stability up to 200 °C. Thus, the fabricated capacitor is very promising for on-chip energy storage applications due to favorable integratability with the standard complementary metal–oxide–semiconductor (CMOS) process.

In this paper, a novel scheme for source/drain-first (S/D-first) full bottom dielectric isolation (BDI), i.e., Full BDI_Last, with integration of a sacrificial Si0.5Ge0.5 layer was proposed and demonstrated in a stacked Si nanosheet gate-all-around (NS-GAA) device structure using TCAD simulations. The proposed full BDI scheme flow is compatible with the main process flow of NS-GAA transistor fabrication and provides a large window for process fluctuations, such as the thickness of the S/D recess. It is an ingenious solution to insert the dielectric material under the source, drain and gate regions to remove the parasitic channel. Moreover, because the S/D-first scheme decreases the problem of high-quality S/D epitaxy, the innovative fabrication scheme introduces full BDI formation after S/D epitaxy to mitigate the difficulty of providing stress engineering in the full BDI formation before S/D epitaxy (Full BDI_First). The electrical performance of Full BDI_Last is demonstrated by a 4.78-fold increase in the drive current compared to Full BDI_First. Furthermore, compared to traditional punch through stoppers (PTSs), the proposed Full BDI_Last technology could potentially provide an improved short channel behavior and good immunity against parasitic gate capacitance in NS-GAA devices. For the assessed inverter ring oscillator (RO), applying the Full BDI_Last scheme allows the operating speed to be increased by 15.2% and 6.2% at the same power, or alternatively enables an 18.9% and 6.8% lower power consumption at the same speed compared with the PTS and Full BDI_First schemes, respectively. The observations confirm that the novel Full BDI_Last scheme incorporated into an NS-GAA device can be utilized to enable superior characteristics to benefit the performance of integrated circuits.

In this paper, nanosheet deformation during channel release has been investigated and discussed in Gate-All-Around (GAA) transistors. Structures with different source/drain size and stacked Si nanosheet lengths were designed and fabricated. The experiment of channel release showed that the stress caused serious deformation to suspended nanosheets. With the guidance of the experiment result, based on simulation studies using the COMSOL Multiphysics and Sentaurus tools, it is confirmed that the stress applied on the channel from source/drain plays an important role in nanosheet deformation during the fabrication process. The deformation of Si nanosheets would cause a serious degradation of the device performance due to an inability to control the work function of the metal gate. This study proposed that the uniformly stacked GAA nanosheets structure could be successfully demonstrated with suitable channel stress engineering provided by fitting S/D size and an appropriate channel length. The conclusions provide useful guidelines for future stacked GAA transistors’ design and fabrication.

The effect of the source/drain compressive stress on the mechanical stability of stacked Si nanosheets (NS) during the process of channel release has been investigated. The stress of the nanosheets in the stacking direction increased first and then decreased during the process of channel release by technology computer-aided design (TCAD) simulation. The finite element simulation showed that the stress caused serious deformation of the nanosheets, which was also confirmed by the experiment. This study proposed a novel channel release process that utilized multi-step etching to remove the sacrificial SiGe layers instead of conventional single-step etching. By gradually releasing the stress of the SiGe layer on the nanosheets, the stress difference in the stacking direction before and after the last step of etching was significantly reduced, thus achieving equally spaced stacked nanosheets. In addition, the plasma-free oxidation treatment was introduced in the multi-step etching process to realize an outstanding selectivity of 168:1 for Si0.7Ge0.3 versus Si. The proposed novel process could realize the channel release of nanosheets with a multi-width from 30 nm to 80 nm with little Si loss, unlocking the full potential of gate-all-around (GAA) technology for digital, analog, and radio-frequency (RF) circuit applications.

Floating gate (FG) memory has long erasing time, which limits its application as an electronic synapse in online training. This paper proposes a novel enhanced floating gate memory (EFM) by TCAD simulation. Here, three other structures are simulated just for comparison. The simulation results show that the erasing speed is about 34ns while the other three need the time over 1.8ms, which makes the operation speed of long-term potentiation (LTP) more symmetrical to long-term depression (LTD). In addition, both LTP and LTD are approximately linear in the simulation results. The speed, linearity, and symmetry of weight update are the keys to online training of analog neural networks. These excellent performances indicated a potential application of EFM in analog neuro-inspired computing.

Abstract Synaptic devices are necessary to meet the growing demand for the smarter and more efficient system. In this work, the anisotropic rhenium disulfide (ReS2) is used as a channel material to construct a synaptic device and successfully emulate the long-term potentiation/depression behavior. To demonstrate that our device can be used in a large-scale neural network system, 165 pictures from Yale Face database are selected for evaluation, of which 120 pictures are used for artificial neural network (ANN) training, and the remaining 45 pictures are used for ANN testing. A three-layer ANN containing more than 105 weights is proposed for the face recognition task. Also 120 continuous modulated conductance states are selected to replace weights in our well-trained ANN. The results show that an excellent recognition rate of 100% is achieved with only 120 conductance states, which proves a high potential of our device in the artificial neural network field.

Abstract For advanced Cu interconnect technology, Co films have been widely investigated to serve as the liner and seed layer replacement because of a better wettability to Cu than Ta. In this article, the Co films are grown by plasma-enhanced atomic layer deposition using Co(EtCp)2 as a precursor, and the influences of process parameters on the characteristics of the Co films are elaborately investigated. The results indicate that the process window is 125–225 °C with a growth rate of ~ 0.073 Å/cycle. That is to say, the connection of Et group to Cp ligand can enable a stable film growth at 125 °C, while the corresponding temperature must be higher than 200 °C in terms of Co(Cp)2 and Co(MeCp)2. The deposited films contain N and O elements besides dominant Co and C. Furthermore, the prolongation of the NH3 pulse time significantly enhances the conductivity of the Co film and a low resistivity of 117 μΩ cm can be achieved with a NH3 pulse time of 40 s. The root mean square roughness shows a smaller variation with the deposition temperature and maintains a low value of ~ 0.3 nm, indicative of a flat Co film.

Abstract Artificial synapses are the fundamental of building a neuron network for neuromorphic computing to overcome the bottleneck of the von Neumann system. Based on a low-temperature atomic layer deposition process, a flexible electrical synapse was proposed and showed bipolar resistive switching characteristics. With the formation and rupture of ions conductive filaments path, the conductance was modulated gradually. Under a series of pre-synaptic spikes, the device successfully emulated remarkable short-term plasticity, long-term plasticity, and forgetting behaviors. Therefore, memory and learning ability were integrated to the single flexible memristor, which are promising for the next-generation of artificial neuromorphic computing systems.

A two-dimensional electron gas (2DEG) was formed at the interface of an ultrathin ZnO/Ga2O3 heterostructure deposited by atomic layer deposition (ALD) at 200 °C on a SiO2/Si substrate. It is found that the sheet resistance decreases steeply to ∼104 Ω/□ as the thickness of the ZnO layer increases to a certain extent, and an optimal thickness of the top layer is determined. An ∼50-nm-thick β-phase Ga2O3 layer was formed after annealing at 800 °C, and a 12-nm-thick amorphous ZnO layer was observed by x-ray diffraction and transmission electron microscopy. The oxygen defects were analyzed by x-ray photoelectron spectroscopy. The defect energy levels of oxygen vacancies in Ga2O3 and ZnO thin films were calculated by first-principles simulation, and oxygen vacancies were generated at the interface of the ZnO/Ga2O3 thin film heterostructure to form 2DEG, which is demonstrated experimentally and theoretically. An assumption is proposed that the oxygen vacancy plays a role of the donor of free electrons at the ZnO/Ga2O3 interface because of the small energy level between the oxygen vacancy defect level and conduction band minimum (CBM) of the ZnO layer, which could easily trigger the charge transfer in the interface region. The 2DEG can be realized on the partially ordered microstructure of the Ga2O3 layer. With the assistance of the ALD technique, the thickness of the ZnO/Ga2O3 heterostructure can be as thin as ∼65 nm, which is favorable for devices of stack or ultrathin structures. Moreover, the low temperature deposition by ALD can be adopted for flexible or stretchable devices.

A new S/D trimming process was proposed to significantly reduce the parasitic RC of gate-all-around (GAA) nanosheet transistors (NS-FETs) while retaining the channel stress from epitaxy S/D stressors at most. With optimized S/D trimming, the 7-stage ring oscillator (RO) gained up to 27.8% improvement of delay with the same power consumption, for a 3-layer stacked GAA NS-FETs. Furthermore, the proposed S/D trimming technology could enable more than 4-layer vertical stacking of nanosheets for GAA technology extension beyond 3 nm CMOS technology.

In the tide of artificial intelligence evolution, the demand for data computing has exploded, and the von Neumann architecture computer with separate memory and computing units require cumbersome data interaction, which leads to serious degradation in performance and efficiency. Biologically inspired neuromorphic engineering performs digital/analog computations in memory, with massive parallelism and high energy efficiency, making it a promising candidate to get out of the woods. Memristive device‐based artificial synapses and neurons are building blocks to form hardware neural networks for computing acceleration. In addition, it enables the implementation of integrated bionic perception and motion systems to mimic the human peripheral nervous system for information sensing and processing. Herein, the biological basis and inspiration are described first, and the memristive synapses and circuit‐emulation neurons used for neuromorphic engineering are addressed and evaluated as well as the mechanisms. The computational acceleration and bionic perception motion integration of neuromorphic systems are discussed. Finally, the challenges and opportunities for neuromorphic engineering to accelerate computation and enrich biomimetic perception motion functions are prospected, and it is hoped that light is shed on future advances.

Recently, hafnium oxide (HfO2)-based ferroelectric materials have achieved phenomenal success in next-generation nonvolatile memory applications. In this study, we fabricated Hf0.5Zr0.5O2 (HZO) ferroelectric capacitors and back-gate field-effect transistors (FETs) with few-layered molybdenum disulfide (MoS2) nanosheets as the channel and a ferroelectric Hf0.5Zr0.5O2 film as the gate dielectric. Good dielectric and ferroelectric properties have been observed from the HZO film fabricated with atomic layer deposition-based techniques. The MoS2–HZO ferroelectric FETs (FeFETs) have exhibited excellent performance including ferroelectric polarization switching with a high on/off ratio and negligible degradation in endurance and retention properties. Our results shown here suggest that MoS2–HZO FeFETs can be a promising alternative for next-generation nonvolatile memories.

Abstract With Moore’s law closing to its physical limit, traditional von Neumann architecture is facing a challenge. It is expected that the computing in-memory architecture-based resistive random access memory (RRAM) could be a potential candidate to overcome the von Neumann bottleneck problem of traditional computers [Backus, J, Can programming be liberated from the von Neumann style?, 1977]. In this work, HfAlOx-based RRAM which is compatible with CMOS technology was fabricated by an atomic layer deposition (ALD) process. Metal Ag and TaN are selected as top electrodes (TE). Experiments show that the Ag/HfAlOx/Pt device has demonstrated advantages as a memory-computing device because of the low set voltage (0.33~0.6 V) which means low power consumption and good uniformity. Based on a Ag/HfAlOx/Pt structure, IMP logic was implemented at high speed by applying a 100-ns high-frequency low-voltage pulse (0.3 V and 0.6 V). After two steps of IMP implementation, NAND can also be obtained.