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1. Engineered SiC materials for power technologies

Author

Schwarzenbach, W., primary, Rouchier, S., additional, Berre, G., additional, Boulet, R., additional, Ledoux, O., additional, Cela, E., additional, Drouin, A., additional, Chapelle, A., additional, Monnoye, S., additional, Biard, H., additional, Alassaad, K., additional, Viravaux, L., additional, Mohamed, N. Ben, additional, Radisson, D., additional, Picun, G., additional, Lavaitte, G., additional, Bouville-Lallart, A., additional, Roi, J., additional, Widiez, J., additional, Abadie, K., additional, Rolland, E., additional, Fournel, F., additional, Gelineau, G., additional, Mazen, F., additional, Moulin, A., additional, Moulin, C., additional, Delprat, D., additional, Daval, N., additional, Odoul, S., additional, Sandri, P., additional, and Maleville, C., additional

Published
2022
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4. SmartSiC™ for Manufacturing of SiC Power Devices

Author

Daval, N., primary, Drouin, A., additional, Biard, H., additional, Viravaux, L., additional, Radisson, D., additional, Rouchier, S., additional, Gaudin, G., additional, Widiez, J., additional, Allibert, F., additional, Rolland, E., additional, Vladimirova, K., additional, Gelineau, G., additional, Troutot, N., additional, Navone, C., additional, Berre, G., additional, Bosch, D., additional, Leow, Y.L, additional, Duboust, A., additional, Bethoux, J-M., additional, Boulet, R., additional, Chapelle, A., additional, Cela, E., additional, Lavaitte, G., additional, Bouville-Lallart, A., additional, Bhargava, S., additional, Schwarzenbach, W., additional, Maddalon, C., additional, Radu, I., additional, Odoul, S., additional, Delprat, D., additional, Bonnin, O., additional, and Maleville, C., additional

Published
2022
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6. Contributor contact details

Author

Kononchuk, O., primary, Nguyen, B.-Y., additional, Moriceau, H., additional, Fournel, F., additional, Rieutord, F., additional, Cristoloveanu, S., additional, Ghosh, S., additional, Burnett, D., additional, Andrieu, F., additional, Colinge, J.P., additional, Cheng, B., additional, Brown, A., additional, Towie, E., additional, Daval, N., additional, Bourdelle, K.K., additional, Asenov, A., additional, Markov, S., additional, Zain, A.S.M., additional, Khazhinsky, M.G., additional, Raskin, J.-P., additional, Emam, M., additional, Sugii, N., additional, Tan, C.S., additional, Bogaerts, W., additional, Selvaraja, S.K., additional, and Mori, K., additional

Published
2014
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10. Engineering strained silicon on insulator wafers with the Smart Cut TM technology

Author

Ghyselen, B., Hartmann, J.-M., Ernst, T., Aulnette, C., Osternaud, B., Bogumilowicz, Y., Abbadie, A., Besson, P., Rayssac, O., Tiberj, A., Daval, N., Cayrefourq, I., Fournel, F., Moriceau, H., Di Nardo, C., Andrieu, F., Paillard, V., Cabié, M., Vincent, L., Snoeck, E., Cristiano, F., Rocher, A., Ponchet, A., Claverie, A., Boucaud, P., Semeria, M.-N., Bensahel, D., Kernevez, N., and Mazure, C.

Published
2004
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11. Monolithic III-V/Si Integration

Author

Fitzgerald, Eugene A., primary, Bulsara, M. T., additional, Bai, Y., additional, Cheng, C., additional, Liu, W. K., additional, Lubyshev, D., additional, Fastenau, J. M., additional, Wu, Y., additional, Urtega, M., additional, Ha, W., additional, Bergman, J., additional, Brar, B., additional, Drazek, C., additional, Daval, N, additional, Leterte, F., additional, Hoke, W. E., additional, LaRoche, J. R., additional, Herrick, Katherine J., additional, and Kazior, T. E., additional

Published
2019
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13. Strained Silicon on Insulator wafers made by the Smart Cut™ technology

Author

Ghyselen, B., Bogumilowicz, Y., Aulnette, C., Abbadie, A., Osternaud, B., Besson, P., Daval, N., Andrieu, F., Cayrefourq, I., Moriceau, H., Ernst, T., Tiberj, A., Rayssac, O., Blondeau, B., Mazure, C., Lagahe-Blanchard, C., Pocas, S., Cartier, A.-M., Hartmann, J.-M., Leduc, P., Nardo, C. Di, Lugand, J.-F., Fournel, F., Semeria, M.-N., Kernevez, N., Campidelli, Y., Kermarrec, O., Morand, Y., Rivoire, M., Bensahel, D., Paillard, V., Vincent, L., Claverie, A., and Boucaud, P.

Published
2003
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16. Modeling and direct extraction of band offset induced by stress engineering in silicon-on-insulator metal-oxide-semiconductor field effect transistors: Implications for device reliability.

Author

Garros, X., Rochette, F., Andrieu, F., Baudot, S., Reimbold, G., Aulnette, C., Daval, N., and Boulanger, F.

Subjects
SILICON-on-insulator technology, METAL oxide semiconductor field-effect transistors, RELIABILITY in engineering, SILICON, STRAINS & stresses (Mechanics)
Abstract

We study the performance and reliability of metal-oxide-semiconductor field effect transistors fabricated on strained and unstrained silicon on insulator substrates, sSOI and SOI, respectively. The biaxial strain strongly enhances electron mobility and changes the threshold voltage, Vt, of the devices. We show that the Vt shift in the “ideal SOI structures,” i.e., with no oxide defects, is due to the conduction band offset induced by strain ΔEc and therefore can be used for the stress monitoring. The biaxial strain also affects the gate oxide leakage current. A new method to extract ΔEc from the leakage current measurements is proposed. This method is less sensitive to the gate oxide defects than the one based on Vt shift. A complete modeling of leakage current in SOI and sSOI transistors is presented. Due to the strong confinement at the Si/SiO2 interface the leakage current in the Fowler–Nordheim (FN) regime mainly results from electron tunneling in the subband associated to the ground level E0Δ2. A simple FN model is therefore used to extract the ΔEc from the variation in the effective barrier height [lowercase_phi_synonym]bFN between the Si film and the SiO2 oxide. Based on this experimental and accurate extraction of ΔEc, realistic values of the deformation potentials in Si are finally proposed. The final part of the paper discusses the different implications of this band offset ΔEc on device performance and reliability. It is demonstrated that strained devices exhibit reduced leakage currents and a superior reliability, in terms of interface state density and oxide breakdown, than unstrained devices. [ABSTRACT FROM AUTHOR]

Published
2009
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17. Splitting kinetics of Si0.8Ge0.2 layers implanted with H or sequentially with He and H.

Author

Nguyen, Phuong, Bourdelle, K. K., Aulnette, C., Lallement, F., Daix, N., Daval, N., Cayrefourcq, I., Letertre, F., Mazuré, C., Bogumilowicz, Y., Tauzin, A., Deguet, C., Cherkashin, N., and Claverie, A.

Subjects
ION implantation, ION bombardment, PARTICLES (Nuclear physics), TRANSMISSION electron microscopy, BACKSCATTERING, SCATTERING (Physics), CHANNELING (Physics)
Abstract

We have performed systematic measurements of the splitting kinetics induced by H-only and He+H sequential ion implantation into relaxed Si0.8Ge0.2 layers and compared them with the data obtained in Si. For H-only implants, Si splits faster than Si0.8Ge0.2. Sequential ion implantation leads to faster splitting kinetics than H-only in both materials and is faster in Si0.8Ge0.2 than in Si. We have performed secondary ion mass spectrometry, Rutherford backscattering spectroscopy in channeling mode, and transmission electron microscopy analyses to elucidate the physical mechanisms involved in these splitting phenomena. The data are discussed in the framework of a simple phenomenological model in which vacancies play an important role. [ABSTRACT FROM AUTHOR]

Published
2008
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18. Splitting kinetics of [Si.sub.0.8][Ge.sub.0.2] layers implanted with H or sequentially with He and H

Author

Nguyen, Phuong, Bourdelle, K.K., Aulnette, C., Lallement, F., Daix, N., Daval, N., Cayrefourcq, F., Mazure, C., Bogumilowicz, Y., Tauzin, A., Deguet, C., Cherkashin, N., and Claverie, A.

Subjects
Germanium -- Mechanical properties, Germanium -- Electric properties, Helium -- Thermal properties, Hydrogen -- Thermal properties, Silicon-on-isolator -- Mechanical properties, Silicon-on-isolator -- Electric properties, X-rays -- Diffraction, X-rays -- Usage, Physics
Abstract

The splitting kinetics of [Si.sub.0.8][Ge.sub.0.2] substrates implanted with H-only or sequentially implanted with He and then with H is studied. The extended physical characterization of the implanted and annealed substrates has provided insights into the mechanism of splitting in [Si.sub.0.8][Ge.sub.0.2].

Published
2008

20. Strained FDSOI CMOS technology scalability down to 2.5nm film thickness and 18nm gate length with a TiN/HfO2 gate stack

Author

Barral, V., Poiroux, T., Andrieu, F., Buj-Dufournet, C., Faynot, O., Ernst, T., Brevard, L., Fenouillet-Beranger, C., Lafond, D., Hartmann, Jm, Vidal, V., Allain, F., Daval, N., Cayrefourcq, I., Tosti, L., Daniela Munteanu, Autran, Jl, Deleonibus, S., Institut des Matériaux, de Microélectronique et des Nanosciences de Provence (IM2NP), Université de Toulon (UTLN)-Centre National de la Recherche Scientifique (CNRS)-Aix Marseille Université (AMU), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), and Aix Marseille Université (AMU)-Université de Toulon (UTLN)-Centre National de la Recherche Scientifique (CNRS)

Subjects
[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

IEEE International Electron Devices Meeting, Washington, DC, DEC 10-12, 2007; International audience; Scalability of both unstrained and strained FDSOI CMOSFETs is explored for the first time down to 2.5nm film thickness and 18nm gate length with HfO2/TiN gate stack. Off-state currents in the pA/mu m range are achieved for 18nm short and 3.8nm thin MOSFETs thanks to outstanding electrostatic control: 67mV/dec subthreshold swing and 75mV/V DIBL. For such thin bodies, the buried oxide fringing field limitation on DIBL is experimentally evidenced and quantified for the first time. Furthermore, we demonstrate strain induced ION gain as high as 40% on the shortest transistors. An in-depth analysis of this gain as a function of the film thickness is carried out through mobility and ballisticity extractions.

Published
2007
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21. SiC Power Devices on QUASIC and SiCOI Smart-Cut® Substrates: First Demonstrations

Author

Letertre, Fabrice, Daval, N., Templier, Francois, Bano, Edwige, Planson, Dominique, Di Cioccio, Lea, Jalaguier, E., Bluet, Jean Marie, Billon, Thierry, Madar, Roland, Chante, Jean-Pierre, SOITEC, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique (IMEP), Université Joseph Fourier - Grenoble 1 (UJF)-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), Centre de génie électrique de Lyon (CEGELY), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS), Ampère, Département Energie Electrique (EE), Ampère (AMPERE), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)-École Centrale de Lyon (ECL), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), Laboratoire de physique de la matière (LPM), Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Université de Lyon-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS), Laboratoire des matériaux et du génie physique (LMGP ), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Institut de Chimie du CNRS (INC)-Centre National de la Recherche Scientifique (CNRS)

Subjects
SOI, SiC, QUASIC, Smart-Cut, CVD epitaxy, [SPI.NRJ]Engineering Sciences [physics]/Electric power, wafer bonding, Schottky diodes, SICOI
Abstract

Wafer bonding technologies have been recognized to provide new substrates structures suitable for the development of Si power devices. Among the multiple examples that could be listed, the possibility to generate PN junctions without thick epitaxial growth and lateral devices onto dielectrically isolated substrates such as SOI (Silicon On Insulator) are significant examples of the interest proposed by wafer bonding. Thin film substrates obtained with the Smart-Cut® technology such as SiCOI (SiC On Insulator) substrates for lateral devices and QUASIC substrates for vertical power devices have already been demonstrated. In this article, we review the recent developments in the field of SiC power devices using these two kinds of SiC Smart-Cut substrates. Lateral and vertical Schottky diodes have been processed onto SiCOI and QUASIC substrates as a demonstration of feasibility. Simulations, results and prospects are presented in this article.

Published
2003
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22. SiC On Insulator as substrate for power Schottky diodes

Author

Daval, N., Templier, F, Letertre, F., Planson, Dominique, Cioccio, Léa, Raynaud, Christophe, Chante, Jean-Pierre, Billon, T., Planson, Dominique, Silicon-on-Insulator Technologies (SOITEC), Parc Technologique des Fontaines, Centre de génie électrique de Lyon (CEGELY), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), and Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)

Subjects
Smart-cut, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Schottky diodes, Wafer bonding, SiCOI, [SPI.NRJ] Engineering Sciences [physics]/Electric power
Abstract

International audience; Recently INFINEON and other companies announced the market introduction of their SiC Schottky rectifiers in the range of 600 V several amperes. This announcement allows the design of power electronic systems with a cooling effort drastically reduced than required before, which is a great improvement for electronics in terms of cost and efficiency. However SiC components are still checked by an expensive substrate supplying and by the small 3 inches size of the SiC wafers.SiCOI substrate presents the capability of large sized handle wafers, allowing the utilization of 4,6 or 8 inches facilities. In addition the fabrication of numerous SiCOI substrates requires a single SiC substrate as illustrated in figure 1. This later point should make SiCOI a low cost SiC substrate. The purpose of this article is to give the first electrical characteristics of a Schottky rectifier on that promising substrate.

Published
2002

23. Thermal considerations for advanced SOI substrates designed for III-V/Si heterointegration

Author

Massachusetts Institute of Technology. Department of Materials Science and Engineering, Bulsara, Mayank, Fitzgerald, Eugene A., Yang, N., Liu, W. K., Lubyshev, D., Fastenau, J. M., Wu, Y., Urteaga, M., Ha, W., Bergman, J., Brar, B., Drazek, C., Daval, N., Benaissa, L., Augendre, E., Hoke, William E., LaRoche, J. R., Herrick, K. J., Kazior, T. E., Massachusetts Institute of Technology. Department of Materials Science and Engineering, Bulsara, Mayank, Fitzgerald, Eugene A., Yang, N., Liu, W. K., Lubyshev, D., Fastenau, J. M., Wu, Y., Urteaga, M., Ha, W., Bergman, J., Brar, B., Drazek, C., Daval, N., Benaissa, L., Augendre, E., Hoke, William E., LaRoche, J. R., Herrick, K. J., and Kazior, T. E.

Abstract

Silicon-on-lattice engineered substrates (SOLES) are SOI substrates with embedded Ge layers that facilitate III-V compound integration for advanced integrated circuits. The new materials integration scheme in SOLES requires the analysis of its thermal stability and diffusion barrier properties. In this study, we report on the successful monolithic integration of CMOS/III-V transistors with a reduced CMOS thermal budget. We further investigated the ultimate thermal budget limits for the SOLES platform. We demonstrated a new SOLES structure incorporating a SiNx interlayer, which adds greater integration flexibility for future circuit applications., United States. Defense Advanced Research Projects Agency (COSMOS Program contract N00014-07-C-0629)

Published
2012

24. A high performance differential amplifier through the direct monolithic integration of InP HBTs and Si CMOS on silicon substrates

Author

Massachusetts Institute of Technology. Materials Processing Center, Bulsara, Mayank, Fitzgerald, Eugene A., LaRoche, J. R., Kazior, T. E., Lubyshev, D., Fastenau, J. M., Liu, W. K., Urteaga, M., Ha, W., Bergman, J., Choe, M. J., Smith, D., Clark, D., Thompson, R., Drazek, C., Daval, N., Benaissa, L., Augendre, E., Massachusetts Institute of Technology. Materials Processing Center, Bulsara, Mayank, Fitzgerald, Eugene A., LaRoche, J. R., Kazior, T. E., Lubyshev, D., Fastenau, J. M., Liu, W. K., Urteaga, M., Ha, W., Bergman, J., Choe, M. J., Smith, D., Clark, D., Thompson, R., Drazek, C., Daval, N., Benaissa, L., and Augendre, E.

Abstract

We present results on the direct monolithic integration of III-V devices and Si CMOS on a silicon substrate. InP HBTs (0.5 times 5 um2 emitter) with ft and fmax > 200 GHz were grown directly in windows adjacent to CMOS transistors on silicon template wafers or SOLES (Silicon on Lattices Engineered Substrates). A BCB based multilayer interconnect process was used to interconnect the InP HBT and Si CMOS to create a differential amplifier demonstration circuit. The heterogeneously integrated differential amplifier serves as the building block for high speed, low power dissipation mixed signal circuits such as ADCs and DACs., United States. Defense Advanced Research Projects Agency. COSMOS Program (Contract Number N00014-07-C-0629)

Published
2010

25. A high performance differential amplifier through the direct monolithic integration of InP HBTs and Si CMOS on silicon substrates

Author

MIT Materials Research Laboratory, Bulsara, Mayank, Fitzgerald, Eugene A., LaRoche, J. R., Kazior, T. E., Lubyshev, D., Fastenau, J. M., Liu, W. K., Urteaga, M., Ha, W., Bergman, J., Choe, M. J., Smith, D., Clark, D., Thompson, R., Drazek, C., Daval, N., Benaissa, L., Augendre, E., MIT Materials Research Laboratory, Bulsara, Mayank, Fitzgerald, Eugene A., LaRoche, J. R., Kazior, T. E., Lubyshev, D., Fastenau, J. M., Liu, W. K., Urteaga, M., Ha, W., Bergman, J., Choe, M. J., Smith, D., Clark, D., Thompson, R., Drazek, C., Daval, N., Benaissa, L., and Augendre, E.

Abstract

We present results on the direct monolithic integration of III-V devices and Si CMOS on a silicon substrate. InP HBTs (0.5 times 5 um2 emitter) with ft and fmax > 200 GHz were grown directly in windows adjacent to CMOS transistors on silicon template wafers or SOLES (Silicon on Lattices Engineered Substrates). A BCB based multilayer interconnect process was used to interconnect the InP HBT and Si CMOS to create a differential amplifier demonstration circuit. The heterogeneously integrated differential amplifier serves as the building block for high speed, low power dissipation mixed signal circuits such as ADCs and DACs., United States. Defense Advanced Research Projects Agency. COSMOS Program (Contract Number N00014-07-C-0629)

Published
2010

26. Progress and challenges in the direct monolithic integration of III-V devices and Si CMOS on silicon substrates

Author

Massachusetts Institute of Technology. Department of Materials Science and Engineering, Fitzgerald, Eugene A, Fitzgerald, Eugene A., Bulsara, Mayank, Augendre, E., Benaissa, L., Daval, N., Drazek, C., Thompson, R., Clark, D., Smith, D., Choe, M. J., Bergman, J., Ha, W., Urteaga, M., Liu, W. K., Fastenau, J. M., Lubyshev, D., LaRoche, J. R., Kazior, T. E., Massachusetts Institute of Technology. Department of Materials Science and Engineering, Fitzgerald, Eugene A, Fitzgerald, Eugene A., Bulsara, Mayank, Augendre, E., Benaissa, L., Daval, N., Drazek, C., Thompson, R., Clark, D., Smith, D., Choe, M. J., Bergman, J., Ha, W., Urteaga, M., Liu, W. K., Fastenau, J. M., Lubyshev, D., LaRoche, J. R., and Kazior, T. E.

Abstract

We present results on the direct monolithic integration of III-V devices and Si CMOS on a silicon substrate. Through optimization of device fabrication and material growth processes III-V devices with electrical performance comparable to devices grown on native III-V substrates were grown directly in windows adjacent to CMOS transistors on silicon template wafers or SOLES (Silicon on Lattices Engineered Substrates). While the results presented here are for InP HBTs, our direct heterogeneously integration approach is equally applicable to other III-V electronic (FETs, HEMTs) and opto-electronic (photodiodes, VSCLS) devices and opens the door to a new class of highly integrated, high performance, mixed signal circuits., Defence Advanced Research Projects Agency COSMOS Program (Contract Number N00014-07-C-0629)

Published
2010

28. Comparison between <100> and <110> oriented channels in highly strained FDSOI pMOSFETs

Author

Morvan, S., primary, Andrieu, F., additional, Nguyen, P., additional, Hartmann, J.-M., additional, Casse, M., additional, Tabone, C., additional, Toffoli, A., additional, Allain, F., additional, Schwarzenbach, W., additional, Ghibaudo, G., additional, Nguyen, B.-Y., additional, Daval, N., additional, Haond, M., additional, Poiroux, T., additional, and Faynot, O., additional

Published
2012
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29. Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS

Author

Khakifirooz, A., primary, Cheng, K., additional, Nagumo, T., additional, Loubet, N., additional, Adam, T., additional, Reznicek, A., additional, Kuss, J., additional, Shahrjerdi, D., additional, Sreenivasan, R., additional, Ponoth, S., additional, He, H., additional, Kulkarni, P., additional, Liu, Q., additional, Hashemi, P., additional, Khare, P., additional, Luning, S., additional, Mehta, S., additional, Gimbert, J., additional, Zhu, Y., additional, Zhu, Z., additional, Li, J., additional, Madan, A., additional, Levin, T., additional, Monsieur, F., additional, Yamamoto, T., additional, Naczas, S., additional, Schmitz, S., additional, Holmes, S., additional, Aulnette, C., additional, Daval, N., additional, Schwarzenbach, W., additional, Nguyen, B.-Y., additional, Paruchuri, V., additional, Khare, M., additional, Shahidi, G., additional, and Doris, B., additional

Published
2012
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32. Enabling the use of ion implantation for ultra-thin FDSOI n-MOSFETs

Author

Vinet, M., primary, Kumar, A., additional, Grenouillet, L., additional, Ponoth, S., additional, Posseme, N., additional, Destefanis, V., additional, Mehta, S., additional, Loubet, N., additional, Le Tiec, Y., additional, Monsieur, F., additional, Liu, Q., additional, Daval, N., additional, Doris, B., additional, Faynot, O., additional, and Poiroux, T., additional

Published
2012
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33. Ultra-thin SOI for 20nm node and beyond

Author

Aulnette, C., primary, Schwarzenbach, W., additional, Daval, N., additional, Bonnin, O., additional, Nguyen, B.-Y., additional, Mazure, C., additional, Maleville, C., additional, Cheng, K., additional, Ponoth, S., additional, Khakifirooz, A., additional, Hook, T., additional, and Doris, B., additional

Published
2011
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34. Dual channel and strain for CMOS co-integration in FDSOI device architecture

Author

Le Royer, C., primary, Casse, M., additional, Andrieu, F., additional, Weber, O., additional, Brevard, L., additional, Perreau, P., additional, Damlencourt, J.-F., additional, Baudot, S., additional, Tabone, C., additional, Allain, F., additional, Scheiblin, P., additional, Rauer, C., additional, Hutin, L., additional, Figuet, C., additional, Aulnette, C., additional, Daval, N., additional, Nguyen, B.-Y., additional, and Bourdelle, K. K., additional

Published
2010
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35. Thermal considerations for advanced SOI substrates designed for III-V/Si heterointegration

Author

Yang, N., primary, Bulsara, M. T., additional, Fitzgerald, E. A., additional, Liu, W.K., additional, Lubyshev, D., additional, Fastenau, J.M., additional, Wu, Y., additional, Urteaga, M., additional, Ha, W., additional, Bergman, J., additional, Brar, B., additional, Drazekd, C., additional, Daval, N., additional, Benaissa, L., additional, Augendre, E., additional, Hoke, W.E., additional, LaRoche, J.R., additional, Herrick, K.J., additional, and Kazior, T.E., additional

Published
2009
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36. A high performance differential amplifier through the direct monolithic integration of InP HBTs and Si CMOS on silicon substrates

Author

Kazior, T.E., primary, LaRoche, J.R., additional, Lubyshev, D., additional, Fastenau, J. M., additional, Liu, W. K., additional, Urteaga, M., additional, Ha, W., additional, Bergman, J., additional, Choe, M. J., additional, Bulsara, M. T., additional, Fitzgerald, E. A., additional, Smith, D., additional, Clark, D., additional, Thompson, R., additional, Drazek, C., additional, Daval, N., additional, Benaissa, L., additional, and Augendre, E., additional

Published
2009
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37. Progress and challenges in the direct monolithic integration of III–V devices and Si CMOS on silicon substrates

Author

Kazior, T.E., primary, LaRoche, J.R., additional, Lubyshev, D., additional, Fastenau, J. M., additional, Liu, W. K., additional, Urteaga, M., additional, Ha, W., additional, Bergman, J., additional, Choe, M. J., additional, Bulsara, M. T., additional, Fitzgerald, E. A., additional, Smith, D., additional, Clark, D., additional, Thompson, R., additional, Drazek, C., additional, Daval, N., additional, Benaissa, L., additional, and Augendre, E., additional

Published
2009
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38. High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding

Author

Weber, O., primary, Faynot, O., additional, Andrieu, F., additional, Buj-Dufournet, C., additional, Allain, F., additional, Scheiblin, P., additional, Foucher, J., additional, Daval, N., additional, Lafond, D., additional, Tosti, L., additional, Brevard, L., additional, Rozeau, O., additional, Fenouillet-Beranger, C., additional, Marin, M., additional, Boeuf, F., additional, Delprat, D., additional, Bourdelle, K., additional, Nguyen, B.-Y., additional, and Deleonibus, S., additional

Published
2008
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39. Engineering Substrates for 3D Integration of III-V and CMOS

Author

Herrick, Katherine J., primary, Kazior, T. E., additional, LaRoche, J. R., additional, Liu, A W., additional, Lubyshev, D., additional, Fastenau, J. M., additional, Urteaga, M., additional, Ha, W., additional, Bergman, J., additional, Brar, B., additional, Bulsara, M. T., additional, Fitzgerald, Eugene A., additional, Clark, D., additional, Smith, D, additional, Thompson, R. F., additional, Daval, N, additional, and Celler, George K., additional

Published
2008
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40. Monolithic III-V/Si integration

Author

Fitzgerald, E.A., primary, Bulsara, M.T., additional, Bai, Y., additional, Cheng, C., additional, Liu, W.K., additional, Lubyshev, D., additional, Fastenau, J.M., additional, Wu, Y., additional, Urtega, M., additional, Ha, W., additional, Bergman, J., additional, Brar, B., additional, Drazek, C., additional, Daval, N., additional, Letertre, F., additional, Hoke, W.E., additional, LaRoche, J.R., additional, Herrick, K.J., additional, and Kazior, T.E., additional

Published
2008
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41. Strained FDSOI CMOS technology scalability down to 2.5nm film thickness and 18nm gate length with a TiN/HfO2 gate stack

Author

Barral, V., primary, Poiroux, T., additional, Andrieu, F., additional, Buj-Dufournet, C., additional, Faynot, O., additional, Ernst, T., additional, Brevard, L., additional, Fenouillet-Beranger, C., additional, Lafond, D., additional, Hartmann, J.M., additional, Vidal, V., additional, Allain, F., additional, Daval, N., additional, Cayrefourcq, I., additional, Tosti, L., additional, Munteanu, D., additional, Autran, J.L., additional, and Deleonibus, S., additional

Published
2007
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42. Additivity between sSOI- and CESL-induced nMOSFETs Performance Boosts

Author

Andrieu, F., primary, Allain, F., additional, Buj-Dufournet, C., additional, Faynot, O., additional, Rochette, F., additional, Casse, M., additional, Delaye, V., additional, Aussenac, F., additional, Tosti, L., additional, Maury, P., additional, Vandroux, L., additional, Daval, N., additional, Cayrefourcq, I., additional, and Deleonibus, S., additional

Published
2007
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43. Strained Silicon On Insulator wafers made by the Smart Cut™ technology

Author

Ghyselen, B., primary, Bogumilowicz, Y., additional, Aulnette, C., additional, Abbadie, A., additional, Osternaud, B., additional, Besson, P., additional, Daval, N., additional, Andrieu, F., additional, Cayrefourq, I., additional, Moriceau, H., additional, Ernst, T., additional, Tiberj, A., additional, Rayssac, O., additional, Blondeau, B., additional, Mazure, C., additional, Lagahe-Blanchard, C., additional, Pocas, S., additional, Cartier, A.-M., additional, Hartmann, J.-M., additional, Leduc, P., additional, Nardo, C. Di, additional, Lugand, J.-F., additional, Fournel, F., additional, Semeria, M.-N., additional, Kernevez, N., additional, Campidelli, Y., additional, Kermarrec, O., additional, Morand, Y., additional, Rivoire, M., additional, Bensahel, D., additional, Paillard, V., additional, Vincent, L., additional, Claverie, A., additional, and Boucaud, P., additional

Published
2004
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44. New layer transfers obtained by the SmartCut process

Author

Moriceau, H., primary, Fournel, F., additional, Aspar, B., additional, Bataillou, B., additional, Beaumont, A., additional, Morales, C., additional, Cartier, A. M., additional, Pocas, S., additional, Lagahe, C., additional, Jalaguier, E., additional, Soubie, A., additional, Biasse, B., additional, Sousbie, N., additional, Sartori, S., additional, Michaud, J. F., additional, Letertre, F., additional, Rayssac, O., additional, Cayrefourcq, I., additional, Richtarch, C., additional, Daval, N., additional, Aulentte, C., additional, Akatsu, T., additional, Osternaud, B., additional, Ghyselen, B., additional, and Mazuré, C., additional

Published
2003
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47. Monolithic III-V/Si Integration

Author

Fitzgerald, Eugene A., Daval, N, and Herrick, Katherine J.

Abstract

We summarize our work on creating substrate platforms, processes, and devices for the monolithic integration of silicon CMOS circuits with III-V optical and electronic devices. Visible LEDs and InP HBTs have been integrated on silicon materials platforms that lend themselves to process integration within silicon fabrication facilities. We also summarize research on tensile Ge, which could be a high mobility material for III-V MOS, and research on an in-situ MOCVD Al2O3/GaAs process for III-V MOS.

Published
2008

49. High Ge content Si / SiGe heterostructures for microelectronics and optoelectronics purposes

Author

Bogumilowicz, Y., Hartmann, J. M., Damlencourt, J. F., Vandelle, B., Abbadie, A., Papon, A. -M, Rolland, G., Holliger, P., Di Nardo, C., Besson, P., thomas ernst, Billon, T., Aulnette, C., Daval, N., Rayssac, O., Ghyselen, B., Cherkashin, N., Claverie, A., Cluzel, B., Calvo, V., Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Science et Ingénierie des Matériaux et Procédés (SIMaP), Université Joseph Fourier - Grenoble 1 (UJF)-Centre National de la Recherche Scientifique (CNRS)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut de Chimie du CNRS (INC)-Institut National Polytechnique de Grenoble (INPG), SOITEC, Matériaux et dispositifs pour l'Electronique et le Magnétisme (CEMES-MEM), Centre d'élaboration de matériaux et d'études structurales (CEMES), Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut de Chimie de Toulouse (ICT-FR 2599), Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut de Recherche pour le Développement (IRD)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut de Chimie du CNRS (INC)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut de Recherche pour le Développement (IRD)-Institut de Chimie du CNRS (INC)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université Toulouse III - Paul Sabatier (UT3), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA), Silicon Nanoelectronics Photonics and Structures (SiNaps), PHotonique, ELectronique et Ingénierie QuantiqueS (PHELIQS), Université Grenoble Alpes [2016-2019] (UGA [2016-2019])-Institut de Recherche Interdisciplinaire de Grenoble (IRIG), Direction de Recherche Fondamentale (CEA) (DRF (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Direction de Recherche Fondamentale (CEA) (DRF (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])-Institut de Recherche Interdisciplinaire de Grenoble (IRIG), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Institut de Chimie du CNRS (INC)-Centre National de la Recherche Scientifique (CNRS), Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut de Chimie de Toulouse (ICT), Institut de Recherche pour le Développement (IRD)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut de Chimie du CNRS (INC)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Institut de Recherche pour le Développement (IRD)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Institut de Chimie du CNRS (INC)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS), Laboratoire de thermodynamique et physico-chimie métallurgiques (LTPCM), and Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)

Subjects
[PHYS]Physics [physics]
Abstract

International audience; SiGe virtual substrates grown by RP-CVD onto Si(001) substrates are characterized by a macroscopic degree of strain relaxation R = 97.2 ± 1.2%, threading dislocations densities as low as 4×105 cm -2 and rather smooth surfaces (rms roughness: 2 - 5 nm). Such virtual substrates have been used as templates for the formation of SiGe-On-Insulator structures (on which we have studied the specifics of Si and SiGe re-epitaxy). We have also grown Ge thick layers directly onto Si(001). Tensile-strained (R = 107%), smooth (rms ∼ 1 nm) Ge layers with a low threading dislocation density (6×106 cm-2) are obtained that are characterized by high absorption coefficients: A = 10000 cm-1 @ 1.3μm and 4500 cm-1 @ 1.55μm. Finally, we have obtained dense, narrowly size-distributed Ge islands that, when integrated into {Ge quantum dots / Si spacer} stacks, emit light at 1520 nm (PL @ 10K) and are characterized by A ∼ 70 cm-1 in-between 1.2 and 1.7 μm.

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