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Quantum Dot Cellular Automata (QCA) and reversible logic have emerged as promising alternatives to conventional CMOS technology, offering several advantages, such as ultra-dense structures and ultra-low-power consumption. Among the crucial components of processors, the Arithmetic Logic Unit (ALU) has witnessed significant advancements in reversible computing, leading to energy-efficient and high-speed computing systems, particularly beneficial for Digital Signal Processing (DSP) applications. Conventional ALUs, reliant on irreversible logic, encounter energy inefficiencies due to information loss during computations, resulting in increased power consumption. Moreover, they may face limitations in processing speed, impacting real-time processing capabilities, especially for complex DSP tasks involving intensive arithmetic and logic operations. In response to these challenges, a research paper presents a pioneering approach, proposing a novel reversible ALU design using QCA nanotechnology. The proposed design ingeniously incorporates Modified Fredkin (MF) gates, and a coplanar reversible full adder based on the HNG gate, skillfully leveraging the unique features of QCA nanotechnology to optimize the ALU's energy-efficient and high-speed performance for DSP applications. This revolutionary QCA reversible ALU comprises 330 QCA cells arranged in a compact 0.41 μm2 area, skillfully realized through the coplanar clock-zone-based crossover approach. Its core computational elements, the three MF gates, and the innovative coplanar reversible full adder empower the ALU to execute a remarkable array of 20 distinct arithmetic and logic operations, showcasing its versatility in handling diverse DSP tasks. The proposed structure undergoes extensive simulations utilizing QCADesigner version 2.0.3 to confirm its performance. The evaluation results manifest substantial improvements compared to previous designs, boasting a 30% reduction in area occupancy, a 20% decrement in cell count, a 10% reduction in latency, and a 10% decrease in quantum cost compared to the best-known previous structure. These compelling outcomes solidify the potential of the proposed reversible ALU as a transformative advancement in energy-efficient and high-speed computing for DSP applications. [ABSTRACT FROM AUTHOR]

Designing high-speed and energy-efficient blocks for image and digital signal processing (DSP) architecture is an evolving research field. This work designs a high-speed and energy-efficient multiply-accumulate (MAC) unit to augment the performance of field-programmable gate array (FPGA)-based accelerators and softcore processors. In this work, three discrete 32-bit fixed-point signed MAC architectures were designed in Verilog and synthesized for the Zynq 7000 ZedBoard to obtain efficient MAC architecture. The ultimate goal of this work is to design a fast and energy-efficient MAC unit that can achieve speed up to the DSP48 block to reduce the latency of IoT edge computing. Energy efficiency was achieved in PPG and partial product addition (PPA) for the proposed Booth radix-4 Dadda (BR4D)-based MAC. At PPG, the width of the partial product (PP) terms was optimized with Bewick's signed extension to reduce the power consumption. At PPA, the number of PP rows reduces the critical path delay (CPD) with Dadda-based PPA. The proposed BR4D MAC unit offers a reduction in dynamic power, CPD, power-delay product (PDP) and energy-delay product (EDP) by 22%, 9%, 29% and 36%, respectively, compared to standard Booth radix-4 Wallace tree (BR4WT) based MAC. Furthermore, hybrid MACs (BR4WT and BR4D) were compared with the current state-of-the-art (SoA) designs, and it was found that the proposed BR4D MAC is 47% faster compared to the same design in SoA. The proposed BR4D was tested for frequency scaling technique by reducing the frequency in steps of 10 MHz from a maximum usable frequency (MUF) of 64 MHz to 10 MHz to evaluate the performance for low-power applications. Reducing clock frequency by 84% will reduce the power consumption at the same proportion and speed by 38%. Additionally, the proposed design helps to improve the battery life of IoT end nodes with a reduction in energy consumption and EDP by 76% and 61%, respectively. [ABSTRACT FROM AUTHOR]

In many industries and telecommunication system there is a need for digital signal processing for fast transfer of data between two points or devices with low power consumption and considerable hardware resources (circuit size and speed). Finite Impulse Response (FIR) filters play an important role in many signal processing applications and telecommunication systems. This paper propose the design and implementation of 4-bit FIR Filter using Distributed Arithmetic (DA) Algorithms, which substitute, multiply and accumulate operation with series of Look Up Table (LUT). The proposed FIR filter is implemented in high-density field programmable logic devices (FPGAs) and designed using very high-speed integrated circuit hardware description language (VHDL) and verified using Xilinx ISE 14.7 tool and simulator. The proposed, modified and optimized DA provided the multiplication and accumulation free calculation of inner product data of FIR filter and this consecutively reduces the size and power dissipation of circuit. DA is one of the methods to implement FIR filters that impact the storage resource and the calculating speed, which make the memory size smaller and the operation speed faster. The simulated proposed structure required nearly 40% less cells, 35% less LUT pairs and 4% less power consumption with existing structure. [ABSTRACT FROM AUTHOR]

In embedded applications and digital signal processing systems, multipliers are crucial components. In these applications, there is an increasing need for energy-efficient circuits. We use an approximate adder for error tolerance in the computational process to improve performance and reduce power consumption. Due to human perceptual constraints, computational errors do not significantly affect applications like image, audio, and video processing. Adiabatic logic (AL), which recycles energy, can also be used to build circuits that require less energy. In this work, we propose a carry save array multiplier employing an approximate adder based on CMOS logic and clocked CMOS adiabatic logic (CCAL) to conserve power. Additionally, using a precise full adder, multiplier parameters like average power and power delay product are calculated and compared with the multiplier. We performed simulations using 180 nm technology in Cadence Virtuoso. [ABSTRACT FROM AUTHOR]

Coherent optics has profoundly impacted diverse applications ranging from communications, LiDAR to quantum computations. However, developing coherent systems in integrated photonics comes at great expense in hardware integration and energy efficiency. Here we demonstrate a high-coherence parallelization strategy for advanced integrated coherent systems at minimal cost. By using a self-injection locked microcomb to injection lock distributed feedback lasers, we achieve a record high on-chip gain of 60 dB with no degradation in coherence. This strategy enables highly coherent channels with linewidths down to 10 Hz and power over 20 dBm. The overall electrical-to-optical efficiency reaches 19%, comparable to that of advanced semiconductor lasers. This method supports a silicon photonic communication link with an unprecedented data rate beyond 60 Tbit/s and reduces phase-related DSP consumption by 99.99999% compared to traditional III-V laser pump schemes. This work paves the way for realizing scalable, high-performance coherent integrated photonic systems, potentially benefiting numerous applications. Researchers demonstrate the high-coherence parallelization in integrated photonics. Their high-coherence, high-power, multiwavelength light source drives a silicon photonic link with a 60 Tbit/s data rate and significantly reduces digital signal processing consumption. [ABSTRACT FROM AUTHOR]

This manuscript presents a novel control approach for Permanent Magnet Synchronous Motors (PMSMs) by integrating the widely used Direct Torque Control (DTC) method with Deep Reinforcement Learning (DRL), specifically the Twin Delayed Deep Deterministic Policy Gradient (TD3) algorithm. The TD3 algorithm is well-suited to address the challenges posed by high-dimensional state and action spaces in PMSM drives. The conventional Proportional–Integral (PI) controller in the outer loop of DTC is replaced with the DRL based TD3 agent to overcome the limitations of traditional PI controllers, such as model dependency and complex parameter tuning. The DRL technique allows the agent to learn optimal control policies from experience, making it suitable for complex and nonlinear control problems. Extensive simulation studies demonstrate the effectiveness of the TD3-based control in achieving accurate speed tracking under varying operating conditions. Real-time experimental validation using a TMS320F28379D digital signal processor confirms the feasibility of the proposed DRL based approach. The research offers new insights into improving the performance of PMSM drives and paves the way for future advancements in electric drive control. [ABSTRACT FROM AUTHOR]

Clinical fetal monitoring devices can only be operated by medical professionals and are overly costly, prone to detrimental false positives, and emit radiation. Thus, highly accurate, easily accessible, simplified, and cost-effective fetal monitoring devices have gained an enormous interest in obstetrics. In this study, a cost-effective and user-friendly wearable home fetal movement and distress detection device is developed and assessed for early-stage design progression by facilitating continuous, comfortable, and non-invasive monitoring of the fetus during the final trimester. The functionality of the developed prototype is mainly based on a microcontroller, a single accelerometer, and a specialized fetal phonocardiography (fPCG) acquisition board with a low-cost microphone. The developed system is capable of identifying fetal movement and monitors fetal heart rhythm owing to its considerable sensitivity. Further, the device includes a Global System for Mobile Communication (GSM)-based alert system for instant distress notifications to the mother, proxy, and emergency services. By incorporating digital signal processing, the system achieves zero false negatives in detecting fetal movements, which was validated against an open-source database. The acquired results clearly substantiated the efficacy of the fPCG acquisition board and alarm system, ensuring the prompt identification of fetal distress. [ABSTRACT FROM AUTHOR]

This document contains abstracts from the Journal of Neonatal - Perinatal Medicine, covering a range of topics related to neonatal encephalopathy (NE) and its associated complications. The studies explore the efficacy of AI-based seizure-detection algorithms, the feasibility of EEG recordings in emergency transport, the validation of neonatal encephalopathy scores using neurophysiology measures, and the use of an automated seizure detection algorithm for neonatal EEG. Additionally, the document discusses the development and achievements of the HRB Neonatal Encephalopathy PhD Training Network (HRB NEPTuNE) research program, which aims to improve understanding, diagnosis, and management of NE. The text also includes studies on somatosensory evoked potentials (SEPs), red reflex assessment, catecholamine therapy, and neonatal ventriculitis. [Extracted from the article]

The automated guided vehicle (AGV) is currently used in a wide range of industries. The control system is the core of the AGV, responsible for task assignment, localization, path planning, motion planning, vehicle management, etc. In previous AGV implementations, personal computer, embedded computer, digital signal processor for computing, and programmable logic controller, micro control unit, field programmable gate array for control have been combined to form the whole control system. These solutions can solve common control problems, but they are complex to implement. To simplify the implementation complexity, the following work is presented in this study: (1) a new real-time operating system (RTOS), called Student RTOS, is developed. The RTOS includes memory management, task management, message queue, semaphore, synchronization, and timer, etc.; (2) a control system based on the newly designed RTOS is presented on a single processor; (3) the RTOS and the control system are tested on a newly designed AGV. From the actual test results, the newly designed RTOS and control system can meet the requirements of real-time, functionality, etc., and can effectively replace the original control system composed of multiple device combinations. In addition to running on the ARM Cortex-A processor used in the AGV control system, the RTOS also runs on the ARM Cortex-M and the STM8S (8-bit) processors for more low-end applications. [ABSTRACT FROM AUTHOR]

Sync word-based frame synchronization is an established method of frame synchronization that is employed in many low-resource applications because of its simplicity, and it involves the attachment of sync words (digital binary sequences) to the frames, which are then used for detection. Despite its simplicity, the method is underutilized today because there is no available hardware scheme that can perform correlation-based sync word frame synchronization with long sync words (>80 bits) efficiently. For this reason, the sync word methods that are used typically employ sync words of shorter lengths (<50 bits) with limited accuracy. This article introduces a highly modifiable, minimalist hardware architecture that performs correlation-based sync word frame synchronization using long sync words with evident accuracy gains over existing methods. As a bonus, the architecture not only detects the frame but also captures its payload regardless of size. Its low complexity allows for its deployment at a low cost in terms of hardware resources and power while providing high bit rates. Its flexibility is demonstrated by using a low-cost FPGA for implementation. [ABSTRACT FROM AUTHOR]

In order to solve the problem of duplicate data entry between construction management platform systems in construction engineering, the author proposes to apply RPA intelligent process robots to replace manual data collection, operation, entry, and verification. The design of the system is divided into overall architecture, instruction program loading process, human-machine interaction system level services, and other levels. An end-to-end procedural instruction transmission control method is adopted, establish a low-level control command output module for the online calibration system of the flight path, using a basic service architecture system, implement human-machine interactive control of the online calibration system for flight paths on the B/S architecture system. Build a record controller module for the inspection trajectory correction of RPA intelligent process robots, and perform feedback control during the trajectory correction process in LOG-CONTROL-BLOCK, using the RPA feedback correction algorithm, achieve adaptive correction and error feedback tracking of the inspection trajectory of RPA intelligent process robots. Implement calibration system development and design in an integrated DSP (Digital Signal Processing) information processing platform. The experimental results show that good economic benefits have been achieved through application, and the problem of duplicate data entry between the employer's IFS system and the ENPOWER document management system has been solved, greatly reducing error rates and personnel costs. It can replace manual data collection, entry, verification, and business operations; It has the characteristics of low error rate, low cost, high accuracy, compliance, and 24/7 standby; In 2021, 108000 yuan was saved, in 2022, 432000 yuan was saved, and in 2023, 432000 yuan was saved, demonstrating the labor hour cost savings achieved by utilizing RPA intelligent process robots. [ABSTRACT FROM AUTHOR]

Fast Fourier transform (FFT) is a fundamental building block for digital signal processing applications where high processing speed is crucial. Resource utilization in implementing FFT structures can be minimized by optimizing the performance of multipliers and adders used within the design. FFTs are also widely used in various machine learning algorithms. To achieve increased processor efficiency and reduced resource utilization, we propose a hardware design for Radix-2, Radix-4, and Split-Radix FFT architectures that utilizes a novel parallel prefix adder. This design offers lower power consumption, smaller chip area, and faster operation compared to existing architectures. Our performance analysis focuses on metrics such as power consumption, clock speed, and hardware complexity for Radix-2, Radix-4, and Split-Radix FFT algorithms implemented with the proposed adder. We compare these metrics using our proposed arithmetic structure against existing adder designs. The results indicate that the Split-Radix FFT architecture achieves lower power consumption and smaller chip area compared to Radix-4 and Radix-2 methods. Additionally, the Split-Radix FFT exhibits a higher clock speed. Therefore, based on these findings, the Split-Radix algorithm appears to be a compelling choice for implementation on field-programmable gate arrays due to its high speed and lower power consumption. [ABSTRACT FROM AUTHOR]

An induction motor is an electric machine widely used in various industrial and commercial applications due to its efficiency and simple design. In this regard, a methodology based on the electric phasor analysis of line currents and the variations in the phase angles among these line currents is proposed. The values in degrees of the angles between every pair of line currents were introduced to a fuzzy logic algorithm based on the Mamdani model, developed using the Matlab toolbox for detection and isolation of the inter-turn short-circuit faults on the windings of an induction motor. To carry out the analysis, the induction motor was modified in its stator windings to artificially induce short-circuit faults of different magnitudes. The current signals are acquired in real time using a digital platform developed in the Delphi 7 high-level language communicating with a float point unit Digital Signal Processor (DSP) TMS320F28335 by Texas Instruments. The proposed method not only detects the short circuit faults but also isolates the faulty winding. [ABSTRACT FROM AUTHOR]

In this review, we summarize the latest advances in the design of optical frequency-domain reflectometers (OFDRs), digital signal processing, and sensors based on special optical fibers. We discuss state-of-the-art approaches to improving metrological characteristics, such as spatial resolution, SNR, dynamic range, and the accuracy of determining back reflection coefficients. We also analyze the latest achievements in the OFDR-based sensors: the accuracy of spatial localization of the impact, the error in detecting temperatures, deformation, and other quantities, and the features of separate measurement of various physical quantities. We also pay attention to the trend of mutual integration of frequency-domain optical reflectometry methods with time-domain optical reflectometry, which provides completely new sensing possibilities. We believe that this review may be useful to engineers and scientists focused on developing a lab setup, complete measurement instrument, or sensing system with specific requirements. [ABSTRACT FROM AUTHOR]

A tunable active-noise-control (ANC) circuit topology for headsets used in different applications is presented in this article. In the current consumer headset market, ANC is a mature technology that is commonly applied to wireless headsets connected to smartphones for listening to music and making phone calls. The development of ANC headsets has resulted in low-cost and simple devices due to the built-in ANC registers in the digital circuit. Digital circuit implementation is important to provide ultra-low latency processing for different algorithms compared with using digital signal processors (DSPs). However, a limitation associated with these built-in ANC filters is that the ANC digital circuit has been designed only for the wireless headset consumer market. Consequently, ANC headsets can only be used for designated features. ANC tuned for planes by eliminating low-frequency engine noise has been commonly used in the past twenty years. Pass-through (PT) amplification is also commonly tuned to allow users to hear external sounds and have conversations without having to remove their headset. In addition, ANC and PT amplification are also not allowed to operate simultaneously on the existing chipsets. In this paper, an ANC circuit topology with ultra-low latency processing is presented, where the ANC response of the headset can be tuned without any restriction imposed by the built-in ANC filters. The proposed ANC circuit topology consists of a commercial ANC chipset with an external audio codec to provide tunable characteristics. It is achieved by fixed maximum noise cancellation of ANC chipset being modified by summing with the signal from audio-codec path via an audio mixer. Acoustic performance for several headset applications implemented using the proposed circuit is validated. This simple circuit topology can be easily developed and adapted to the current headset consumer market for consumer-selective ANC in different environments. [ABSTRACT FROM AUTHOR]

The digital correlator is one of the most crucial data processing components of a radio telescope array. With the scale of radio interferometeric array growing, many efforts have been devoted to developing a cost-effective and scalable correlator in the field of radio astronomy. In this paper, a 192-input digital correlator with six CASPER ROACH2 boards and seven GPU servers has been deployed as the digital signal processing system for Tianlai cylinder pathfinder located in Hongliuxia observatory. The correlator consists of 192 input signals (96 dual-polarization), 125-MHz bandwidth, and full-Stokes output. The correlator inherits the advantages of the CASPER system, for example, low cost, high performance, modular scalability, and a heterogeneous computing architecture. With a rapidly deployable ROACH2 digital sampling system, a commercially expandable 10 Gigabit switching network system, and a flexible upgradable GPU computing system, the correlator forms a low-cost and easilyupgradable system, poised to support scalable large-scale interferometeric array in the future. [ABSTRACT FROM AUTHOR]

Due to advances in power electronics technology and the evolution of automation devices, the number of electrical devices that are sensitive to power quality is rapidly increasing, and for this reason, users are increasing their demand for high quality. To meet power quality demands, many power conversion devices are used, including dynamic voltage restorers (DVRs). DVRs are recognized as devices that can effectively manage problems such as voltage segments, swells, and harmonics. DVR control requires many samples for harmonic compensation, which has the disadvantage of being complicated to implement due to fast digital signal processing computation and the application of the cyclic discrete Fourier transform. In this paper, a high-precision DVR system configuration is proposed that compensates for harmonics using a periodically equivalent time-interval sampling technique and a novel circular-structured memory filter. The proposed circular-structured multi-pointer memory filter is an effective filter algorithm for high-precision input voltage measurement because it can remove noise and compensate for the delay of the phase angle of the filter in voltage measurement. A simulation and DVR prototype system were built, and the feasibility and effectiveness of the phase angle multi-filter voltage detection method and the compensation method were verified by experiments. [ABSTRACT FROM AUTHOR]

Quality prediction in additive manufacturing (AM) processes is crucial, particularly in high-risk manufacturing sectors like aerospace, biomedicals, and automotive. Acoustic sensors have emerged as valuable tools for detecting variations in print patterns by analyzing signatures and extracting distinctive features. This study focuses on the collection, preprocessing, and analysis of acoustic data streams from a Fused Deposition Modeling (FDM) 3D-printed sample cube (10 mm × 10 mm × 5 mm). Time and frequency-domain features were extracted at 10-s intervals at varying layer thicknesses. The audio samples were preprocessed using the Harmonic–Percussive Source Separation (HPSS) method, and the analysis of time and frequency features was performed using the Librosa module. Feature importance analysis was conducted, and machine learning (ML) prediction was implemented using eight different classifier algorithms (K-Nearest Neighbors (KNN), Support Vector Machine (SVM), Gaussian Naive Bayes (GNB), Decision Trees (DT), Logistic Regression (LR), Random Forest (RF), Extreme Gradient Boosting (XGB), and Light Gradient Boosting Machine (LightGBM)) for the classification of print quality based on the labeled datasets. Three-dimensional-printed samples with varying layer thicknesses, representing two print quality levels, were used to generate audio samples. The extracted spectral features from these audio samples served as input variables for the supervised ML algorithms to predict print quality. The investigation revealed that the mean of the spectral flatness, spectral centroid, power spectral density, and RMS energy were the most critical acoustic features. Prediction metrics, including accuracy scores, F-1 scores, recall, precision, and ROC/AUC, were utilized to evaluate the models. The extreme gradient boosting algorithm stood out as the top model, attaining a prediction accuracy of 91.3%, precision of 88.8%, recall of 92.9%, F-1 score of 90.8%, and AUC of 96.3%. This research lays the foundation for acoustic based quality prediction and control of 3D printed parts using Fused Deposition Modeling and can be extended to other additive manufacturing techniques. [ABSTRACT FROM AUTHOR]

The analysis of biomedical signals is a very challenging task. This review paper is focused on the presentation of various methods where biomedical data, in particular vital signs, could be monitored using sensors mounted to beds. The presented methods to monitor vital signs include those combined with optical fibers, camera systems, pressure sensors, or other sensors, which may provide more efficient patient bed monitoring results. This work also covers the aspects of interference occurrence in the above-mentioned signals and sleep quality monitoring, which play a very important role in the analysis of biomedical signals and the choice of appropriate signal-processing methods. The provided information will help various researchers to understand the importance of vital sign monitoring and will be a thorough and up-to-date summary of these methods. It will also be a foundation for further enhancement of these methods. [ABSTRACT FROM AUTHOR]

Nowadays, the application of computations and communications is needed for high performance, reduced size and lower power utilisation. The multiply and add functions are one of the frequently used operations in digital signal processing. Various types of multipliers are available in digital Various types of multipliers are available for various Signal processing applications.. Among these multipliers, Vedic multiplier is one of the most optimised multipliers used in a signal processing module. In the existing method, the Vedic multiplier is designed with conventional adders, which is having higher area utilisation, lower speed and higher power consumption. Hence, the modified Vedic multiplier is proposed to improve the speed of multiplication using hybrid technology. The partial products of the proposed multiplication are added using 2 × 2 Vedic multiplier and hybrid carry select adder (binary to excess one converter (BEC), Han-Carlson adder and Multiplexer). The critical path delays of hybrid 4 × 4 Vedic multiplier are the summation of 2 × 2 Vedic multiplier, two full adders, two multiplexers and two BECs for producing the final product. The proposed hybrid Vedic multiplier is operated at high speed with reduced size as compared to the existing multiplier techniques. The proposed hybrid Vedic multiplier is designed and simulated using Verilog HDL and implemented in Spartan 6 field-programmable gate array device. The implementation results showed that the delay of the proposed multiplier gets ameliorated as compared to array multiplication (30.84%), Wallace tree multiplication (29.52%), multiplication based on compressor (23.71%), Vedic multiplication by carry look-ahead adder (22.91%), Vedic multiplication by ripple carry adder (14.45%), revised booth multiplication (15.42%) and Vedic multiplication by Han-Carlson adder with BEC (13.95%) and hybrid multiplier (11.37%). [ABSTRACT FROM AUTHOR]

The Molonglo Cross was first commissioned in 1965, as a transit radio (408 MHz) interferometer with the largest collecting area in the Southern hemisphere. In 1981, the telescope was redeveloped as an Earth-rotation synthesis interferometer using only the East–West arm (843 MHz), known as the Molonglo Observatory Synthesis Telescope. While the East–West arm was revitalized in the 2010s, the (slightly larger) North–South (NS) arm, which consists of two co-linear paraboloid cylindrical reflectors spanning 2 × 778 m × 12.7 m, had not been used for over 40 yr. Re-fitting this 19 800-m2 collecting area with modern electronics is a cost-effective way of producing a significant survey instrument. The upgrades made to the entire signal chain of the NS arm from the antenna through the transport, digitization, and digital signal processing are described, along with the subsequent performance of the system. The instrument was designed to undertake pulsar timing and searching for dispersed single pulses [e.g. from fast radio bursts (FRBs)]. The upgraded system operated across the 806.25–856.25-MHz frequency range, and had a primary beam that spans 12.7 × 2.5 deg. It had dual linear polarization capability and a lower system temperature and wider bandwidth compared with the East–West system. The digital signal processing was performed on servers with graphics processing units, which enabled low-latency, high-speed data processing, and made use of pipelines built from existing and custom codes. It timed around 70 pulsars per day while running concurrent FRB searches at nearly 100 per cent duty cycle during its operation. [ABSTRACT FROM AUTHOR]

This paper derives an advanced multi-loop speed feedback system equipped with model-free pole-zero cancellation (PZC) filters for the position and current measurements of servo drives. The proposed feedback system does not necessitate an exact system model, and it renders the transfer function of each loop in a first-order low-pass filter form by involving active damping terms. Furthermore, the PZC filters output the desired speed and current information for each of the loops along the first-order convergent system, independent of the system model. An experimental platform involving a 500 W brushless DC motor, with a digital signal processor as a controller, validates the practical improvement of the proposed feedback system. [ABSTRACT FROM AUTHOR]

A new algorithm for frequency measurement in an electric power system (EPS) under conditions of high harmonic distortions is presented. The algorithm is based on a combination of the Fourier method and zero-crossing technique which processes three-phase voltage signals at the site of the embedded digital relay. The Fourier method is used as a digital filter in order to form the calculated signals containing the fundamental frequency of the original signal. The zero-crossing technique is successively applied to the three-phase system formed by the three sine calculated components obtained by the Fourier method. The three-phase frequency measurement possesses better dynamic characteristics compared to the single-phase measurement. In addition, the three-phase measurement is more reliable since the algorithm allows frequency measurement even under conditions of single- or two-phase failures. By losing one or two input signals the algorithm loses only on dynamic performance but retains the stability and accuracy. [ABSTRACT FROM AUTHOR]

According to the World Health Organization, 430 million individuals, or more than 5% of the world's population, need hearing loss rehabilitation. They also estimate that by 2050, one in ten individuals, or over 700 million people, would suffer hearing loss, that is incapacitating. Despite these difficulties, technological developments have made it feasible to enhance these people's quality of life. The Real-time Smart Auditory Assistive Wearable (RESAAW), is a revolutionary gadget that aids people with hearing problems by employing omnidirectional microphones to record real-time surrounding noises. In the case of abrupt or harmful noises, the gadget gives the user tactile input while employing advanced digital signal processing and machine learning models to distinguish vital sounds from background noise. The goal of RESAAW is to use 4 omnidirectional microphones that constantly pick up noises in the vicinity of the individual wearing it and filter the noises using digital signal processing techniques ML models. There are people with different degrees of hearing loss. This system would be a boon to them in their work places. [ABSTRACT FROM AUTHOR]

This research aims to enhance the understanding of the acoustic processes occurring during sonotubometry, a method used to assess the Eustachian tube (ET) function. Recent advancements in digital signal processing enable a more comprehensive data analysis. In this project, a silicone model of the ET was developed to systematically study the existing noise and sound sources. These measurements were then compared with recordings from human subjects. Three distinct 'noise sources' were identified, which can influence the assessment of the ET opening using transmission measurements of the imposed signal: sound leakage from the speaker, a clicking noise at the initiation of ET opening, and rumbling/swallowing noise. Through spectral analysis, it was also possible to ascertain the spectral and temporal occurrence of these sound and noise types. The silicone model exhibited remarkable similarity to the healthy human ET, making it a robust experimental model for investigating the acoustics of sonotubometry. The findings underscore the significance of delving deeper into the analysed sound, as the noise occurring during sonotubometry can be easily misconstrued as an actual ET opening. Particularly, careful consideration is warranted when evaluating data involving clicking and swallowing noise. [ABSTRACT FROM AUTHOR]

Performing noise characterizations of lasers and optical frequency combs on sampled data offers numerous advantages compared to analog measurement techniques. One of the main advantages is that the measurement setup is greatly simplified. Only a balanced detector followed by an analog-to-digital converter is needed, allowing all the complexity to be moved to the digital domain. Secondly, near-optimal phase estimators are efficiently implementable, providing accurate phase noise estimation in the presence of measurement noise. Finally, joint processing of multiple comb lines is feasible, enabling the computation of the phase noise correlation matrix, which includes all information about the phase noise of the optical frequency comb. This tutorial introduces a framework based on digital signal processing for phase noise characterization of lasers and optical frequency combs. The framework is based on the extended Kalman filter (EKF) and automatic differentiation. The EKF is a near-optimal estimator of the optical phase in the presence of measurement noise, making it very suitable for phase noise measurements. Automatic differentiation is key to efficiently optimizing many parameters entering the EKF framework. More specifically, the combination of EKF and automatic differentiation enables the efficient optimization of phase noise measurement for optical frequency combs with arbitrarily complex noise dynamics that may include many free parameters. We show the framework's efficacy through simulations and experimental data, showcasing its application across various comb types and in dual-comb measurements, highlighting its accuracy and versatility. Finally, we discuss its capability for digital phase noise compensation, which is highly relevant to free-running dual-comb spectroscopy applications. [ABSTRACT FROM AUTHOR]

Sleep apnea, characterized by breathing interruptions or slow breathing at night, can cause various health issues. Detecting respiratory rate (RR) using Wireless Fidelity (Wi-Fi) can identify sleep disorders without physical contact avoiding sleep disruption. However, traditional methods using Network Interface Cards (NICs) like the Intel Wi-Fi Link 5300 NIC are often costly and limited in channel state information (CSI) resolution. Our study introduces an effective strategy using the affordable ESP32 single-board computer for tracking RR through detailed analysis of Wi-Fi signal CSI. We developed a technique correlating Wi-Fi signal fluctuations with RR, employing signal processing methods—Hampel Filtering, Gaussian Filtering, Linear Interpolation, and Butterworth Low Pass Filtering—to accurately extract relevant signals. Additionally, noise from external movements is mitigated using a Z-Score for anomaly detection approach. We also implemented a local peak function to count peaks within an interval, scaling it to bpm for RR identification. RR measurements were conducted at different rates—Normal (12–16 bpm), Fast (>16 bpm), and Slow (<12 bpm)—to assess the effectiveness in both normal and sleep apnea conditions. Tested on data from 8 participants with distinct body types and genders, our approach demonstrated accuracy by comparing modeled sleep RR against actual RR measurements from the Vernier Respiration Monitor Belt. Optimal parameter settings yielded an overall average mean absolute deviation (MAD) of 2.60 bpm, providing the best result for normal breathing (MAD = 1.38). Different optimal settings were required for fast (MAD = 1.81) and slow breathing (MAD = 2.98). The results indicate that our method effectively detects RR using a low-cost approach under different parameter settings. [ABSTRACT FROM AUTHOR]

An end-to-end testbed for In-phase and Quadrature (I/Q) Imbalance (IQI) communication systems based on Software-Defined Radio (SDR) is presented. The scenario under consideration is a Single-Input–Single-Output (SISO) single-carrier communication where the transmitter is heavily affected by IQI, whose effects are mitigated through digital signal processing at the receiver. The presented testbed is highly configurable, enabling the testing of different communication and IQI parameters. Crucial insights into the practical implementation of IQI mitigation techniques, specifically through the use of asymmetric signaling at the receiver, are provided. Initially, a detailed description of the mathematical framework is given. This framework serves as the foundation for the subsequent discussion on system implementation, effectively bridging the gap between research on IQI mitigation and its practical application in single-carrier architectures. Over-The-Air (OTA) Symbol Error Rate (SER) measurements for different constellations validate the receiver design and implementation. The source code of the presented testbed is publicly available. [ABSTRACT FROM AUTHOR]

Multi-motor servo systems are widely used in industrial control. However, the single-core microprocessor architecture based on the microcontroller unit (MCU) and digital signal processor (DSP) is not well suited for high-performance multi-motor servo systems due to the inherent limitations in computing performance and serial execution of code. The bus-based distributed architecture formed by interconnecting multiple unit controllers increases system communication complexity, reduces system integration, and incurs additional hardware and software costs. Field programmable gate array (FPGA) possesses the characteristics of high real-time performance, parallel processing, and modularity. A single FPGA can integrate multiple motor servo controllers. This research uses MCU + FPGA as the core to realize high-precision multi-axis real-time control, combining the powerful performance of the MCU processor and the high-speed parallelism of FPGA. The MCU serves as the central processor and facilitates data interaction with the host computer through the controller area network (CAN). After data parsing and efficient computation, MCU communicates with the FPGA through flexible static memory controller (FSMC). A motor servo controller intellectual property (IP) core is designed and packaged for easy reuse within the FPGA. A 38-axis micro direct current (DC) motor control system is constructed to test the performance of the IP core and the heterogeneous embedded platforms. The experimental results show that the designed IP core exhibits robust functionality and scalability. The system exhibits high real-time performance and reliability. [ABSTRACT FROM AUTHOR]

Data converters are necessary for the conversion process of analog and digital signals. Successive approximation register (SAR) analog-to-digital converters (ADC) can achieve high levels of accuracy while consuming relatively low amounts of power and operating at relatively high speeds. This paper describes a design of 8-bit 125 kS/s SAR ADC with a proposed high-speed comparator design based on dynamic latch architecture. The proposed design of the comparator enhances the performance compared to a conventional dynamic comparator by adding two parallel clocked input complementary metal-oxide semiconductor (CMOS) transistors which reduce the parasitic resistance in the latch ground path and serve to minimize the latch delay time. The design of each sub-system for the ADC is explained thoroughly, which contains a sample and hold circuit, successive approximation register, charge redistribution types digital-to-analog converter, and the new proposed comparator. The proposed design is implemented using 180 nm CMOS technology with a power supply of 1.2 V. The average inaccuracy in differential non-linearity (DNL) is +0.6/-0.8 LSB (least significant bit), and integral non-linearity (INL) is +0.4/-0.7 LSB. The proposed design exhibits a delay time of 157 ps at 1 MHz clock frequency. [ABSTRACT FROM AUTHOR]

In recent years, the automotive industry has made significant progress in integrating multifunctional sensors to improve vehicle performance, safety, and efficiency. As the number of integrated sensors keeps increasing, there is a growing interest in alternative energy sources. Specifically, self‐powered sensor systems based on energy harvesting are drawing much attention, with a main focus on sustainability and reducing reliance on typical batteries. This paper demonstrates the use of triboelectric nanogenerators (TENGs) in a computer mouse for efficient energy harvesting and in automobile braking systems for safety applications using SrBi2Ta2O9 (SBTO) perovskite, blended PDMS composite operating in free‐standing mode with an interdigitated patterned aluminum electrode. This self‐powered sensor is capable of distinguishing between normal and abnormal braking patterns using digital signal processing techniques. It is noteworthy that the addition of 15% wt. of the SBTO in PDMS composite‐based TENG delivered 13.5 V, 45 nA, and an output power of 0.98 µW. This new combination of energy harvesting and safety applications enables real‐time monitoring and predictive maintenance in the automotive industry. [ABSTRACT FROM AUTHOR]

Addressing the global disparity in cancer care necessitates the development of rapid and affordable nucleic acid (NA) testing technologies. This need is particularly critical for cervical cancer, where molecular detection of human papillomavirus (HPV) has emerged as an accurate screening method. However, implementing this transition in low- and middle-income countries has been challenging due to the high costs and centralized facilities required for current NA tests. Here, we present CreDiT (CRISPR Enhanced Digital Testing) for on-site NA detection. The CreDiT platform integrates i) a one-pot CRISPR strategy that simultaneously amplifies both target NAs and analytical signals and ii) a robust fluorescent detection based on digital communication (encoding/decoding) technology. These features enable a rapid assay (<35 minutes) in a single streamlined workflow. We demonstrate the sensitive detection of cell-derived HPV DNA targets down to single copies and accurate identification of HPV types in clinical cervical brushing specimens (n = 121). Developing rapid and affordable HPV tests is imperative for effective cervical cancer screening in resource-limited regions. Here, the authors demonstrate an advanced HPV diagnostic system that integrates CRISPR technology with digital signal processing. [ABSTRACT FROM AUTHOR]

In this paper, we introduce a hardware-in-the-loop simulation analysis method for controlling the speed of a surface-mounted permanent magnet synchronous motor using the development software Altair Embed 2019. We focused on implementing a comprehensive closed-loop speed control drive using the field-weakening algorithm, encompassing maximum torque per ampere, constant output power, and maximum torque per voltage. Altair Embed 2019 facilitates an intuitive graphical approach for swift control design through real-time embedded controller simulation that is particularly compatible with digital signal processors such as those from Texas Instruments. The effectiveness of the proposed approach is validated through hardware-in-theloop simulation conducted on a dynamometer system, showcasing promising results. Future endeavors involve the direct implementation of this methodology in practical drive and motor systems to substantiate its efficacy in streamlining programming technical skills. [ABSTRACT FROM AUTHOR]

The design and integration of intelligent energy management systems in hybrid electric vehicle (EV) charging stations, leveraging industry 4.0 and renewable energy sources, is crucial for advancing sustainability, efficiency, and technological development. The innovative hybrid EV charging station described in this study uses a combination of fuel cells, batteries, and solar panels that run at 14 amps a piece at 240 volts. The system consists of five essential components that work together to transfer power wirelessly: an EV battery bank, a boost converter, an HF inverter, transfer coils, and a power supply. Two crucial phases make up the optimization process. In phase 1, the boost converter's maximum power point is tracked and optimized to generate the most power possible by varying the duty cycle between 10% and 90%. In phase 2, the HF uses a class ϕ2 inverter at 30 MHz to synchronize with the resonant frequency of wireless power transfer coils. Zero-voltage switching is used by a digital signal processor card to carry out control for effective operations. By utilizing hybrid sources to optimize power transmission, this design improves the sustainability of EV charging options. [ABSTRACT FROM AUTHOR]

The aim of this study is to develop a practical software solution for real-time recognition of sign language words using two arms. This will facilitate communication between hearing-impaired individuals and those who can hear. We are aware of several sign language recognition systems developed using different technologies, including cameras, armbands, and gloves. However, the system we propose in this study stands out for its practicality, utilizing surface electromyography (muscle activity) and inertial measurement unit (motion dynamics) data from both arms. We address the drawbacks of other methods, such as high costs, low accuracy due to ambient light and obstacles, and complex hardware requirements, which have limited their practical application. Our software can run on different operating systems using digital signal processing and machine learning methods specific to this study. For the test, we created a dataset of 80 words based on their frequency of use in daily life and performed a thorough feature extraction process. We tested the recognition performance using various classifiers and parameters and compared the results. The random forest algorithm emerged as the most successful, achieving a remarkable 99.875% accuracy, while the naïve Bayes algorithm had the lowest success rate with 87.625% accuracy. The new system promises to significantly improve communication for people with hearing disabilities and ensures seamless integration into daily life without compromising user comfort or lifestyle quality. [ABSTRACT FROM AUTHOR]

This paper outlines the development of a Hardware Development Kit (HDK) for a remote training platform on FPGA Devices designed to provide university students pursuing degrees in electronic and informatics engineering (at the bachelor's, master's, and PhD levels) with the tools they need to learn and develop systems related to artificial intelligence, digital signal processing, image processing, digital systems, integrated and embedded systems using an FPGA chip. Through the internet or a local network, students can engage with the platform to conduct engineering experiments. The HDK is equipped with a Raspberry Pi, a screen, a camera, and LEDs to facilitate the transfer of experiment results and to aid in assessing the validity of lab experiment execution. The Raspberry Pi plays a crucial role in the HDK, providing control and monitoring, remote access, data processing, user interface, and integration with other possible systems. [ABSTRACT FROM AUTHOR]

Power grids are progressing, and the possibility of incorporating DC grids toward hybrid AC/DC grids is gaining increasing relevance, as several technologies available nowadays are operating natively in DC. This paper proposes a topology of a full-controlled bidirectional dual-stage interleaved converter for interfacing hybrid AC/DC grids. The topology is based on a dual-stage architecture, constituted by an AC/DC converter and by a DC/DC converter, both based on interleaved power converters. On the AC side, which is connected to the main AC power grid, the proposed dual-stage architecture operates with sinusoidal current in phase or phase opposition with the voltage, meaning a bidirectional operation. In addition, it has the possibility of interfacing with other AC loads, such as domestic electrical appliances, or with an AC microgrid. The DC link, formed by the AC/DC power stage, is interfaced with a DC power grid, which provides numerous advantages, e.g., for interfacing battery electric vehicles directly charged in DC, as well as other DC loads, such as renewable energy sources. The DC/DC power stage is considered for interfacing with an energy storage system, which is capable of bidirectional power exchange with the DC grid or with the AC grid through the AC/DC power stage. A complete laboratory prototype was designed and developed, with the unified control algorithms implemented on a digital signal processor. The experimental results validated the operation of the full-controlled bidirectional dual-stage interleaved converter based on the specifications for the hybrid AC/DC grid, such as bidirectional operation, synchronization with the AC power grid, predictive current control, interleaved operation on both AC/DC and DC/DC power stages, DC-link voltage control for the DC grid, as well as the operation with different power levels. [ABSTRACT FROM AUTHOR]

Blended learning is the latest and inevitable trend in the development of education. Although blended learning research is on the rise, fewer studies examine the learning behaviour of college students in blended learning environments. This study aimed to investigate the learning behaviours of students in the field of computer science and examine these behaviours using data mining algorithms, taking the teaching practice of the Digital Signal Processing course as a case study. A total of 18 behavioural indicators were extracted and divided into three categories: basic learning behaviours, self-regulated learning behaviours, and extended learning behaviours. Data analysis of the behavioural indicators yielded the following conclusions: (1) Students did not have the habit of watching course playback and were less receptive to multiple online learning platforms; (2) Students' midterm performance and duration of livestream watching directly affected their basic learning behaviours, with all indicators of self-regulated and extended learning behaviours showing significant correlations; (3) The clustering of learning behaviours yielded four different learner patterns, which calls for personalised teaching strategies; (4) The random forest algorithm had an accuracy of 95.4% in predicting performance of the four types of learners. [ABSTRACT FROM AUTHOR]

This study seeks to establish connections between Ramanujan-type Eisenstein series and Borweins’ cubic theta functions, employing the (p, k)-parametrization method introduced by Alaca. Furthermore, the derived identities are applied to provide a novel representation for the evaluation of the discrete convolution sum P 2l+3m=n δ(i)δ(j). [ABSTRACT FROM AUTHOR]

The article presents an innovative approach to increasing the number of digital samples in analog-to-digital systems using a strobing method in a "sliding-window" mode. Particular attention is paid to optimizing the in-phase/quadrature demodulation for signals with orthogonal frequency division multiplexing. The study analyzes the amplitude-frequency characteristics of the latest I/Q demodulators, demonstrating a reduction in the side lobes of the frequency response. [ABSTRACT FROM AUTHOR]

In this paper, we introduce the continuous and discrete version of the linear canonical shearlet transform (LCST). The authors begin with the definition of the LCST and then establish a relationship between the linear canonical transform (LCT) and the LCST. Next, the paper derives several basic properties like Parseval's Formula, inversion formula, and the characterization of the transform's range. In addition to the continuous version of the transform, the authors also present a discrete version of the LCST. This discrete version allows for practical implementation and efficient computation of the transform in digital signal processing systems. Lastly, the paper establishes a frame condition for the discrete LCST, which thereby helps in establishing the reconstruction formula for the discrete LCST. The paper ends with a conclusion. [ABSTRACT FROM AUTHOR]

Summary This article proposes a novel angle representation method for floating‐point number, which eliminates the need for DSP (Digital Signal Processor) resources and reduces the resource usage when performing floating‐point multiplication. Compared with the implementation of floating‐point multiplier using IP cores, the implementation of approximate multiplication based on lookup tables can achieve an average reduction of 58.2% in LUTs (look‐up tables) and an average increase of 20.4% in frequency for mantissa widths ranging from 3 to 12 bits. Additionally, it can also save an average of 23.2% in registers. Analysis of PDP (power‐delay product)/LUT to MRED (mean relative error distance)/PRED (probability of relative error distance) among other approximate multipliers shows that the proposed design extends the Pareto front. At last, simulation of a three‐level inverter is implemented to verify the effectiveness of the multiplier. [ABSTRACT FROM AUTHOR]

The analysis workflow of Prompt gamma activation analysis (PGAA) at the Budapest Neutron Centre's PGAA and NIPS-NORMA facilities, at the MLZ FRM II PGAA station, and other centers worldwide relied on the use of the Hypermet-PC gamma spectrometry software and the ProSpeRo concentration calculation Excel macro. The sustained interest of our user community amid the reduced availability of multiple large-scale neutron sources worldwide called for more efficient utilization of the operational PGAA facilities. The present paper addresses both measurement and data evaluation bottlenecks of the analysis procedure to achieve higher productivity and superior spectroscopic performance. [ABSTRACT FROM AUTHOR]

Traditional logic circuit emits energy into the environment due to information loss, and it is referred to be irreversible logic circuits. Reversible logic circuit is capable of diminishing power loss, quantum cost, and garbage output. Many academics have recently embraced reversible logic-based circuits exploiting all-optical technology to conduct their research. In this article, all-optical reversible adder and subtractor have been implemented using microring resonator-based Naveen Raymond reversible logic gate, for the first time to our knowledge. MATLAB serves as the tool for design and analysis of the proposed architecture at almost 260 Gbps operational speed. The ultrafast response times and compact design of the microring resonator-based circuits make them especially useful for digital signal processing and communication systems. Some performance reflecting factors such as "quality factor", "photon cavity lifetime", "extinction ratio", "contrast ratio", "amplitude modulation", "on-off ratio", and "relative eye opening" are explored and analyzed. Optimized design parameters have been selected in order to build the model practically. [ABSTRACT FROM AUTHOR]

The article presents an innovative approach to increasing the number of digital samples in analog-to-digital systems using a strobing method in a “sliding-window” mode. Particular attention is paid to optimizing the in-phase/quadrature demodulation for signals with orthogonal frequency division multiplexing. The study analyzes the amplitude-frequency characteristics of the latest I/Q demodulators, demonstrating a reduction in the side lobes of the frequency response. [ABSTRACT FROM AUTHOR]

In order to meet the increasing requirements of speed and distance, an advanced digital signal processing (DSP) algorithm is preferred without changing the system structure in intensity modulation and the direct detection (IM/DD) system. As the transmission distance increases, the power fading induced by dispersion must be mitigated. In addition, linear and nonlinear inter symbol interference (ISI) introduced by bandwidth limitation and device imperfections becomes an obstacle to achieving higher capacity. The Gerchberg–Saxton (GS) algorithm was recently used to compensate for dispersion. In this paper, GS-based pre- and post-compensation schemes in the IM/DD system with nonlinearity were investigated. We investigated and compared the performance of the GS-based pre- and post-compensation algorithm in a 28 GB aud four-level pulse amplitude modulation (PAM-4) transmission over 40 km standard single-mode fiber (SSMF). The bit error rate (BER) achieved a threshold of 3.8 × 10−3 using look-up-table (LUT), FFE, and the GS-based pre-compensation algorithm without iterations. Turning to the GS-based post-compensation scheme, 80 iterations are needed. However, the demand for FFE is reduced. The algorithm selection depends on the tolerance of the transmitter or receiver complexity in specific scenarios. The joint LUT and GS-based pre-compensation algorithm may be a preferable approach in scenarios where a low-complexity receiver is desired. [ABSTRACT FROM AUTHOR]

We propose a novel approach to mitigate the limitations of high-speed Passive Optical Networks (PONs) by introducing an all-optical processor. This solution addresses the escalating demand for higher data rates and improved performance in future access networks. The all-optical processor leverages optical signal processing to enhance system efficiency and reduce power consumption compared to traditional electrical methods. Specifically, we explore the processor's dual functionality in performing all-optical equalization and chromatic dispersion compensation. Our research includes a comprehensive analysis of the processor's design, operational principles, and system validation through extensive simulation studies, demonstrating significant improvements in signal quality and overall network performance. The results indicate that the all-optical processor not only relaxes the DSP and power requirements but also outperforms the more sophisticated digital counterpart methods. [ABSTRACT FROM AUTHOR]

The emerging high-bandwidth services of 6G, such as high-definition video transmission and real-time interaction, have promoted the progress of the fiber optic access network industry, driving its development towards the next-generation PON with higher speed and larger system capacity. In response to the future requirements of 200 Gb/s/λ PON for both 20 km and 30 km downlink transmission scenarios, this paper proposes a Simplified Volterra Equalization (SVLE) scheme based on Nyquist PAM4 single-sideband modulation direct detection (SSBM-DD) scheme. In order to verify its advantages, the IQ-modulated Kramers–Kronig reception (KK) scheme is introduced for comparison. Simulation validation platforms for two schemes are conducted, and the performance comparison of the SVLE and KK schemes is carried out. In both, the impact of the carrier signal power ratio (CSPR) on receiver sensitivity, the influence of input optical power on power budget and receiver sensitivity, and the tolerance of receiver sensitivity to the linewidth of the DFB laser are investigated in the simulation. Finally, a comprehensive comparison of the two schemes is presented in terms of system performance, cost, and DSP complexity. In the 20 km downlink transmission scenario, the SVLE scheme outperforms the KK scheme by 4.9 dB in terms of power budget. The total number of multiplications of the SVLE scheme is 37, while that of the KK scheme is 4358. Therefore, the DSP complexity of the SVLE scheme is much lower than that of the KK scheme. The results of the comparison demonstrate that, in downlink transmission scenarios, the SVLE scheme is more suitable than the KK scheme as it exhibits a higher power budget, lower DSP complexity, and lower cost. Consequently, the proposed SVLE scheme could be a highly promising solution for future ultra-high-speed PON downlink transmission. [ABSTRACT FROM AUTHOR]

Recently, extensive research has been conducted to explore the utilization of machine learning (ML) algorithms in various direct-detected and (self)-coherent short-reach communication applications. These applications encompass a wide range of tasks, including bandwidth request prediction, signal quality monitoring, fault detection, traffic prediction, and digital signal processing (DSP)-based equalization. As a versatile approach, ML demonstrates the ability to address stochastic phenomena in optical systems networks where deterministic methods may fall short. However, when it comes to DSP equalization algorithms such as feed-forward/decision-feedback equalizers (FFEs/DFEs) and Volterra-based nonlinear equalizers, their performance improvements are often marginal, and their complexity is prohibitively high, especially in cost-sensitive short-reach communications scenarios such as passive optical networks (PONs). Time-series ML models offer distinct advantages over frequency-domain models in specific contexts. They excel in capturing temporal dependencies, handling irregular or nonlinear patterns effectively, and accommodating variable time intervals. Within this survey, we outline the application of ML techniques in short-reach communications, specifically emphasizing their utilization in high-bandwidth demanding PONs. We introduce a novel taxonomy for time-series methods employed in ML signal processing, providing a structured classification framework. Our taxonomy categorizes current time-series methods into four distinct groups: traditional methods, Fourier convolution-based methods, transformer-based models, and time-series convolutional networks. Finally, we highlight prospective research directions within this rapidly evolving field and outline specific solutions to mitigate the complexity associated with hardware implementations. We aim to pave the way for more practical and efficient deployment of ML approaches in short-reach optical communication systems by addressing complexity concerns. [ABSTRACT FROM AUTHOR]