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Digital Radio over Fiber (DRoF) technologies end up being the most often used option for the backbone of Wide Area Networks (WAN). The main goal of this paper is to evaluate a DRoF scheme called Sigma Delta Radio over Fiber (SDRoF). Studies have been done on the suggested system performance metrics, such as Error Vector Magnitude (EVM). According to the simulation findings, the suggested model can handle 6.144 Gbps data transfer up to 300 km with zero BER and an EVM of about 4.153%. The proposed system model was found to be superior to the most recent peer-reviewed papers. [ABSTRACT FROM AUTHOR]

This paper presents a fourth-order discrete-time direct RF-to-digital Delta-Sigma receiver architecture for flexible receivers with a wide frequency range. The use of a current-driven passive mixer with RF feedback enables high-Q bandpass filtering and relaxes the linearity requirement of the RF amplifier. In addition, the reconfigurable passive/active loop filter offers a good compromise between power consumption, linearity, and dynamic range. The other important feature of the proposed architecture is the use of a sampling frequency that is a divisor of the LO frequency. This solves several problems such as the upmixing of quantization noise, the need to reconfigure the Delta-Sigma loop when changing the LO frequency, and the use of two independent clocks for the LO and the sampling frequency. The circuit was implemented using 65 nm CMOS technology. The I/Q Direct Delta-Sigma receiver has an RF bandwidth of 20 MHz and a sampling frequency of 400 MHz. Measurement results show a very high dynamic range of up to 80 dB with a peak SNDR of 46 dB for a power consumption of 46 mW at 800 MHz. [ABSTRACT FROM AUTHOR]

Image processing has widespread uses practically in every branch of science and arts. Processing images is more difficult than processing sound or data as there are more bits in the high pixel quality image. It requires more space to store the image, more bandwidth to transmit it, and more time and resources to process. An image's complexity may decrease if its bit size is decreased. Sigma-delta modulation, or SDM for short, is an alternative method of minimizing data-word length to compression. Digital signal processing (DSP) systems can be made simpler by using the SDM approach, which was first created for analog to digital conversion (ADC). This paper suggests a novel way to use SDM in MATLAB for improved image processing. Consequently, the suggested single-bit SDM-based image arithmetic architecture is tested and compared with the traditional image arithmetic techniques. Additionally, to see the noisy channel influence on the traditional and proposed systems, some statistical metrics are also studied at different noise variance values, such as signal to noise ratio (SNR), mean square error (MSE), and Peak SNR value. The suggested architecture for the SDM-based image arithmetic precisely matches the addition and subtraction results of the conventional design, even yielding a higher SNR and the same Peak SNR as the traditional methods. In contrast, the outcomes of division and multiplication fall within an acceptable range. For better results the over-sampling ratio (OSR), an inherent characteristic of SDM must be increased at the cost of more processing cycles. Therefore, the trade-off between fewer resources, limited transmission bandwidth, and comparatively more cycles is provided by the SDM-based technique. [ABSTRACT FROM AUTHOR]

We propose a wideband model-embedding delta-sigma radio-over-fiber (DS-RoF) design for keeping the adjacent channel leakage low. This RoF design is derived on the basis of the DS-RoF embedding a pulse-distortion model (PDM). To enable wideband modulation with low adjacent channel leakage, we also propose an optimization method using an objective function simulating the adjacent channel leakage. By refining the digital down-converter from previous work, we additionally propose an extended PDM that generalizes its parameters from real numbers to complex numbers, which allow for fine-tuned delay adjustments in the PDM. A RoF demonstration using commercially available small form-factor pluggable (SFP) modules and a 10-km single mode fiber (SMF) with a 400-MHz-bandwidth orthogonal frequency division multiplexing (OFDM) signal, including a calibration path for modeling pulse distortion, revealed that the proposed design with our extended complex-valued PDM improved the signal-to-noise ratio (SNR) by 0.8 dB, normalized mean-squared error (NMSE) by 0.3 dB and adjacent channel leakage ratio (ACLR) by 0.4 dB compared with a RoF design with the original real-valued PDM. These results indicate that the complex-valued PDM, which enables fine-tuned delay adjustments, increases modeling accuracy, leading to enhanced compensation performance. Moreover, the proposed DS-RoF design with our complex-valued PDM also achieved an ACLR below -31 dBc. This result indicates that, to the best of our knowledge, we are the first to realize a 400-MHz-bandwidth modulation required for 5G millimeter wave as a DS-RoF system.

This paper introduces and experimentally validates a switched-capacitor inverter-based second-order 3-tap FIR single-bit Delta-Sigma Modulator ( $\Delta \Sigma $ M) designed for nanowatt-level analog-to-digital conversion in wearable healthcare devices. The focus is on applications with energy harvesters, emphasizing continuous monitoring of chronic conditions and closed-loop drug-delivery systems. The design methodology addresses ultralow-power considerations at both architectural and transistor levels, tackling challenges like process variations without relying on complex digital calibration techniques. Experimental results from prototypes, implemented on a standard 180-nm CMOS process, reveal a peak SINAD of 77.8 dB and SNR of 79.4 dB, with a power consumption of 71.5 nW at a 900-mV supply. Measurements across nine chip samples are consistent, demonstrating low DC offset, with low temperature drift and live sensitivity. The outcomes confirm the modulator suitability for energy-harvested wearable systems.

In this paper an advanced modulation strategy is proposed that generates the switch control signals of a power converter while inherently guaranteeing zero-voltage switching (ZVS) operation. The proposed modulator is based on a first-order $\Delta \Sigma$-modulator combined with a hold-off circuit. This hold-off circuit consists of a D-latch and maintains the converter's switching state until ZVS commutation can be achieved while an integrator ensures the correct average output. Furthermore, features are implemented to improve start-up and transient behavior. The operating principle and stability of the proposed modulator is discussed and simulation results are presented. Finally, the proposed modulator is validated on a $2 \,\mathrm{k}\mathrm{W}$ GaN-based synchronous buck converter. Results show that the converter naturally operates under ZVS conditions by continuously varying its switching frequency without having to compute switching times or frequencies. The proposed method is an interesting alternative to pulse-width modulation especially when operating at high switching frequencies or when the switching loss in the power converter is significant.

Delta-sigma modulation can be used as a high spectral efficiency interface in place of conventional common public radio interface (CPRI) in mobile fronthaul (MFH) networks. However, inter-symbol interference (ISI) becomes more difficult to be mitigated in the networks due to bit quantization in delta-sigma modulation. In this paper, we propose a novel feedforward equalization (FFE) scheme based on the least mean square (LMS) algorithm for MFH networks employing 4th-order delta-sigma modulation technology with 1 and 2 bit quantization to alleviate the performance degradation caused by ISI. The performance of both 1-bit and 2-bit quantization systems employing the proposed FFE scheme with different tap lengths and step sizes has been systematically investigated. Our results show that, under the minimum computational complexity, the maximum transmission capacity can reach 8.98 Gbps when using the FFE scheme with 11 taps and step size of 3 × 10-5 or 3.5 × 10-5 and the average error vector magnitude (EVM) can be minimized to a level less than 0.032 with 19 taps and step size of 4 × 10-5 or 4.5 × 10-5 for 1-bit quantization system while for 2-bit quantization system, the maximum transmission capacity of 11.4 Gbps can be obtained when employing the FFE scheme with 19 taps and step size of 3.5 × 10-5 and the minimal average EVM less than 0.01 can be achieved with 19 taps and step size of 4 × 10-5. More hopefully, this work provides guidelines for optimizing the equalization scheme based on the requirements of EVMs, capacity, and computational complexity.

In response to the demand for efficient and high-precision detection in marine capture fishery, here the omnidirectional fishery sonar was developed to detect the targets in long distance using digital broadband and multiple beams. Broadband technology was used to effectively suppress the interference of interface and volume reverberation. Multiple beams were to improve the resolution of target detection. A distributed architecture of signal processing was also constructed for the omnidirectional fishery sonar using a field programmable gate array (FPGA). The omnidirectional fishery sonar was divided into multiple sectors. The underwater acoustics was simulated to determine the mutual constraints between the three main influencing parameters, namely the size of the transducer array, the maximum distance of detection, and the optimal point of operating frequency. The key parameters were then selected for the fishery sonar, according to the typical fishery vessels in China. The preferred frequency band of the signal was 20-30 kHz. A systematic investigation was also conducted on the effects of noise, interface reverberation, and volume reverberation on the detection performance of omnidirectional fishery sonar. A parallel and serial broadband beamforming FPGA was utilized to reduce the on-chip storage by 90% during operation; the Delta Sigma module was adopted to improve the signal-to-noise ratio of the transmission signal, where the noise within 20-30 kHz shifted to the frequency band above 50 kHz. A one-step stability of the predictive beam was improved using two-point recursive interpolation. The real-time stability errors of the beam were achieved at less than 1.6° (-0.8°-+0.8°) under significant sway of fishing vessels. The core components were also developed, such as a cylindrical transducer array, a highly integrated receiver and transmitter, and a 256 multi-channel signal processor, and system integration. 256 channels were independent receiving and transmitting for the signals in the 20-30 kHz frequency band. The scanning detection capabilities were for horizontal 360° and vertical 70°. The omnidirectional multi-beam fishery sonar was installed on the deep-sea fishery vessel. Environmental and simulated target detection tests were carried out on the fish school. The sea test results showed that the omnidirectional fishery sonar better performed stable, clear and continuous detection of environmental targets, where the detection ability of the 0 dB fish target reached more than 1 500 m. The key indicators of the self-developed omnidirectional sonar can fully meet the needs of marine fishing scenarios. The finding can greatly improve the detection performance of fishing for large-scale autonomous production. [ABSTRACT FROM AUTHOR]

Solid-state transformers (SSTs) are expected to become one of the most powerful and adaptable devices that allow controllable voltage, power factor correction, fault isolation, compact size as compared to their low-frequency (50 Hz/60 Hz) counterparts. The high-frequency isolation of single-phase modified quasi-Z-source AC–AC converter (SPM-qZAC) employing bidirectional switches to create the single-stage SPM-qZAC-based SST is proposed in this paper. The proposed topology offers all the benefits of conventional impedance source topologies, including single-stage power conversion with a small footprint, buck–boost operation and retaining or reversing the phase angle. Moreover, the presented converter topology allows to share the same ground between input and output voltage, continuous input current, no input–output LC filters and performs AC–AC power conversion without the use of DC storage, making it suitable for AC voltage regulation. This study introduces two modulation schemes for SPM-qZAC-based SST. Finite control set model predictive control (FCS-MPC) which is a current control technique at variable switching frequency is employed owing to the capabilities of modern digital signal processing. Further, an adaptive hysteresis band-based delta sigma modulation (DSM) technique that offers the benefit of constant switching frequency (CSF) is proposed as an alternative voltage control-based modulation of the same topology. Various performance indices including steady-state response, total harmonic distortion of source current and dynamic response are assessed through simulation studies using MATLAB/Simulink software and real-time simulation environment using RT-Lab with OPAL-RT OP4510. It is observed that SPM-qZAC exhibits good performance when modulated using either modulation techniques; however, CSF-DSM technique offers an additional benefit of constant switching frequency. [ABSTRACT FROM AUTHOR]

This article presents a new modulation technique called three-dimensional sigma–delta (3D- Σ Δ ) modulation for high-frequency three-leg four-wire voltage source converters (VSCs) that use wide-bandgap (WBG) semiconductors. These WBG devices allow for the use of high switching frequencies with a greater efficiency than silicon devices. The proposed 3D- Σ Δ technique enables operation at a variable switching frequency, resulting in a significant reduction in switching losses compared to classical pulse-width modulation (PWM) techniques. Moreover, the 3D- Σ Δ technique uses a fast-processing 3D quantiser that simplifies implementation and considerably reduces computational costs. The behaviour of the 3D- Σ Δ modulation is analysed using MATLAB/Simulink and PLECS. The experimental results performed on an active power filter that uses silicon carbide (SiC) MOSFETs demonstrate an improvement in converter efficiency compared to the conventional SPWM technique. Additionally, the experimental results show how 3D- Σ Δ allows for the compensation of harmonics and homopolar currents, thereby balancing the electrical grid currents. The experiments also show that the proposed 3D- Σ Δ modulation outperforms an SPWM technique in terms of power quality, since the former achieves a larger reduction in the harmonic content of the power grid. In conclusion, the proposed modulation technique is an attractive option for improving the performance of four-wire converters in active power filter applications. [ABSTRACT FROM AUTHOR]

Abstract This paper presents a high‐precision, low‐power delta‐sigma modulator (DSM) designed for healthcare and medical diagnostics. It utilizes a hybrid switching integrator to reduce distortion caused by the non‐linear on‐resistance of switches at a low supply voltage. Leveraging the characteristics of the hybrid switching integrator, a non‐50% duty cycle sampling timing and a corresponding tunable Miller‐compensated operational transconductance amplifier are proposed to reduce resistor thermal noise and meet lower power consumption requirements. The DSM is simulated based on 130‐nm CMOS technology and achieves 93.5‐dB signal‐to‐noise‐plus‐distortion ratio at a 1‐kHz bandwidth while consuming 23.7 µW from a 1.5‐V supply.

This paper presents a high‐precision, low‐power delta‐sigma modulator (DSM) designed for healthcare and medical diagnostics. It utilizes a hybrid switching integrator to reduce distortion caused by the non‐linear on‐resistance of switches at a low supply voltage. Leveraging the characteristics of the hybrid switching integrator, a non‐50% duty cycle sampling timing and a corresponding tunable Miller‐compensated operational transconductance amplifier are proposed to reduce resistor thermal noise and meet lower power consumption requirements. The DSM is simulated based on 130‐nm CMOS technology and achieves 93.5‐dB signal‐to‐noise‐plus‐distortion ratio at a 1‐kHz bandwidth while consuming 23.7 µW from a 1.5‐V supply. [ABSTRACT FROM AUTHOR]

This paper presents a prediction‐based dynamic range (DR) compensation technique in continuous‐time (CT) delta ‐sigma modulator (DSM) with digital‐domain noise coupling (DNC) structure. A digital prediction technique is proposed to address the issue of maximum stable amplitude (MSA) loss caused by DNC. The proposed prediction method has been shown to significantly extend the MSA of CT DSM with DNC. Moreover, through the extension of MSA, the DR and SNDR is significantly improved. A CTDSM with proposed compensation achieves a SNDR of 85.1dB at ‐1dBFS and a DR of 89dB. [ABSTRACT FROM AUTHOR]

Abstract This letter proposes a reconfigurable bandpass noise‐shaping successive approximation register analog‐to‐digital converter (ADC) with a cascade of integrators with feedforward (CIFF) structure. Unlike conventional CIFF structures that use a passive feedforward path, the new design incorporates an amplifier within the filter, providing effective bandpass noise transfer function regardless of passband location, and facilitating the use of a unity gain 2‐input comparator for low noise and high stability. The loop filter includes amplification by a low power Gm‐R amplifier and two‐step charge sharing. The proposed ADC supports three different intermediate frequencies (IFs), and 12‐bit resolution is achieved for all IFs in a 28‐nm complementary metal‐oxide‐semiconductor (CMOS) process.

In this paper, we study error diffusion techniques for digital halftoning from the perspective of 1-bit Σ Δ quantization. We introduce a method to generate Σ Δ schemes for two-dimensional signals as a weighted combination of their one-dimensional counterparts and show that various error diffusion schemes proposed in the literature can be represented in this framework via Σ Δ schemes of first order. Under the model of two-dimensional bandlimited signals, which is motivated by a mathematical model of human visual perception, we derive quantitative error bounds for such weighted Σ Δ schemes. We see these bounds as a step towards a mathematical understanding of the good empirical performance of error diffusion, even though they are formulated in the supremum norm, which is known to not fully capture the visual similarity of images. Motivated by the correspondence between existing error diffusion algorithms and first-order Σ Δ schemes, we study the performance of the analogous weighted combinations of second-order Σ Δ schemes and show that they exhibit a superior performance in terms of guaranteed error decay for two-dimensional bandlimited signals. In extensive numerical simulations for real-world images, we demonstrate that with some modifications to enhance stability this superior performance also translates to the problem of digital halftoning. More concretely, we find that certain second-order weighted Σ Δ schemes exhibit competitive performance for digital halftoning of real-world images in terms of the Feature Similarity Index (FSIM), a state-of-the-art measure for image quality assessment. [ABSTRACT FROM AUTHOR]

We describe challenges encountered in the design of continuoustime delta-sigma modulators that target high resolution (>16 bits) over wide bandwidths (several hundreds of kHz). The linearity of the feedback DAC and flicker noise introduced by the loop filter are primary problems that need to be addressed. We describe two techniques that are inherently more linear than prior-art DACs, namely the virtual-ground-switched resistor DAC and the zapped virtual-ground-switched dual return-to-open DAC. Flicker noise can be eliminated by chopping, but one needs to pay careful attention to minimize chopping artifacts. Example multi-bit and singlebit designs achieving in excess of 100 dB SNDR over a 250 kHz bandwidth, designed in a 180 nm CMOS technology, are used to illustrate the efficacy of the techniques described in this article. [ABSTRACT FROM AUTHOR]

Digital Image Processing has dominated Digital Signal Processing at the cost of more memory, resources, and high computational power. In image processing, filtering transformations and other operations need complex multiplications, and the multiplier is one of the most resources consuming elements. Recently, mitigating the multiplier complexity in the digital signal processing (DSP) algorithms sigma-delta modulation based general purpose and adaptive DSP algorithms are developed in MATLAB and compared with its counterpart multibit algorithms for functionality and area-performance-power in FPGA. The contemporary multiplier algorithms are also optimized to overcome the multiplier complexity challenge as computation becomes simple and fast. This paper extends the reported work by investigating the sigma-delta modulation approaches for developing a computationally efficient low-power image processing algorithm. The proposed model is designed, developed, and simulated in MATLAB. The simulation results are analyzed using SNR, MSE, and Peak SNR. The simulation results show that the proposed system can better mitigate the noise effect, making it robust for noisy environment. [ABSTRACT FROM AUTHOR]

This paper presents a BJT-based smart CMOS temperature sensor. The analog front-end circuit contains a bias circuit and a bipolar core; the data conversion interface features an incremental delta-sigma analog-to-digital converter. The circuit utilizes the chopping, correlated double sampling, and dynamic element matching techniques to mitigate the effects of process bias and nonideal device characteristics on measurement accuracy. Furthermore, based on the principle of charge conservation, the dynamic range utilization of the ADC increases. We propose a neural network that uses a multilayer convolutional perceptron to calibrate the sensor output results. Using the algorithm, the sensor achieves an inaccuracy of ±0.11 °C (3σ), exceeding the accuracy of ±0.23 °C (3σ) achieved without calibration. We implement the sensor in a 0.18 µm CMOS process, occupying an area of 0.42 mm2. It achieves a resolution of 0.01 °C and has a conversion time of 24 ms. [ABSTRACT FROM AUTHOR]

With the advent of wide band-gap semiconductors like SiC and GaN, the frequency of pulse-width modulation has increased. In modern electric drives, the switching frequency can reach 100 kHz or more. In this case the performance of the drive is limited by the delay in the current feedback measurement. This delay can be changed by using deltasigma modulators. This type of current sensors allows setting the measurement time. However, as the measurement time decreases, the accuracy of the feedback reduces. This paper proposes the algorithm in which the current controller uses variable-precision feedback. When the error between the reference and feedback is large, it uses faster but less accurate current feedback. When the error is small, it uses slower but accurate feedback. Changing the feedback measurement time requires changing the current controller gains. The algorithm was investigated on a virtual servo drive model. To evaluate the performance of the proposed regulator, the results were compared with standard regulators with different settings. It was proved that this approach allows increasing the speed of the current loop without loss in the transient performance. Besides, the algorithm increases the cut-off frequency in comparison with the standard slow and accurate controller.

The energy efficiency of analog-to-digital converters (ADCs) has improved steadily over the past 40 years, with the best reported ADC efficiency improving by nearly six orders of magnitude over the same period. The best figure-of-merit (FoM) is achieved with a limited class of ADC in terms of resolution and speed, but the coverage of the best FoM ADC has been expended. Many ADCs with the record FoM open up new applications and often incorporate multiple combinations of architectural and circuit innovations. It would be very interesting to follow a path of relentless optimization that could be useful to further expand the operating bandwidth of energy-efficient ADCs. To help along this path, this review article discusses the design techniques that focus on optimizing energy efficiency, involving successive approximation, pipelining, noise-shaping, and continuous-time operation.

In free space optical (FSO) communication, acquisition, tracking and pointing (ATP) is the key technology to maintain a high-quality FSO link. Specifically, the detection of pointing angle deviation greatly affects the performance of ATP, especially under weak receiving power. However, the separated beacon laser beam commonly used in ATP will increase the structural complexity of the terminal such as the size, weight, and power. It is unwanted in some limited applications such as satellite. To improve the pointing accuracy with weak signal in beaconless FSO communication, we propose a delta-sigma enabled beaconless cross-correlation (CCR) method with four-quadrant detectors. In the proposed method, a low-frequency sine analog signal for CCR calculation is modulated into a 1-bit digital signal by delta-sigma modulation and then inserted into the communication data as a training sequence. The root means square error (RMSE) of the pointing angle deviation measurement is 14.17 μrad with the incident optical power of −40 dBm. Compared with the direct intensity method, of which RMSE is 67.61 μrad, the proposed method can effectively improve the pointing accuracy with weak power without a beacon laser in FSO communication.

Synchronous detection is used to detect and measure very low-level signals in the presence of significant noise. A defining characteristic of this measurement approach is the use of a periodic probe signal to excite the system under test. This is followed by mixing of the reference signal and its phase-quadrature with the measured signal. Standard analog to digital converters are employed, usually with the mixing and filtering performed digitally. Most practical high-resolution analog to digital converters employ oversampled sigma-delta modulation and are incorporated as a separate functional block. This paper derives a processing algorithm that combines the oversampled analog to digital conversion with signal mixing into one functional block. There are several important advantages of this approach. The computational complexity of the lock-in amplifier is substantially reduced, with no loss of accuracy. Moreover, the requirement for high-resolution analog-to-digital conversion is relaxed; it is replaced with low-resolution high-rate sampling, which is typically much easier to realize in practice. Experimental results are presented to demonstrate the correctness of the technique as determined via theory and simulation. [ABSTRACT FROM AUTHOR]

The Real-time wearable Electrocardiogram (ECG) monitoring device is a perfect choice for assisting in detecting cardiovascular disease. A novel ECG beat classification algorithm is presented for continuous heart monitoring on low-processing-capacity wearable devices. We discuss the different wearable wristwatch monitoring system, which allows for continuous 24-h heart rate monitoring. This paper introduces a novel method for classifying arrhythmias based on deep learning. The method relies on QRS/PT detection, Sigma-Delta Modulation (SDM), One-Dimensional Convolution Neural Networks (1D-CNN) algorithms. The QRS/PT wave detection system is based on the 1D-CNN and SDM framework with local minimum and local maximum point algorithms. We proposed a Long Short-Term Memory (LSTM) recurrent neural network with a blend classifier. The classifier combines two small LSTM networks' predictions using two different features directly extracted from 1D-CNN and SDM bitstreams. The proposed model is evaluated by detecting QRS/PT waves and classifying arrhythmias using the MIT-BIH Arrhythmia Database. Five different classifications are performed and evaluated by the AAMI standard: N, F, Q, S, and V. The values for accuracy, positive predictivity, sensitivity, and F1-score are 99.56%, 96.5%, 93.87%, and 95.18%, respectively. The proposed algorithm detects QRS/PT in approximately 2050 ms and classifies each heartbeat in approximately 40–60 ms with wearable devices, and it consumes 1.5 μ w total power. The results indicate that our proposed system outperforms previous research in accuracy and meets both computation time and low power consumption requirements. [ABSTRACT FROM AUTHOR]

In this study, a digital calibration method applicable for a continuous‐time sigma‐delta analogue‐to‐digital converter is proposed using the AC injection technique. The proposed technique directly calibrates the integration accuracy of a converter instead of only trimming the capacitors. Compared with the existing calibration methods, the proposed method does not require complex timing logic processing or additional capacitors and does not adversely impact the dynamic performance of the converter. Furthermore, it ensures the accuracy of the converter, regardless of the non‐ideal effects of advanced processes. [ABSTRACT FROM AUTHOR]

This letter proposes a reconfigurable bandpass noise‐shaping successive approximation register analog‐to‐digital converter (ADC) with a cascade of integrators with feedforward (CIFF) structure. Unlike conventional CIFF structures that use a passive feedforward path, the new design incorporates an amplifier within the filter, providing effective bandpass noise transfer function regardless of passband location, and facilitating the use of a unity gain 2‐input comparator for low noise and high stability. The loop filter includes amplification by a low power Gm‐R amplifier and two‐step charge sharing. The proposed ADC supports three different intermediate frequencies (IFs), and 12‐bit resolution is achieved for all IFs in a 28‐nm complementary metal‐oxide‐semiconductor (CMOS) process. [ABSTRACT FROM AUTHOR]

Sigma-delta modulators use a noise-shaping technique to curtail the noise power in the band of interest during digital-to-analog conversion. Error feedback modulator employs an efficient noise transfer function for time varying inputs than any other sigma-delta modulators. However, the efficiency of the conventional noise transfer function degrades and the quantizer saturation issue provokes when the input signal reaches to full scale. This work proposes a new noise transfer function which is a combination of transfer functions of two-stage Feed-forward delays and a novel Hybrid multi-stage noise shaping-error feedback sigma-delta modulator. The noise transfer function of two-stage Feed-forward delays mitigates the concern of quantizer saturation. The noise transfer function offered by the Hybrid multi-stage noise shaping-error feedback architecture provides sustainable solutions to limit cycles and idle tones. The simulation concludes that the proposed noise-shaping approach obtains comparatively high signal-to-quantization noise ratio than the conventional error feedback modulators. Other performance parameters like spurious-free dynamic range, effective number of bits and signal-to-noise plus distortion ratio are also significantly improved. [ABSTRACT FROM AUTHOR]

The current study proposes three electrode-channels with time delay of artificial nerve signals generator utilized with only a active low pass filter and a Field Programmable Gate Array (FPGA). The XC3S100E FPGA board adopted to design a novel and realtime artificial transmembrane action potential (TMAP). The implementation of one bit Sigma Delta Modulation (SDM) method with linearized technique could be very expensive and complicated products with other technologies option currently available such as a microcontroller due to the fabrication requirements. This technique could employ in many biomedical applications and testing efficiently, especially, in evaluating the multi-electrode cuff system without requiring use of real nerves spike from animal models and saving time and effort, and cost. Moreover, this approach is adopted for further improvement to the signal performances such as resolution, accuracy, differential linearity monotonic DAC, and settling time of the signal waveform without extra hardware or cost required. In addition, the design included three channels of white Gaussian noise uncorrelated for each TMAP signal to simulate the real nerve noise environment, which surrounds the electrode cuff in experimental cases. A noise channels with adjustment level is added to the nerve spike using three sets of taps are employed to provide three channels of noise sources. The Xilinx ISE platform and Mentor Graphics ModelSim tool are used to simulate and implement this, and the results produced are compared. The power consumption of conventional technology is 31 mW, which is significantly higher than the power consumed (21mW) in modern technology. Furthermore, as compared to the usual way, the proposed solution conserved around 10% of the FPGA resources. This technique offers reuse in other applications where delay time, low amplitude voltage signals, and multichannel generator is needed. Moreover, this system offers adjustable waveform signal, noise level, conduction velocity and time delay easily to adequate different applications and tests. [ABSTRACT FROM AUTHOR]

Summary: Direct pulse width modulated (PWM) AC–AC converters, derived from their DC–DC counterparts, serve as promising media for AC–AC power conversion because they offer benefits, such as single‐stage power conversion, absence of bulky DC links, and small footprint. In this study, a single‐phase (1−ϕ) AC–AC zeta converter was analyzed under buck, boost, and buck‐boost operations. Delta‐sigma modulation (DSM) technique, known for its simple logic implementation, excellent reference‐tracking property, robust control, and fast transient response, was employed for the load voltage control of a 1−ϕ AC–AC zeta converter. However, the conventional DSM technique relies on a fixed hysteresis band (FHB) for restricting the integrated (sigma) error (delta) between the reference and estimated control voltages within a narrow band, which causes the converter to operate at a variable switching frequency (VSF). Although VSF enhances the converter performance with low total harmonic distortion (THD) and high degree of flexibility over waveform quality, it poses serious implications such as higher switching losses, putting more strain on thermal management of switches. This paper presents a constant switching frequency‐based DSM technique based on an adaptive hysteresis band (AHB) for a 1−ϕ AC–AC zeta converter. The converter is controlled using FHB‐DSM and AHB‐DSM techniques, and a comparison is drawn between the two in terms of various performance indices. In this comparison, FHB‐DSM serves as a benchmark and an optimum switching frequency based on AHB‐DSM technique is determined, which exhibits low switching losses while maintaining the same THD limits, dynamic response, and waveform quality as that of FHB‐DSM technique. The proposed strategy was validated by simulation studies in MATLAB/SIMULINK software. Furthermore, a real‐time simulator, OPAL‐RT (OP4510), was used to validate the study with real‐time implementation. [ABSTRACT FROM AUTHOR]

A rapid design and verification of sigma delta modulators are presented at the system level with high accuracy and computational efficiency. Sigma delta analog to digital converters showcased an excellent choice for low bandwidth applications from near DC to high bandwidth standard 5G applications. The conceptualization of the graphical user interface (GUI) in the efficient selection of integrator weights has been proposed, which solves various tradeoffs between various abstraction levels. The sigma delta modulator of the 5th order is designed and simulated using the proposed design methodology of calculating integrator weights for targeted specifications. The efficiency of design exploration and optimum selection of integrator coefficients has been investigated on single loop architectures. Power and performance of the selected modulator has been verified in the time domain behavioral simulation. The discrete time circuit technique has been adopted for design of distributed feedback, feed forward architectures and comparison of performance metrics done between selected architectures. A huge design space is computed for the best design parameters that offers ultra-low power and high performance. The proposed virtual instruments supported the methodology for designing delta sigma modulators at the system level achieving SNDR of 122 dB over a bandwidth of 5 kHz at a clock frequency of 1 MHz. [ABSTRACT FROM AUTHOR]

Variable speed drives incorporating multiphase motors have started gaining attention in recent years due to their benefits over three-phase counter parts. In this article, we propose a digital control scheme based on space vector pulse density modulation for two-level five phase induction motor drive. The scheme combines principles of digital signal processing techniques, such as sigma delta modulation and vector quantization, along with space vector modulation to form computationally efficient motor drives. In this article, vector space is divided into ten nonoverlapping regions, with each region partitioned into three voronoi regions. The reference vector is vector quantized to the nearest switching vector. Absence of dwell time calculations, less memory requirements, and reduced computational complexity of the scheme along with reduced acoustic noise and electromagnetic interference in the drive are the core advantages of the scheme. The work has been experimentally implemented with 2 HP five-phase induction motor drive and the results are compared with space vector pulsewidth modulation scheme for validation purpose. [ABSTRACT FROM AUTHOR]

In this brief, a self-calibrated two-point delta-sigma modulation technique for a CMOS RF transmitter is proposed for use for a voltage-controlled oscillator (VCO) and a delta–sigma modulator in a frequency synthesizer. By using the counter to calibrate the frequency deviation of two-point modulation to the desired value, the gain mismatch between two paths can be completely calibrated by modifying the gain of the VCO path. The frequency modulation therefore guarantees a robust performance against PVT variations without using any additional circuit. This technique is applied to Bluetooth Low Energy (BLE) applications. The proposed Two-Point Modulation achieves error vector magnitude (EVM) of −29.3 dB at 1 Mbps and is implemented in 55 nm CMOS process technology. The area of the chip is 0.28 mm2 and its power consumption is 2.9 mW. [ABSTRACT FROM AUTHOR]

Image degradation, caused by various factors, often results in noise and blur. For image restoration, inverse filters are typically used, while Wiener filters are employed for noise reduction. Unlike text or voice processing, image processing deals with significantly larger data volumes, necessitating greater computational resources. This demand can saturate resource-limited hardware such as FPGAs and ASICs, making architectural optimization essential for designing a complete System on Chip or Network on Chip. Although several hardware optimization methods exist in the literature, each has its limitations. Sigma-Delta Modulation has emerged as a promising technique in recent years, particularly for reducing the complexity of DSP systems by shortening word lengths from multi-bit to single-bit. This reduction simplifies systems and conserves hardware resources. While SDM has been widely applied in various domains, including basic arithmetic and complex adaptive filters, its use has been largely confined to speech and text processing. In recent work, the authors proposed a novel application of SDM in image processing. This study extends that investigation by designing a single-bit SDM-based Wiener filter for image noise reduction. The proposed single-bit filter is functionally compared against traditional Wiener filters, Steepest-Descent filters, and Adaptive Mean filters. Key statistical metrics such as noise variance, signal-to-noise ratio, Mean Squared Error, and Peak SNR are simulated and analyzed for real-time performance evaluation. The results demonstrate that the proposed single-bit technique remains robust against noise in dynamic environments. An FPGA-based implementation of the single-bit system further highlights its efficiency, requiring fewer resources and consuming less operational power. The findings confirm that the proposed design outperforms conventional methods in terms of effectiveness, statistical performance, and resource-optimized implementation, thereby enhancing its acceptability and robustness. The study is further strengthened by qualitative and quantitative analyses, with simulation results clearly illustrating the advantages of the proposed single-bit filter over conventional multi-bit approaches. [ABSTRACT FROM AUTHOR]

For the fronthaul link in the fifth-generation (5G) wireless networks, optical fiber is one of the most widely used medium, owing to its large bandwidth and low transmission loss. However, in some scenarios, especially the dense urban areas, the installation of fiber optic cables is costly and difficult to establish. Alternatively, the free space optical (FSO) link can be installed easily and spans complex terrain. In this context, we propose and experimentally demonstrate a hybrid FSO/Wireless transmission system based on bandpass delta-sigma modulator and real-time coherent transponder. Advantage of the proposed technique is twofold. Firstly, coherent detection is applied to improve the system sensitivity compared to conventional direct detection. Secondly, delta-sigma modulation (DSM) is utilized to greatly simplify the wireless transmitters and to enhance the bandwidth flexibility. Over a 50-m FSO and 1-m wireless link, a 64-QAM wireless signal at 1 GHz with 500 MHz bandwidth is successfully transmitted. With 16 wavelength division multiplexing channels, the total throughput of the system is up to 24 Gb/s. Meanwhile, the error vector magnitude (EVM) of all channels is around 2.68% and 6.51%, which are demonstrated after FSO and FSO/Wireless transmission, respectively. The results meet the requirement of the third-generation partnership project release 15 with EVM value of 8% for 64-QAM. Moreover, sensitivity of the real-time coherent receiver is lower than −48 dBm under the 7% forward error correction limit with bit error rate of 3.8e-3.

Internet of everything is being build up rapidly, which causes much higher requirements towards the flexibility of communication resources, especially the adaptivity of the fronthaul to various transmission distances and capacities. In this paper, we proposed a low-cost and spectrum efficient 5G fronthaul broadband connection solution that combines hierarchical modulation technology and delta-sigma modulation. The proposed scheme can double the number of accesses without occupying extra wavelengths. Moreover, such architecture can flexibly allocate the SNR of a group of remote radio units for different user requirement of transmission rate and reaches. Simulation results show that the proposed scheme can increase the access distance of the fronthaul network by 23% and the capacity by 16.7%. The feasibility of the solution is verified through a proof-of-concept experiment. After 20 km transmission, the OFDM-64QAM and -256QAM signal with a center frequency of 3.5 GHz and a bandwidth of 500 MHz can meet the EVM requirements of 8% and 3.5%, respectively. And when the ${R_{LM}}$ of the hierarchical PAM4 signal is 0.6, the ROP required by the most-significant bit branch can be reduced by ∼1.5 dB.

This brief presents a 2.16 $\mu \text{W}$ low-power third-order single-bit continuous-time delta-sigma modulator (CTDSM) for electrocardiogram (ECG) signal acquisition application. The proposed CTDSM uses an active-RC (A-RC) integrator as a first integrator and an improved linearized $G_{m}$ -C integrator for the second and third integrators, respectively. The mixed-integrator structure helps to mitigate the trade-offs between power consumption and resolution. Moreover, a source-degenerated auxiliary differential pair circuit is used for the $G_{m}$ -C integrators to improve their linearity. By using A-RC and $G_{m}$ -C integrators together along with an improved-linearized $G_{m}$ block, the total power consumption was measured as 2.16 $\mu \text{W}$ with a peak signal-to-noise ratio of 80.1 dB, signal-to-noise, and distortion ratio of 78.4 dB, and a dynamic range of 81.4 dB with a bandwidth of 250 Hz. Furthermore, a real-time ECG signal was successfully captured in an ECG acquisition system that consisted a heart-rate sensor and a signal acquisition circuit, including the proposed CTDSM. [ABSTRACT FROM AUTHOR]

In energy harnessing applications there are instances where energy should be transferred from a low-power, low-leakage backup battery to a temporary power delivery output capacitor. The high power delivery feature of the storage capacitor usually comes at the price of higher leakage current and thus it cannot replace the long-term energy storage backup battery. This paper presents a CMOS capacitor charger circuit which connects a long term low power battery to a short-burst high power delivery capacitor. The proposed circuit uses a switching output stage with an external inductor to reduce the dissipation during the capacitor charge-up cycle. A sigma-delta modulation approach is used to control the power switches. Under low power transfer scenarios which perform transfer in a longer duration, the proposed approach shows better performance compared with previously presented techniques. It is shown that under different transfer durations the control section only consumes 970nWs. The efficiency of the proposed circuit is more than 90% for average input powers in the 0.7 mW to 2 mW range. [ABSTRACT FROM AUTHOR]

This article describes the improvement of volt standards based on the Josephson effect as a development stage of VNIIM quantum volt standards. The equipment was created and improved based on the "superconductor– insulator–superconductor"-type Josephson array for reproducing direct current voltages up to 10 V. This work presents the development results of transportable quantum standards based on the "superconductor– normal metal–superconductor" and "superconductor–insulator–normal metal–insulator–superconductor" Josephson anhysteretic arrays. The findings reveal that anhysteretic arrays can be used to reproduce constant voltages and voltages of the arbitrary form by approximating signals with Josephson taps and pulsed sigma-delta modulation, which reproduces voltages with a given harmonics level. The results of the study on the transfer of a unit of volt to the measuring channels of alternating voltages with high-precision analog-to-digital converters from the state primary standard of electric power units in the frequency range from 1 to 2500 Hz GET 153-2019 are presented. [ABSTRACT FROM AUTHOR]

Various sigma–delta ($\Sigma$ $\Delta$) modulation techniques for reducing the maximum peak-to-peak amplitude of common-mode voltage (CMV) by 80% in a five-phase, high-frequency voltage source inverter (VSI) are proposed and evaluated in this article. These techniques are based on choosing a set of vectors that limits the CMV amplitude. Operating the VSI under high-frequency pulsewidth modulations (PWM) generates a large number of changes in the CMV levels, which leads to common-mode currents (CMCs) and conducted electromagnetic interferences (EMIs). The proposed modulation techniques achieve the following: 1) High-efficiency converter operation and output voltage with low total harmonic distortion (THD); 2) an 80% reduction in CMV peak-to-peak amplitude; 3) a decrease in the number of the CMV transitions, thus reducing the CMCs; and 4) a decrease in the conducted EMI amplitude. The use of single-loop and double-loop $\Sigma$ $\Delta$ modulators is analyzed by means of Matlab/Simulink and PLECS simulations. The implementation of the proposed modulation techniques has been experimentally evaluated using a five-phase VSI with silicon carbide semiconductors. In order to demonstrate the improved performance, the results obtained are compared with those of other PWM and space vector modulation techniques that also mitigate the CMV amplitude by 80% but lack the other improvements. [ABSTRACT FROM AUTHOR]

Consider the following distributed optimization scenario. A worker has access to training data that it uses to compute the gradients while a server decides when to stop iterative computation based on its target accuracy or delay constraints. The server receives all its information about the problem instance from the worker via a rate-limited noiseless communication channel. We introduce the principle we call differential quantization (DQ) that prescribes compensating the past quantization errors to direct the descent trajectory of a quantized algorithm towards that of its unquantized counterpart. Assuming that the objective function is smooth and strongly convex, we prove that differentially quantized gradient descent (DQ-GD) attains a linear contraction factor of $\max \{\sigma _{\mathrm {GD}}, \rho _{n} 2^{-R}\}$ , where $\sigma _{\mathrm {GD}}$ is the contraction factor of unquantized gradient descent (GD), $\rho _{n} \geq 1$ is the covering efficiency of the quantizer, and $R$ is the bitrate per problem dimension $n$. Thus at any $R\geq \log _{2} \rho _{n} /\sigma _{\mathrm {GD}}$ bits, the contraction factor of DQ-GD is the same as that of unquantized GD, i.e., there is no loss due to quantization. We show a converse demonstrating that no algorithm within a certain class can converge faster than $\max \{\sigma _{\mathrm {GD}}, 2^{-R}\}$. Since quantizers exist with $\rho _{n} \to 1$ as $n \to \infty $ (Rogers, 1963), this means that DQ-GD is asymptotically optimal. In contrast, naively quantized GD where the worker directly quantizes the gradient barely attains $\sigma _{\mathrm {GD}} + \rho _{n}2^{-R}$. The principle of differential quantization continues to apply to gradient methods with momentum such as Nesterov’s accelerated gradient descent, and Polyak’s heavy ball method. For these algorithms as well, if the rate is above a certain threshold, there is no loss in contraction factor obtained by the differentially quantized algorithm compared to its unquantized counterpart, and furthermore, the differentially quantized heavy ball method attains the optimal contraction achievable among all (even unquantized) gradient methods. Experimental results on least-squares problems validate our theoretical analysis. [ABSTRACT FROM AUTHOR]

We consider the problem of estimating the mean of a symmetric log-concave distribution under the constraint that only a single bit per sample from this distribution is available to the estimator. We study the mean squared error as a function of the sample size (and hence the number of bits). We consider three settings: first, a centralized setting, where an encoder may release $n$ bits given a sample of size $n$ , and for which there is no asymptotic penalty for quantization; second, an adaptive setting in which each bit is a function of the current observation and previously recorded bits, where we show that the optimal relative efficiency compared to the sample mean is precisely the efficiency of the median; lastly, we show that in a distributed setting where each bit is only a function of a local sample, no estimator can achieve optimal efficiency uniformly over the parameter space. We additionally complement our results in the adaptive setting by showing that one round of adaptivity is sufficient to achieve optimal mean-square error. [ABSTRACT FROM AUTHOR]

This article presents a highly digital robust voltage-controlled oscillator (VCO)-based front end for multiplexed single-ended resistive sensor readout applications. The architecture features a modified digital phase-locked loop (DPLL) structure that enables second-order noise shaping without any operational transconductance amplifiers (OTAs) and a single feedback digital-to-analog converter (DAC). The direct conversion of the sensor input resistance to time-domain information obviates the need for any conditioning circuit, thus resulting in a highly digital and area-compact architecture. The closed loop substantially reduces the amplitude of the signal at the VCO input, thereby achieving high linearity. To ensure high robustness against supply and temperature variations, a double measurement approach is employed. Fabricated in a 180-nm CMOS process with a 0.1-mm2 active area, the sensor readout consumes 109 $\mu \text{W}$ of power and achieves a resolution of 96.9 dB for 0.5-ms conversion time, resulting in a Schreier figure of merit (FoM) of 166.5 dB. The circuit only requires a cheap and efficient single-point trimming calibration at room temperature. The low conversion time enables multiplexing among multiple sensor readouts. The supply and temperature sensitivities are 0.4%/V and 36 ppm/°C, respectively. [ABSTRACT FROM AUTHOR]

The issue of accurate reception of signals in wireless communication systems is a constant concern due to the presence of noise/fading/interferences that may occur on the transmission path. Acknowledging that 5G requirements for these systems increase the standards related to high throughput and lowest bit error rate (BER), noise reduction must be performed to achieve reliable communication. Delta-sigma modulation (DSM) proved to be cost efficiency and reduced circuit complexity technique. Therefore, the performance of DSM is analyzed in a potential 5G-compliant system in Additive White Gaussian Noise, Nakagami-m and Weibull fading channels in the context of BER reduction. The main goal is to offer some landmarks related to expectations of DSM use in an OFDM-based communication system. The performance is evaluated for different sets of spreading sequences (Walsh-Hadamard and pseudo-noise) and based on the simulation results several conclusions are highlighted. Further improvement will be proposed for noise effects reduction and interference minimization in DSM-based 5G-compliant systems. [ABSTRACT FROM AUTHOR]

Abstract Bitstream modulated transmitters may offer improved power efficiency and linearity simultaneously in RF power amplifiers. Several modulation techniques including envelop delta-sigma modulation and envelope pulse width modulation have been applied. The out-of-band quantization noise associated with these modulations may be rejected by a high-quality factor output filter, yet the in-band quantization noise needs to be further suppressed to meet the requirement of the emission mask. The proposed channelized active noise elimination technique can offer additional quantization noise suppression through software control without involving a passive filter. The essential concept is based on combining the outputs of multiple channels of Pas that have digitally controlled delays to form a FIR filter in analogue domain. A two-channel and a four-channel GaN power amplifiers are built to demonstrate this noise suppression concept and power combiners based on T-junction with quarter wavelength transmission line are proposed to retain the high power efficiency of the transmitters.

Fractional- $N$ frequency synthesizers that use a digital $\Delta $ – $\Sigma $ modulator (DDSM) to control the feedback divider can exhibit spurious tones that move about in the frequency domain; these are known colloquially as “walking” or wandering spurs. Building upon a theoretical explanation of the origin of wandering spurs, this article presents two methods to suppress them. It describes a 4.9-GHz 180-nm SiGe BiCMOS charge-pump phase-locked loop (CP-PLL) fractional- $N$ frequency synthesizer platform with a divider controller that can function as: 1) a standard MASH 1-1-1; 2) a MASH 1-1-1 with high-amplitude dither; and 3) a MASH 1-1-1 with a modified third stage. Measurements confirm the effectiveness of the wandering spur suppression strategies. [ABSTRACT FROM AUTHOR]

This article presents a delta sigma modulator (DSM) analog to digital (ADC) that uses ring amplifiers as integrators to relax speed and efficiency bottlenecks in discrete-time (DT) oversampled ADCs. Its multi-bit quantizer is based on split source (SS) comparators, adding flexibility and power efficiency. The complete oversampling ADC is designed as a 3rd-order cascade of integrator with feed forward (CIFF) with a 4-bit quantizer, and it achieves a peak signal-to-noise and distortion ratio (SNDR) of 67 dB and DR of 70.0 dB with 47.5-MHz bandwidth when clocked at 950 MHz. This is the highest bandwidth reported to date among single-channel DT DSM ADCs and demonstrates a viable alternative to continuous-time (CT) DSM ADCs for wideband oversampling applications. With a power consumption of 4.7 mW from a 1-V supply, figure of merit (FoM) Schreier and Walden are 167.0 dB and 27.0 fJ/c.s, respectively, demonstrating efficient DT delta-sigma conversion with high bandwidth. [ABSTRACT FROM AUTHOR]

Figure 3 shows the schematic of the proposed HT ht known as MASH. The carrier frequency HT ht is 3.5 GHz. The RF signals digitized by 1-bit MASH HT ht is a 256 QAM modulated LTE signal of 20 MHz. [Extracted from the article]

This paper presents a BJT-based smart CMOS temperature sensor. The analog front-end circuit contains a bias circuit and a bipolar core; the data conversion interface features an incremental delta-sigma analog-to-digital converter. The circuit utilizes the chopping, correlated double sampling, and dynamic element matching techniques to mitigate the effects of process bias and nonideal device characteristics on measurement accuracy. Furthermore, based on the principle of charge conservation, the dynamic range utilization of the ADC increases. We propose a neural network that uses a multilayer convolutional perceptron to calibrate the sensor output results. Using the algorithm, the sensor achieves an inaccuracy of ±0.11 °C (3σ), exceeding the accuracy of ±0.23 °C (3σ) achieved without calibration. We implement the sensor in a 0.18 µm CMOS process, occupying an area of 0.42 mm2. It achieves a resolution of 0.01 °C and has a conversion time of 24 ms.

In this paper, we proposed an improved mobile fronthaul architecture employing the SNR-improved delta-sigma digitization scheme and 4-level pulse amplitude modulation (PAM-4) format. Different from traditional 2-bit quantization, this scheme deploys two-fold delta-sigma quantization, which uses 1-bit delta-sigma modulator to quantize the signal, and another 1-bit delta-sigma modulator to quantize the in-band noise. A significant reduction of the in-band noise can be achieved only applying a differentiator, bringing about a much better noise shaping performance. Meanwhile, the two 1-bit streams can be combined and transmitted in a PAM-4 manner through an intensity modulation direct detection (IM-DD) channel. We have successfully experimentally demonstrated the digitization and transmission of 65536 quadrature amplitude modulation (QAM) baseband orthogonal frequency division multiplexing (OFDM) signal with sampling rate of 1.25 GSa/s over 20-km fiber with standard 10-Gbaud PAM-4 signal, with a signal to noise ratio (SNR) of 57.7 dB. Compared to the conventional 2-bit quantized OFDM scheme, experimental results show that a significant SNR improvement of 17.7 dB has been achieved by the proposed scheme. In addition, we also realized a transmission of 16384-QAM intermediate frequency (IF) signal at the center frequency of 3.5 GHz (with an SNR of 49.6 dB). An improvement of 15.9 dB can also be maintained. [ABSTRACT FROM AUTHOR]