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A computational rheooptical model based on the integration of liquid crystal polymer flow equations and two well-known polarized light transmission methods is formulated and applied to the ubiquitous periodic banded textures observed in sheared lyotropic nematic polymers. The selected optical methods are the matrix-type Berreman method and the finite-difference time-domain (FDTD) direct numerical simulation method. The optical response of a single unit cell of the periodic banded texture of sheared lyotropic nematic polymers to polarized light propagation under cross-polars is analyzed and correlated to the shear-induced orientation field previously reported in Han and Rey [W.H. Han, A.D. Rey, Theory and simulation of optical banded textures of nematics polymer during shear flow, Macromolecules 28 (1995) 8401–8405]. The role of orientation gradients on the optical response is elucidated and shown to be source of lack of accuracy of the Berreman matrix method. The findings provide robust guidelines on the applicability and accuracy of matrix and direct numerical simulation optical methods. Computational rheooptics of liquid crystal polymers based on the FDTD method is an additional tool to understand flow-induced texture formation when used in the direct forward mode, and in quantitative assessments of rheological material properties when used in backward mode.

Isotactic polyacrylonitrile (PAN) has been prepared by using a zeolite as a host. After introduction of acrylonitrile monomers, they were subsequently polymerized with radical initiators in Na–Y and Na–β zeolite channels, followed by extraction with hydrofluoric acid. 13C-NMR results show that the isotacticity of extracted PAN is higher than that of bulk PAN prepared under the same reaction conditions and is also affected by the pore structure of host. Thermal and physical properties of extracted PAN were also investigated using GPC, DSC and XRD.

The electrical characterization of p-n diodes fabricated using a newly developed high temperature (⩾ 1100 °C) boron diffusion source consisting of a homogenous distribution of 9Al2O3·2B2O3 in a SiC foam substrate was carried out and results were compared with those obtained using commercial sources. Specifically, current-voltage and open circuit voltage decay measurements were performed. The results obtained indicate that devices fabricated from the new high temperature source perform satisfactorily, exhibiting characteristics that are comparable to the characteristics of devices fabricated from the established commercial high temperature boron diffusion sources.

The problem of determining floorplans with optimum area utilization is addressed. To enable the application of dynamic programming, the problem is first transformed into that of determining all floorplans within a specified tolerance of the perfect floorplan. It is shown that for slicing floorplans the problem of enumerating floorplans is related to enumerating two-partitions. Tests to identify redundant partial floorplans are derived, and it is shown that abandoning them does not violate the principle of optimality of dynamic programming. A novel ordering of two-partitions is derived, which enables determination of the wire length cost of successive two-partitions in constant time. Results for a set of benchmark circuits are presented. >

We present a comprehensive methodology for modeling, as a function of time, increased standby leakage current of VLSI circuits due to soft-breakdown. Predictions, using a post-soft-breakdown leakage-scaling model and device-level time-dependent dielectric breakdown (TDDB) data, agree remarkably well with observations of circuit leakage. The implications of this predictive model for the leakage current regarding the appropriate evaluation of the absolute reliability of intrinsic, ultra-thin oxides are discussed.

An approach to object-oriented description of reconfigurable parallel architectures based on an extended communicating sequential processes (CSP) model of communication is presented. A workbench called OODRA (object-oriented design of reconfigurable architectures), has been designed and implemented, based on this approach which is suitable for the development of highly concurrent, special-purpose, reconfigurable architectures. Intended uses of OODRA include parallel algorithm/architecture functional simulation and reconfiguration algorithm simulation, with an interactive graphical interface for parallel architecture design. Visual programming and parameterized architecture family approaches to design are supported. >

To monitor plasma charging damage, it is common to use extremely large antenna ratio (AR) testers to improve sensitivity. Calculating how the measured damage to these large AR testers impacts product is a serious issue that has not yet been resolved. Without the ability to predict the damage impact to product, and hence to quantitatively establish antenna design rules, the only way to ensure product reliability is to reduce damage as best we can and to use tight design rules. Such practice is extremely costly and provides no assurance. The purpose of this paper is to illustrate a quantitative methodology to deal with the above-mentioned problem using a real example.

In this work, a new commercial system allowing non-contact measurement of the surface charge is used to monitor the condition of the silicon surface following HF/water etch. Results obtained demonstrate that by monitoring changes of surface charge using this system, a truly non-invasive, instant and easy to carry out characterization of Si surfaces after HF/water etch can be accomplished. The results show that HF/water exposure adds positive charge to the silicon surface. Change in the surface charge, considered to be indicative of the change in the electro-chemical condition of the surface, appears to precede initiation of the oxide etching process, and is proposed to be a factor in initiating etching reactions that involve mainly negatively charged species.

This paper proposes a new representation of nets for gate matrix layout, called dynamic-net-lists. The dynamic-net-list representation is better suited for layout optimization than the traditional fixed-net-list since with it net-bindings can be delayed until the gate-ordering has been constructed. Based on dynamic-net-lists, an efficient modified min-net-cut algorithm has been developed to solve the gate ordering problem for gate matrix layout. This new approach is shown through theoretical analysis and experimental results to reduce the number of horizontal tracks and hence the area significantly. The time complexity of the algorithm is O(N log N), where N is the total number of transistors and gate-net contacts. It is also shown that an ideal min-net-cut algorithm for optimal gate matrix layout with n gate signals is at worst a log-n approximation algorithm and is conjectured to be a relative approximation algorithm.

This paper describes the application of the Object-Oriented Design of Reliable/Reconfigurable Architectures (OODRA) workbench to the performance simulation of an adaptive digital beamforming architecture. The performance effects due to chip partitioning and reconfiguration for fault tolerance and yield enhancement are presented. The experiments described illustrate the flexibility of the OODRA work-bench in architectural-level performance evaluation of algorithm-specific reconfigurable architectures.