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The surface-potential-based compact MOS model PSP is reviewed with special emphasis to features of interest to analog and RF designers. Various aspects of the model are discussed, such as Gummel symmetry, capacitance reciprocity at V DS = 0 V, parasitic resistances, junction modeling, distortion modeling, and noise modeling. Examples from circuit design are used to illustrate the benefits of the PSP model.

This paper presents the results of several qualitative ldquobenchmarkrdquo tests that were used to verify the physical behavior of the PSP model and its usefulness for future generations of CMOS IC design. These include newly developed tests and new experimental data stemming from low-power, RF, mixed-signal, and analog applications of MOSFETs.

This paper reports recent progress in partially depleted (PD) SOI MOSFET modeling using a surface potential based approach. The new model is formulated within the framework of the latest industry standard bulk MOSFET model PSP. In addition to its physics-based formulation and scalability inherited from PSP, PSP-SOI captures SOI specific effects by including floating body simulation capability, parasitic body currents and capacitances. A nonlinear body resistance model is included for accurate characterization and simulation of body-contacted SOI devices. The PSP-SOI model has been verified using test data from 90 nm to 65 nm PD/SOI processes.

This paper describes the latest and most advanced surface-potential-based model jointly developed by The Pennsylvania State University and Philips. Specific topics include model structure, mobility and velocity saturation description, further development and verification of symmetric linearization method, recent advances in the computational techniques for the surface potential, modeling of gate tunneling current, inclusion of the retrograde impurity profile, and noise sources. The emphasis of this paper is on incorporating the recent advances in MOS device physics and modeling within the compact modeling context

A new physics-based junction model for CMOS, called JUNCAP2, is presented. It contains new single-piece formulations for the Shockley-Read-Hall generation/recombination current and the trap-assisted tunneling (TAT) current, which are valid both in forward and reverse mode of operation. Moreover, the TAT model extends the existing model (IEEE Trans. Electron Devices, vol. 39, p. 2090, 1992) to the high electric fields encountered in today's CMOS technologies. Furthermore, the model contains expressions for junction capacitance, ideal current, band-to-band tunneling current, avalanche breakdown, and junction shot noise. The parameter extraction is also discussed in this paper

The spline collocation-based nonquasi-static (NQS) model is further developed to include all regions of operation and small-geometry effects. The new formulation provides a unified (hence consistent) approach to both large-signal and small-signal NQS modeling and is sufficiently flexible to work with any surface-potential-based MOSFET model. The model is verified through comparison with the channel segmentation method, two-dimensional numerical simulations, and experimental results and demonstrates a controlled tradeoff between model accuracy and efficiency. The new NQS model has been implemented into PSP model. Circuit simulations are given to demonstrate the accuracy and applicability of the new model

In compact transistor modeling for circuit simulation, the capacitances of conventional MOS devices are commonly determined as the derivatives of terminal charges, which in their turn are obtained from the so-called Ward-Dutton charge partitioning scheme. For devices with a laterally nonuniform channel doping profile, however, it is shown in this paper that no terminal charges exist from which the capacitances can be derived. Instead, for such devices, a new model is presented for the capacitances themselves. Furthermore, a method is given to incorporate such a capacitance model into circuit simulators, which are traditionally based on terminal charge models. Comparison with two-dimensional device simulations and a segmentation model shows that for a constant mobility, the new capacitance model provides an accurate description for a MOSFET with a laterally diffused channel doping profile. Through a comparison with high-frequency measurements, the agreement between model and experimental results is discussed.

The impact of scaling on the analog performance of MOS devices at RF frequencies was studied. Trends in the RF performance of nominal gate length NMOS devices from 350-nm to 50-nm CMOS technologies are presented. Both experimental data and circuit simulations with an advanced validated compact model (MOS Model 11) have been used to evaluate the RF performance. RF performance metrics such as the cutoff frequency, maximum oscillation frequency, power gain, noise figure, linearity, and 1/f noise were included in the analysis. The focus of the study was on gate and drain bias conditions relevant for RF circuit design. A scaling methodology for RF-CMOS based on limited linearity degradation is proposed.

The geometrical scaling of the intrinsic source/drain series resistance of MOSFETs has been investigated experimentally using a large selection of transistor geometries in 0.5 μm CMOS technology. It is found that for narrow-width transistors with a dogbone layout the total source/drain resistance R SD is overestimated considerably when conventional width scaling R SD ∝ W E −1 is applied. This experimental observation is corroborated by simulations based on a three-dimensional network model. The role of the silicide layer in this context is discussed explicitly using a transmission line model. Based on the experiments and simulations, a new scaling rule for the source/drain resistance and thus for the corresponding parameter θ 1 of MOS Model 9 [Velghe RMDA, Klaassen DBM, Klaassen FM. IEDM ‘93 Technical Digest, pp. 485–488 (see also: http://www.semiconductors.philips.com/Philips_Models)]. is derived, which leads to a considerably improved modelling accuracy in both the linear and saturation regime for narrow-width MOSFETs.

The impact of statistical dopant fluctuations on the threshold voltage V/sub T/ and device performance of silicon MOSFET's is investigated by means of analytical and numerical modeling. A new analytical model describing dopant fluctuations in the active device area enables the derivation of the standard deviation, /spl sigma/V/sub T/, of the threshold voltage distribution for arbitrary channel doping profiles. Using the MINIMOS device simulator to extend the analytical approach, it is found that /spl sigma/V/sub T/, can be properly derived from two-dimensional (2-D) or three-dimensional (3-D) simulations using a relatively coarse simulation grid. Evaluating the threshold voltage shift arising from dopant fluctuations, on the other hand, calls for full 3-D simulations with a numerical grid that is sufficiently refined to represent the discrete nature of the dopant distribution. The average V/sub T/-shift is found to be positive for long, narrow devices, and negative for short, wide devices. The fast 2-D MINIMOS modeling of dopant fluctuations enables an extensive statistical analysis of the intrinsic spreading in a large set of compact model parameters for state-of-the-art CMOS technology. It is predicted that V/sub T/-variations due to dopant fluctuations become unacceptably large in CMOS generations of 0.18 /spl mu/m and beyond when the present scaling scenarios are pursued. Parameter variations can be drastically reduced by using alternative device designs with ground-plane channel profiles.

Electrodeposition of copper was investigated on thin films of poly(3,4-ethylenedioxythiophene) (PEDOT). This conducting polymer can be processed from solution and exhibits a high specific conductivity of about 300 S/cm. N -(3-Trimethoxysilyl-propyl)pyrrole was applied as a primer in order to adhere PEDOT to the substrates. The lateral propagation or front velocity of the copper front and the uniformity of the copper deposit were determined as a function of sheet resistance of the PEDOT films, type of PEDOT counterions, and of the temperature, applied potential and composition of the electrochemical baths. The experimental data obtained are interpreted using a simple mathematical model to describe transient thickening during electrodeposition on electrodes of high ohmic resistance. A good agreement with experimental data is obtained, especially for the front velocity being inversely proportional to the square root of the sheet resistance. Quantitative analysis of uniformity data shows that the affinity for nucleation is much higher on the conducting polymer than on the deposited metal. This conclusion is supported by activation energies as determined from temperature-dependent metallization experiments. Finally, adhesion of copper deposits as a function of copper thickness and morphology of the substrate are discussed.

Today's state-of-the-art SiGe BiCMOS processes show impressive high-frequency performance, with ƒ T and ƒ MAX exceeding 500GHz. However, SiGe can also offer significant performance gain at more moderate application frequencies. In this paper we discuss the optimization of SiGe heterojunction bipolar transistors (HBTs) for very low noise applications in the 2–10GHz range. By careful tuning of the base-profile, minimum noise figures below 0.55dB and 0.35dB are obtained at 10GHz and 2GHz respectively.

The increasing complexity of modern technologies has made semiconductor process and device development challenging. A reduction in the number of experimental tests and a detailed internal insight opens the way to a more optimized process in a shorter time at reduced costs and development time. This has largely increased the use of virtual technology platforms for technology development and circuit optimization in e.g. RF BiCMOS applications. The capability of accurate predictions and directly linking basic technology parameters to RF circuit performance makes virtual technology a very powerful tool during RF process and device development. Commercially available technology computer-aided design (TCAD) tools are generally used during device fabrication and characterization, process optimization, and circuit design. With three examples we illustrate the evolution of the virtual technology process used for RF BiCMOS development within NXP Semiconductors. In the first two examples, we illustrate device and process optimization while in the third example we describe a new way of combining device and process optimization with circuit simulations by means of a distributed equivalent circuit. It allows to take the interaction between the intrinsic device (i.e. device doping profile) and the parasitic environment (i.e. device architecture) efficiently into account for high-frequency applications and in particular for low-noise circuits.

In this work we study improvements of the high-frequency noise performance of HBT devices by means of layout and spacer optimization. Using an equivalent circuit, we identify the dominant noise sources and demonstrate that the reduction of the base-resistance induced thermal noise by means of dotted emitters in combination with lowering the edge contribution of the base-emitter capacitance (e.g. by emitter-base spacer optimization) translates into better noise performance.

A new, compact expression for the effective FinFET gate resistance is derived and validated on experimental data. Moreover, FinFET thermal noise measurements are presented and analyzed. We show that the observed increase of drain current noise with drain-source voltage is not due to microscopic excess noise, but to the access resistances, which modify the transfer of channel thermal noise to the terminals.

The physics-based junction model for CMOS, called JUNCAP2, is described. It contains single-piece formulations for the Shockley-Read-Hall generation/recombination current and the trap-assisted tunneling current which are valid both in forward and reverse mode of operation. Moreover, the trap-assisted tunneling model extends the previous model (Hurkx et al. in IEEE Trans. Electron Devices 39(9), 2090–2098, 1992) to the high electric fields encountered in today’s CMOS technologies. Furthermore, the model contains expressions for junction capacitance, ideal current, band-to-band tunneling current, avalanche breakdown, and junction shot noise. The parameter extraction, experimental verification and a calculationally efficient evaluation procedure (JUNCAP2 Express) are also discussed in this chapter. The JUNCAP2 model is incorporated in the PSP model for bulk MOSFET’s (see Chap. 1 of this book) and in the PSP-SOI model for SOI MOSFET’s (see Chap. 2 of this book).

The first physics-based analytical model is presented that unifies the descriptions of majority and minority carrier mobility and that includes screening of the impurities by charge carriers, electron-hole scattering, clustering of impurities and the full temperature dependence of both majority and minority carrier mobility. Using this model, excellent agreement is obtained with published experimental data on Si. The model is especially suited for device simulation purposes, because the carrier mobility is given as an analytical function of the donor, acceptor, electron and hole concentrations and of the temperature.

A recombination model for device simulation that includes both trap-assisted tunneling (under forward and reverse bias) and band-to-band tunneling (Zener tunneling) is presented. The model is formulated in terms of analytical functions of local variables, which makes it easy to implement in a numerical device simulator. The trap-assisted tunneling effect is described by an expression that for weak electric fields reduces to the conventional Shockley-Read-Hall (SRH) expression for recombination via traps. Compared to the conventional SRH expression, the model has one extra physical parameter, the effective mass m*. For m*=0.25 m/sub 0/ the model correctly describes the experimental observations associated with tunneling. The band-to-band tunneling contribution is found to be important at room temperature for electric fields larger than 7*10/sup 5/ V/cm. For dopant concentrations above 5*10/sup 17/ cm/sup -3/ or, equivalently, for breakdown voltages below approximately 5 V, the reverse characteristics are dominated by band-to-band tunneling. >

In this paper, it is shown that self-heating causes a gigantic effect on the capacitances of MOSFETs/FinFETs. The effect is used to determine the SOI FinFET thermal impedance and to determine the temperature rise during FinFET operation.

We review compact modeling techniques that enable a surface-potential-based approach to modeling MOS transistors. These include symmetric linearization method, an analytical approximation of surface potential and surfacepotential-based extrinsic device model. General techniques are illustrated by application to the PSP model.

This paper presents a general weak nonlinearity model that can be used to model, analyze and describe the distortion behavior of various low noise amplifier topologies in both narrowband and wideband applications. Represented by compact closed-form expressions our model can be easily utilized by both circuit designers and LNA design automation algorithms. Simulations for three LNA topologies at different operating conditions show that the model describes IM components with an error lower than 0.1% and a one order of magnitude faster response time. The model also indicates that for narrowband IM2@w1-w2 all the nonlinear capacitances can be neglected while for narrowband IM3 the nonlinear capacitances at the drainterminal can be neglected.

First the surface-potential-based compact MOS model, PSP, is introduced. After a discussion of the general advantages of this model, it is benchmarked against measurements from the 45 nm technology node. Finally, we zoom in on the modeling in PSP of two effects that are of special importance for RF applications: distortion and noise.

In this paper, a small-signal MOSFET model is described, which takes the local effects of both velocity saturation and transverse mobility reduction into account. The model is based on the PSP model and is valid for both quasi-static and nonquasi-static (NQS) operations. Recently, it has been found that, in the presence of velocity saturation, the low-frequency capacitances cannot be determined from the Ward-Dutton charge-partitioning scheme. By use of the small-signal model developed in this paper, it is demonstrated that, in the presence of velocity saturation, no terminal drain and source charges exist, from which the capacitances can be derived. The small-signal model enables the determination of the correct capacitive behavior in the presence of velocity saturation. Furthermore, it is demonstrated how the small-signal model can be used to determine the number of collocation points needed in the large-signal NQS PSP model. Finally, inclusion of the local variation of mobility reduction due to the vertical electrical fields provides insight into the approach commonly applied in compact modeling, where these fields are replaced by global ones depending on the terminal voltages only.

In this presentation we will focus on the two main sources of noise in CMOS devices which are of interest for RF circuit, design: flicker noise and thermal noise.

Recently, the PSP model was selected as the first surface-potential-based industry standard compact MOSFET model. This work presents the results of several qualitative "benchmark" tests that over the last two years were used to verify the physical behavior of the new model and its usefulness for future generations of CMOS IC design. These include newly developed tests and previously unavailable experimental data stemming from low-power, RF, mixed-signal, and analog applications of MOSFETs.

The physical background of the thermal noise equations of the PSP MOSFET model [1] is presented. The PSP thermal noise model is shown to pass a number of proposed benchmark tests for MOSFET thermal noise. Without any fitting parameters, it is shown to predict with great accuracy a collection of experimental data on three modern CMOS technologies. The impact of device layout on noise properties is discussed and demonstrated experimentally.

We present a new compact model for the junction capacitances and leakage currents in deep-submicron CMOS technologies. The model contains Shockley-Read-Hall generation/recombination, trap-assisted tunneling, band-to-band-tunneling, and avalanche breakdown. It has been validated for a wide range of bias and temperature, for NMOS and PMOS junctions, and for different CMOS generations

The spline-collocation-based non-quasi-static model is extended to include small-geometry effects and to enable both small-signal and large-signal simulations. The new NQS model has been implemented into circuit simulators using both SP and PSP models and verified using RF test data. Additional verification is provided by comparison with the results of numerical simulations and with the MM11 channel segmentation method. The large-signal and small-signal simulation results are compatible and consistent with the quasi-static formulation at low frequencies

We have optimized 3 key RF devices realized in standard logic 90 nm CMOS technology and report a record performance in terms of n-MOS maximum oscillation frequency f/sub max/ (280 GHz), varactor tuning range and varactor and inductor quality factor.

In compact transistor modeling for circuit simulation, the capacitances of conventional MOS devices are commonly determined as the derivatives of terminal charges, which on their turn are obtained from the so-called Ward-Dutton charge partitioning scheme (Ward, 1981). For devices with a laterally non-uniform channel doping profile, however, it is shown in this paper that: 1) no terminal charges exist for the description of capacitances. Instead, 2) a model is presented for the capacitances of such devices, including numerical results for a MOS transistor with a laterally diffused channel doping profile. Finally, 3) a method is given to incorporate such a capacitance model in circuit simulators which are traditionally based on terminal charge models.

Accurate compact modeling of induced gate noise is a prerequisite for RF CMOS circuit design. Existing models underestimate the induced gate noise for short-channel devices. In this paper, a new model is introduced, based on an improved Klaassen-Prins approach, which accurately accounts for velocity saturation. The model accurately describes noise without fitting any additional parameters.

We study the the thermal noise of short-channel NMOS transistors in a commercially available 0.13 micron CMOS technology. The experimental results are modeled with a non-quasi-static RF model, based on the principle of channel segmentation. The model is capable of predicting both drain and gate current noise accurately, without fitting any parmeters to the measured noise data. An essential ingredient of the model is the gate resistance, which is shown to dominate the gate current noise. In our optimized device layouts, this gate resistance is mainly determined by the silicide-to-polysilicon contact resistance.

A large-signal non-quasi-static (NQS) model for RF CMOS circuit simulation is presented that can be built from channel segments described by conventional QS models like BSIM3 or MOS Model 9. This large-signal NQS model is shown to give a very accurate prediction of the high-frequency behaviour of the intrinsic transconductance, the power gain and input resistance.

The base- and emitter resistance are important parameters of bipolar transistors and can be extracted from high frequency small signal admittance (Y) parameters. The circle impedance method and the two port method are examined and improvements are presented.

Measurements on the reverse and nonideal forward currents in heavily doped diodes and in advanced bipolar transistors in the temperature range from 77 K to 300 K are presented. A detailed comparison is made between these measurements and various models. It is shown that models from the literature fail to describe all observed phenomena. A model is proposed which is shown to provide a good description of the measured heavy-doping effects on recombination. The model describes the experimentally observed voltage and temperature dependence of both the nonideal forward and the reverse currents without the introduction of fitting parameters. It is shown that, for zero-bias depletion widths between 300 AA and about 700 AA, trap-assisted tunneling is important for reverse-biased junctions at room temperature. For zero-bias depletion widths less than 300 AA, the tunneling effects increase dramatically. Whereas trap-assisted tunneling has to be taken into account for the forward characteristic, the reverse characteristic is dominated by band-to-band tunneling. >

A novel method for computing the light output on a CRT projection tube is verified and used to predict the performance of different phosphors for different scanning parameters. This model is based on measured phosphor saturation data, and can be used to predict not only the light output but also the modulation depth for a given frequency. It is shown, both experimentally and theoretically, that the use of high scanning frequencies (up to 62.5 kHz) considerably alleviates saturation problems, especially for the blue phosphor (ZnS:Ag), where a gain of more than 2 in light output has been measured. Consequently, a significant improvement in the white-D capability and resolution of CRT based projection systems can be achieved. >

Bipolar transistors with P-implanted polysilicon emitters have been fabricated with high emitter efficiency and low emitter series resistance. Temperature-dependent measurements showed that the base current was limited by thermionic emission over a potential barrier of 220 MeV at the polysilicon-monosilicon interface. Due to this effective barrier, the base current was dominated by recombination in the monosilicon emitter. A model which explains the base current and its dependence on the temperature is presented. The difference between the P-doped and As-doped transistor is attributed to the fact that for the latter the base current is not limited by thermionic emission. >

Analog applications of MOS transistors in integrated circuits impose enhanced requirements on the compact MOS models used in circuit simulators. Here we present for the Philips MOS MODEL 9 the successful confrontation with these analog requirements, the scaling of parameters with geometry, the accuracy of the model over the whole geometry range of a process, its capabilities in the description of various processes at least down to 0.35 /spl mu/m and a comparison with advanced analog models available in commercial circuit simulators. >

The device simulator MINIMOS has been used to quantify the influence of intrinsic dopant fluctuations on the spreading and correlations of a large set of transistor and compact model parameters. It is demonstrated that the contribution of dopant fluctuations to MOS transistor matching can be drastically reduced by novel device designs using ground-plane channel profiles.

A physics-based analytical model is presented that unifies the descriptions of majority and minority carrier mobility and that includes screening of the impurities by charge carriers, electron-hole scattering, clustering of impurities, and the full temperature dependence of both majority and minority carrier mobility. The electron and hole mobilities are given as analytical functions of local variables: ionized donor, ionized acceptor, electron and hole concentrations, and the temperature. The excellent agreement between the proposed model and published experimental data on the carrier mobility in silicon reinforces the model predictions on less investigated aspects of the mobility, e.g. the temperature dependence of the minority carrier mobility, which is distinctly different from that of the majority carrier mobility. >

The geometrical scaling of the intrinsic source/drain series resistance of MOSFETs is investigated using a large selection of transistor geometries in 0.5 /spl mu/m CMOS technology. It is shown both experimentally and theoretically that for narrow-width MOSFETs with dog-bone layouts, the source/drain resistance is no longer inversely proportional to the channel width. A new scaling rule for the source/drain resistance and thus for the mobility reduction parameter /spl theta//sub 1/ of MOS Model 9 leads to a considerably improved modelling accuracy in both the linear and saturation regimes.

This paper illustrates the use of an efficient parameter extraction strategy for MOS Model 9 to perform a statistical analysis of sample devices from a 0.18 /spl mu/m CMOS process. The parameter extraction strategy allows all the parameters for a particular device geometry to be extracted from just 50 measurements. These parameters are subsequently used with principal component analysis to provide best-case or worst-case model sets or as inputs to a Monte-Carlo experiment to investigate some of the performance trade-offs of the process.

This paper addresses the numerical requirements for device modeling of statistical dopant fluctuations in MOS transistors. It is found that the standard deviation of the threshold voltage V/sub T/ can be properly derived from 2D or 3D simulations using a relatively coarse simulation grid. Evaluating the threshold voltage shift arising from dopant fluctuations, on the other hand, calls for a full 3D approach with a numerical grid that is sufficiently refined to represent the discrete nature of the dopant distribution. The average V/sub T/-shift is found to be positive for long, narrow devices, and negative for short, wide devices.

A prototype 0.5 /spl mu/m CMOS LNA with a noise figure of 2.2 dB and a gain of 16.9 dB at 900 MHz at a power consumption of 1.8 mW is reported. This result, and the noise figures obtained on 0.25 /spl mu/m CMOS, are reproduced by simulations, confirming that RF noise modeling can be accurately performed using our public domain MOS Model 9. Simulations are presented for similar LNAs realized in standard CMOS processes with gate dimensions down to 0.13 /spl mu/m. Provided high Q matching circuitry is used, for the latter gate length a noise figure of only 1.1 dB and 27 dB gain at 1800 MHz, at a minimal power consumption of only 0.2 mW, is predicted.

A new methodology for sensitivity analysis at circuit level in terms of process parameters is presented. Response functions for long-channel MOSFETs are found from process and device simulations. Responses for a device with arbitrary dimensions are subsequently calculated using the MOS MODEL 9 scaling rules.

A very fast, robust and accurate parameter extraction method for bipolar compact models has been developed. Using a combination of simplified expressions and selected measurements the iterative solution of the full model equations (e.g. using a circuit simulator) is avoided. The method is applied to the bipolar compact model MEXTRAM.

The distortion behaviour of MOSFETs is important for RF-applications. In this paper the influence of technology variations (oxide thickness, substrate doping,...) on distortion is investigated using measurements and a recently developed compact MOSFET model. The influence on distortion of technology scaling down to 0.18 /spl mu/m is verified and further scaling according to the ITRS-roadmap is predicted.

We have investigated the RF potential of 100nm CMOS technology. A high cut-off frequency of 140 GHz for 80nm (actual gate length) NMOS devices was achieved. Combining on wafer measurements with the compact model MOS model 11, we demonstrate that an fmax of 320GHz is achievable on scaled NMOS devices.