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The main purpose of this paper is to introduce an ultracompact device for electrostatic discharge (ESD) protection based on a bipolar metal oxide silicon (BIMOS) transistor merged with a dual back-to-back silicon-controlled rectifier (SCR) for bulk and for ultrathin body box fully depleted (FD)-silicon on insulator (SOI) advanced CMOS technologies in the hybrid bulk thanks to process co-integration. It is well known that ESD protection is a challenge for IC in advanced CMOS technology. In this paper, an optimized solution is described through the concept, design, 3-D technology computer aided design (TCAD) simulation, and silicon characterization in 28-nm FD-SOI in hybrid bulk. Measurements are done thanks to transmission line pulsed (TLP), very fast TLP and dc behavior. Moreover, the overvoltage is investigated through very fast transient characterization system measurements. It demonstrates a promising candidate to protect against ESD event and to develop new ESD network dedicated to system on chip.

International audience; A band-modulation device with a free top surface, named Z3-FET (Zero front-gate, Zero swing slope and Zero impact ionization) and fabricated in the most advanced Fully Depleted Silicon-On-Insulator technology, is demonstrated experimentally. Since the device has no front gate, the operation mechanism is controlled by two adjacent heavily doped buried ground planes acting as back-gates. Characteristics such as sharp quasi-vertical switching, low leakage, and tunable trigger voltage are measured and discussed. We explore several variants (thin and thick silicon or SiGe body) and show promising results in terms of high current, switching performance and ESD capability with relatively low back-gate and drain bias operation.

International audience; A band-modulation device is demonstrated experimentally in advanced FDSOI (Fully Depleted SOI). The Z2-FET (Zero Impact Ionization and Zero Subthreshold Slope FET) is a very recent sharp switching device which achieves remarkable performance in terms of leakage current and triggering control. The device is fabricated with Ultra-Thin Body and Buried Oxide (UTBB) Silicon-On-Insulator (SOI) technology, features an extremely sharp on-switch, low leakage and an adjustable triggering voltage (VON). The Z2-FET operation relies on the modulation of electrons and holes injection barriers. In this paper, we show, for the first time, experimental data obtained with the most advanced FDSOI node.

The purpose of this paper is to present a new trigger design solution to address a double challenge. The first challenge is to trigger a dual back to back SCR during an ESD event with symmetrical response. And the second one is to obtain a pull-up function for the normal mode of the protection. These targets are reached thanks to BIMOS transistor approach compatible with advanced CMOS technology. Moreover, the silicon area constraint is addressed. The study through 3D TCAD simulation is performed on 40 nm and 32 nm and includes Transmission Line Pulse (TLP) measurements of a demonstrator circuit.

In this article, the impact in FDSOI technology, of ground plane and buried oxide (BOX) size on the robustness and on the NMOS triggering voltage (Vt1) is shown. We show experimentally that firstly thin BOX devices are more robust than thick BOX devices and secondly with a higher Vt1, thin BOX device purposes a larger range to trigger ESD network and to optimize design.

session 9: Advanced Devices ad Three-Dimensional Integration; International audience; A systematic study of a novel band modulation device (Z3-FET: Zero gate, Zero swing slope and Zero impact ionization) fabricated in most advanced Fully Depleted Silicon-On-Insulator technology is presented. Since the device has no front gate, the operation mechanism is controlled by two buried ground planes. Characteristics such as sharp switching, low leakage, and controllable triggering are measured and discussed. We explore several variants (thin and thick silicon film) and show promising results in terms of high current and switching performance.

For the first time, we demonstrate an innovative way to build ESD protection in FDSOI technologies. This protection is comprised of two stacked devices one on the other: a bottom bulk-thyristor and a top thin film triggering device. Low leakage current, tunable triggering voltage and high current capability are highlighted.

The aim of this paper is to introduce a new design of modular bi-directional power switch for 28nm Ultra Thin Body and BOX (UTBB) Full Depleted (FD) SOI advanced CMOS technology and beyond. Moreover, this proposed solution is self-protected against ElectroStatic Discharge (ESD). The first challenge is to obtain a robust symmetrical elementary power device compatible with this technology and with a silicon area optimization. The second one is to provide a new design to trigger this power device. The last challenge is to be efficient in term of ESD robust without additional protection device. These specifications are reached thanks to a Triac (dual back to back SCR) power device in matrix and BIMOS transistors used in a new trigger solution. The study is performed through the 2D-3D TCAD simulation and a test chip is performed in 28nm FDSOI with silicon demonstrator. Measurements are done in DC sweep condition, in high current pulse with 100ms time width. It also includes Transmission Line Pulse (TLP) with 100ns time width to characterize and qualify this design and topology in ESD range time event.

We present an innovative set of UTBB (Ultra-Thin Body and BOX) ESD protection devices, which achieves remarkable performance in terms of leakage current and triggering control. Ultra-low leakage current below 0.1 pA/μm and adjustable triggering (1.1V

The aim of this paper is to present an ESD solution to address several challenges. The first challenge is to obtain a robust ESD protection with symmetrical response under ±1 kV HBM. And the second one is to reach 100 GHz broadband for RF application. These targets are reached thanks to the BIMOS transistor and dual back to back SCR solution, both compatible with advanced CMOS technology. Moreover, the silicon area and leakage constraints are also addressed. The study is performed through the 3D TCAD simulation and RF models on 40 nm and 32 nm. It also includes Transmission Line Pulse (TLP) and S parameters measurements to characterize and qualify this design and topology.

The aim purpose of this study is to evaluate the ESD protection using BIMOS transistor in the RF and fast swing application for advanced CMOS technology in 32 nm high k metal gate & bulk substrate. The ESD target is 1kV HBM and the RF one is 100 GHz broadband. Moreover the DC behavior is also performed. Thus, the challenge here is to be efficient in ESD protection with a minimum of parasitic capacitance. To address these specifications the solution discussed in this paper uses the Bimos transistor characterized through TLP and DC measurements. A RF model is proposed and calibrated thanks to S parameters. Moreover, the R parameter range is investigated to the full 100GHz frequency range.

BIMOS transistor is a useful device and now compliant in advanced CMOS technology. This device acts with high controlled current gain. Thus, it is an efficient candidate for Electrostatic Discharge (ESD) protection. Moreover it is well known that ESD protection for advanced CMOS technologies is a major challenge due to down-scaling which introduces a reduction of the intrinsic robustness. This paper introduces the BIMOS ESD approach with simulations in 45nm. Silicon measurements are performed on 32 nm CMOS high k metal gate.

The robustness against Electrostatic Discharge (ESD) events of gated diodes, fabricated in CMOS 45nm FDSOI technology, is compared for 10nm and 145nm Buried Oxide (BOX) thickness. It is shown that the performance of devices for co-design on thin BOX is improved thanks to a better thermal dissipation: A gain of 1.6 on the robustness was found.

This paper highlights the successful co-integration of Localized Silicon-On-Insulator (LSOI) devices and of bulk-Si I/O devices on the same chip. LSOI devices present good logic performances and very low mismatch values down to 1.2mV/µm. In addition, we show the backbiasing impact on LSOI SRAM bit-cells for stability improvement. This work also presents the co-integration of LSOI with bulk devices as a solution for the devices that are not compatible with thin-body technology. In particular, we demonstrate for the first time competitive bulk co-integrated ElectroStatic Discharge (ESD) protections.