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Fin height and width dependence of negative and positive Bias Temperature Instability (N/PBTI) on logic for memory high- $\kappa $ metal gate (HKMG) FinFET transistors is reported for the first time. It was observed that NBTI degradation is less severe when increasing the physical height of the silicon fin. The increased fin height results in a lower effective defect density, believed to be related to a reduced role of the defective fin corners and/or top surface. In addition, activation energies for the capture process in tall fins during NBTI stress show lower values while charge trapping in standard height fins is highly temperature dependent. PBTI results reveal a similar, albeit less severe, impact of fin height, suggesting an impact of fin height on the high- $\kappa $ layer, with again an increased defectivity at the fin corners and/or top surface, whose effective role is reduced in the case of taller fin. On the other hand, PBTI shows limited temperature dependence, independent of fin height.

Continued scaling of DRAM technologies has required a limitation of the power dissipation from the logic components on-chip, while downscaling both transistor oxide thickness and gate length. One route to enable further scaling, while circumventing excessive leakage currents, is the integration of high-permittivity ( ${\kappa }$ ) metal-gate (HKMG) components into the logic and high-voltage (e.g., I/O) devices. The requirement of a gate-first flow for devices in the peripheral region introduces significant reliability challenges. Even though Negative Bias Temperature Instability (NBTI) performance of CMOS and memory thermal budget compatible transistors are aligned with conventional HKMG integration with thin oxide devices, it is not the case for thick oxide devices. In particular, it will be shown that strong NBTI lifetime degradation is observed as soon as high- ${\kappa }$ layers are deposited on top of the thick interfacial layer. In this work, a review of the impact of these high- ${\kappa }$ layers on the NBTI high voltage logic for memory devices is presented. The stress induced degradation is correlated to a diffusion of metal atoms from the HKMG gate stack towards the silicon surface. Directions for reliability improvements are then defined. The presence of Nitrogen throughout the HKMG stack can originate either from high- ${\kappa }$ processing or metal-nitride gate electrode. It is shown that preventing nitrogen diffusion towards the Si/SiO2 interface region, together with AlOx and/or F incorporation at the HKMG interface, can tune device threshold voltage and modulate access to donor trap-defect bands. The result of these effects is a vast improvement in NBTI performance. A detailed study of NBTI-degradation, supported by physical analysis, assessing the impact of various tuning components within the stack (interface layer, high- $\kappa $ fluorination and/or cap, metal gate) will be presented. Potential solutions for this reliability challenge will be reported.

The effect of the geometric parameters of Fin field-effect transistors (FinFETs) on hot-carrier degradation (HCD) in these devices is theoretically studied. To this end, a model is used, in which three subproblems constituting the physical phenomenon of HCD are considered: carrier transport in semiconductor structures, description of microscopic defect formation mechanisms, and simulation of degraded device characteristics. An analysis is performed by varying the gate length, fin width and height. It is shown that HCD becomes stronger under fixed stress conditions in transistors with shorter channels or wider fins, while the channel height does not substantially affect HCD. This information can be important for optimizing the architecture of transistors with the fin-shaped channel to suppress degradation effects.

integration requires development of low thermal budget process modules. High-quality SiO 2 interfacial layer (IL), obtained up to now only by high-temperature (≥850°C) oxidation or exposure, is crucial for pMOS NBTI reliability. In unannealed IL’s grown at reduced temperatures, we show that unrelaxed interface strain induces high defect densities, with physics-based NBTI modeling suggesting excessive hydroxyl-E’ defect formation due to Si-O bond stretch. Based on ab-initio theoretical insights, we demonstrate an atomic hydrogen treatment to passivate SiO 2 defects at low temperatures (100-300°C), which is shown to be vastly more effective than high pressure molecular hydrogen exposure, and to yield an SiO 2 quality and reliability surpassing a 900°C oxide.

In this work, low frequency noise spectroscopy is performed on n-channel gate all around (GAA) nanowire (NW) FETs. The study of generation-recombination noise at fixed temperature as a function of the applied bias suggests the existence of traps located in the depleted Si film. The temperature evolution of the generation-recombination noise at fixed polarization allows constructing an Arrhenius diagram from which a hydrogen related trap was identified. Moreover, it is suggested that it is more suitable to use the surface trap density as a figure of merit.

We develop and validate a physics-based modeling framework for coupled hot-carrier degradation (HCD) and self-heating (SH). Within this framework, we obtain the lattice temperature distribution throughout the device by solving the lattice heat flow equation coupled with the drift-diffusion approach. Then, the evaluated temperature spatial profile in the transistor is taken into account while solving the Boltzmann transport equation for carriers to obtain the carrier energy distribution functions, which are needed to compute the rates of the single-and multiple-carrier mechanisms of bond dissociation. The effect of SH on HCD is threefold: ( $i$ ) it results in a significant distortion of the carrier distribution function, (ii) device heating decreases vibrational lifetime of the Si-R bond, thereby suppressing the multiple-carrier mechanism, and (iii) the rate of thermal bond-breakage becomes higher due to SH. The model is capable of accurately reproducing relative changes in the saturation drain current with stress time measured in p-channel nanowire field-effect transistors subjected to HCD under different stress conditions. We show that neglecting SH leads to substantial underestimation of HCD.

The electrical performance and reliability of MOSFETs and charge-trap flash memories are influenced by the traps in the gate dielectric. Trap properties depend on the atomic structure of the dielectric and are thus expected to be affected by mechanical stress, which modifies the bonds between atoms. Consequently, the mechanical stress, either engineered or created as a side effect of fabrication, needs to be considered in order to improve the device performance and reliability. This work demonstrates a systematic and controlled experimental study of the trapping process in individual gate oxide defects under externally applied mechanical stress. The significant and reversible impact of the mechanical stress on the trapping behavior is demonstrated and a theory to explain the observations is proposed.

GaN-channel based transistors are ideally suited for RF/5G applications and also provide the promise of monolithic integration on a conventional Si-platform. Due to the wide scope of high electron mobility GaN transistor architectures, their reliability assessment is essential to ensure their successful deployment in low-power applications such as mobile computing devices, as well as high-power applications such as autonomous vehicles and base stations. We identify the most important DCreliability metrics necessary for fair benchmarking of future GaNon-Si RF transistors. A detailed analysis of the shortlisted DCreliability parameters for three device types, namely MOSFETs, MOSHEMTs/MISHEMTs and HEMTs is presented. MOSHEMT/MISHEMT is identified as the most robust device architecture, due to the presence of a barrier layer alleviating the impact of certain degradation mechanisms. Defect distributions in the gate-stack of MOS devices are extracted using defect band modelling technique. MOSHEMT devices are shown to undergo negative and positive Bias Temperature Instability (BTI) under specific ranges of positive gate-overdrive, thereby demonstrating the importance of correctly estimating the oxide field for MOSHEMT devices. Degradation map methodology is partially developed to distinguish the different gate-oxide degradation mechanisms and model the device lifetime pertaining to each of the mechanisms.

A common approach to incorporate workload dependent aging in circuits is to use an effective stress time or so-called signal probability (SP) to calculate degradation under realistic workload scenarios. However, this approach is not fully physics-based and incurs erroneous estimation of degradation. Moreover, cycle-accurate (CA) simulations are computationally expensive. In this paper, a relatively fast yet accurate, adaptive waveform splitting (AWS) algorithm is proposed to enable fast calculation of workload-dependent device aging. The proposed algorithm has been adopted to perform aging estimation of large circuits under specific workload scenarios.

For the first time, hot-carrier degradation (HCD) is simulated in non-planar field-effect transistors with a fin-shaped channel (FinFETs). For this purpose, a physical model considering single-carrier and multiple-carrier silicon–hydrogen bond breaking processes and their superpositions is used. To calculate the bond-dissociation rate, carrier energy distribution functions are used, which are determined by solving the Boltzmann transport equation. A HCD analysis shows that degradation is localized in the channel region adjacent to the transistor drain in the top channel-wall region. Good agreement between the experimental and calculated degradation characteristics is achieved with the same model parameters which were used for HCD reproduction in planar short-channel transistors and high-power semiconductor devices.

Filamentary resistive RAM devices have been developed as a possible alternative memory device. In previous work, the device operation has been described using the hourglass model. In the present paper, a simple but quantitative retention model for OxRRAM devices is developed in the framework of the hourglass model. This is achieved by added a one-dimensional diffusion process in the top reservoir of the filament. The model describes the mean retention drift well using an activation energy that is identical to the activation energy for modeling set and reset in these devices, demonstrating that retention from the low resistance state is nothing but a spontaneous temperature-driven narrowing of the constriction. Display Omitted A model describing retention in filamentary vacancy-based RRAM is presented.The model is quantitative and predictive.The activation energy equals the switching activation energy.The mean as well as the distribution are modeled.The model is calibrated with HfO-samples.

Continued scaling of DRAM technologies has required a limitation of the power dissipation from the logic components on-chip, while downscaling both transistor oxide thickness and gate length. One route to enable further scaling, while circumventing excessive leakage currents, is the integration of high-κ metal-gate (HKMG) components into the logic and high-voltage (e. g. I/O) devices. The requirement of a gate-first flow for devices in the peripheral region introduces significant reliability challenges. Even though Negative Bias Temperature Instability (NBTI) performance of CMOS and memory thermal budget compatible transistors are aligned with conventional HKMG integration with thin oxide devices, it is not the case for thick oxide devices. In particular, it will be shown that strong NBTI lifetime degradation is observed as soon as high-κ layers are deposited on top of the thick interfacial layer. In this work, a review of the impact of these high-κ layers on the Negative Bias Temperature Instability (NBTI) of high voltage logic for memory devices is presented. The stress induced degradation is correlated to a diffusion of metal atoms from the HKMG gate stack towards the silicon surface. Directions for reliability improvements are then defined. The presence of Nitrogen throughout the HKMG stack can originate either from high-κ processing or metal-nitride gate electrode. It is shown that preventing nitrogen diffusion towards the Si/SiO 2 interface region, together with AlOx and/or F incorporation at the HKMG interface, can tune device threshold voltage and modulate access to donor trap-defect bands. The result of these effects is a vast improvement in NBTI performance. A detailed study of NBTI-degradation, supported by physical analysis, assessing the impact of various tuning components within the stack (interface layer, high-κ fluorination and/or cap, metal gate) will be presented. Potential solutions for this reliability challenge will be reported.

3D NAND, the mainstream technology for high density Flash application [1], is typically based on the charge trapping paradigm, i.e. it relies on the storage of information as electrons trapped in a charge trapping layer (CTL). The useful life of these devices is limited by the number of program and erase (P/E) operations, because repeated tunneling of electrons and holes progressively creates defects in the tunneling dielectric (TuOx) that increase the charge leakage from the CTL, compromising retention. In this paper we propose a model that describes the creation of traps in TuOx according to the degradation dynamics within each pulse of a P/E cycle, unlike previous models that describe the creation of traps only as a function of the number of P/E cycles [2]. This enables a precise calculation of created traps in TuOx based on arbitrary stress pulses and workloads.

Fin height dependence of negative and positive Bias Temperature Instability (N/PBTI) on logic for memory high-κ metal gate (HKMG) FinFETs transistors is reported for the first time. It was observed that NBTI degradation is less severe when increasing the physical height of the silicon fin. The increased fin height results in a lower effective defect density, believed to be related to a reduced role of the defective fin corners and/or top surface. PBTI results reveal a similar, albeit less severe, impact of fin height, suggesting an impact of fin height on the high-κ layer, with again an increased defectivity at the fin corners and/or top surface, whose effective role is reduced in the case of taller fin.

IEEE We investigate BTI charge trapping trends in high-k metal gate (HKMG) stacks with a variety of work function metals. Most BTI models suggest charge trapping in oxide defects is modulated by the applied oxide electric field, which controls the energy barrier for the capture process, irrespective of the gate work function. However, experimental data on capacitors show enhanced or reduced charge trapping at constant oxide electric field for different work function metal stacks. We ascribe this to a different chemical interaction of the metals with the dielectric, which yields different defect profiles depending on the process thermal budget, and not to the gate work function per se. This observation is confirmed by comparing BTI degradation in nMOS and pMOS Replacement Gate planar transistors with three selected work function metal stacks (representative of high-, standard, and low-Vth device flavors), and two different process thermal budgets. Furthermore, by employing the imec/T.U. Wien physics-based BTI simulation framework “Comphy”, we also show that, on top of the unavoidable chemical interaction of different metals with the underlying SiO2/HfO2 dielectric stack, different gate work functions within a typical range of relevance (4.35-4.75eV) can yield a different charge state of the deep high-k defects, and can therefore have an impact on charge trapping kinetics during BTI stress, particularly in nMOSFETs. ispartof: IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY vol:19 issue:2 pages:268-274 ispartof: location:CA, Tahoe status: published

The way a person walks, i.e. his/her gait, can be as unique as a fingerprint. With portable accelerometers and/or gyroscopes available in present-day smartphones, gait verification and identification can be exploited for low-level security [1]. Achieving this requires machine learning of a time sequence.

© 2019 Author(s). 1.8-MeV proton irradiation to a fluence of 10 14 /cm 2 does not significantly affect the resistance or low-frequency noise of copper or ruthenium resistors fabricated via modern microelectronic fabrication techniques used to form metal lines. The room-temperature noise of these Cu and Ru resistors is surprisingly similar to that of Cu and Pt metal lines and wires fabricated using late-1970s nanofabrication techniques; however, measurements of the temperature dependence of the noise show that the defect kinetics are quite different among the various materials. A large increase in the noise magnitude observed above 200 K in Cu but not in Ru is consistent with the superior resistance to electromigration that Ru lines have shown, relative to Cu. ispartof: Applied Physics Letters vol:114 issue:20 status: published

We present the first physics-based approach to modeling the effect of random dopants on hot-carrier degradation (HCD) in FinFETs, which is based on a statistical analysis of HCD performed over an ensemble of 200 transistors with different random dopant configurations. As a reference, the results obtained with the deterministic version of our HCD model are used. The statistical analysis shows that degradation traces and device lifetimes have quite broad distributions and that the deterministic model tends to overestimate HCD and makes pessimistic predictions on device lifetime. Moreover, lifetime distributions evaluated for high stress voltages and for biases close to the operating regimes have different shapes which makes backward lifetime extrapolation challenging, thereby demonstrating that full physics-based HCD treatment is of crucial importance.

The mechanism of imprint in FE-HfO 2 is investigated in detail. It is clearly shown that the imprint can be recovered by additional pulses and domain switching is indispensable for the recovery. The results from sub-loop measurement suggest that the imprint of each domain can be considered to be independent. Switching time measurements reveal that the imprint is well described by the nucleation limited switching kinetic model. In addition, a clear correlation between imprint and gate leakage current is successfully demonstrated. Based on these results, a model for imprint is proposed.

Low thermal budget gate stacks will be required for novel integration schemes, such as 3D sequential stacking of CMOS tiers. We study the impact of a reduced thermal budget on BTI reliability, and we demonstrate interface dipole engineering to suppress the carrier-defect interaction and achieve sufficient nMOS PBTI and pMOS NBTI reliability without the customary post-deposition anneals.

Degradation mechanisms, such as Bias Temperature Instabilities (BTI) and Hot Carrier Degradation (HCD), as well as the associated time-dependent variability, dictate the limit on the acceptable operating voltage conditions in modern deeply-scaled VLSI devices. Based on large statistical datasets, acquired using specifically designed on-chip arrays, we experimentally obtain DC degradation maps for both $\boldsymbol{n}$ - and $\boldsymbol{p}$ -type FETs. Defect-centric based analysis of the statistical parameters at every $\boldsymbol{V_{G}}, \boldsymbol{V_{D}}$ bias point provides physical insights in the underlying single- and multi-carrier degradation processes. As a result, we can separate the defect charging contributions of each degradation mechanism and describe to which extent these mechanisms co-interact. We finally present a simplified model (the “3-bucket” model) that is able to describe the degradation statistics up to $3\boldsymbol{\sigma}$ of a device population subject to an arbitrary combination of BTI and HCD stress.

Voltage transient overshoot is an essential device characteristic of ESD protection diodes under CDM-like stress. Using 3D TCAD and vfTLP characterization, the impact of device architecture and middle-of-line contact scheme on voltage transient overshoot characteristics can be further explored in next bulk FinFET and GAA technology nodes.

Potential solutions for the reliability challenges of high- k metal gate (HKMG) integration into DRAM high-voltage peripheral logic devices are reported. A detailed study of Negative Bias Temperature Instability (NBTI)-degradation, supported by physical analysis, assessing the impact of various tuning components within the stack (interface layer, high-k fluorination and/or cap, metal gate) is presented. The presence of Nitrogen throughout the HKMG stack can originate either from high-k processing or metal-nitride gate electrode. It is shown that preventing nitrogen diffusion towards the Si/SiO 2 interface region, together with AIO x (and F) incorporation at the HKMG interface, can tune device threshold voltage and modulate access to donor trap-defect bands. The result of these effects is a vast improvement in NBTI performance.

Low thermal budget gate stacks will be required for novel integration schemes, such as 3D sequential stacking of CMOS tiers. We study the impact of a reduced thermal budget on BTI reliability, and we demonstrate two strategies to tolerate the inherently large high-k defect densities: i) replacing inversion mode devices with highly doped junction-less transistors, or ii) engineering dipoles at the interface between SiO 2 and HfO 2 to suppress the carrier-defect interaction. The latter approach is demonstrated for nMOS PBTI and, for the first time here, also for pMOS NBTI, as even this aging mechanism is controlled by high-k defects in ultra-thin EOT low thermal budget gate stacks.

At breakdown conditions, large current flows in STT-MRAM devices. We experimentally show that this large current causes significant self-heating of 200-300°C, which impacts the reliability extrapolation to operating conditions. By measuring and analyzing breakdown at various temperatures and on different MgO thickness, we successfully incorporate self-heating into the breakdown model. We find that the 10 year lifetime is underestimated by a factor 103 at 63-percentile, to even 107 when applying percentile scaling to 1 ppm.

We study the impact of HPAP on SCC 3D NAND devices. We show that the process can reduce trap density but is leaving trap impact on devices V T unaffected. It is also shown, both by simulations and measurements, that further scaling could lead to the increase of single trap impact. Finally, we measure that despite largely improving devices electrical parameter, HPAP has no effect on memory performances (Program/Erase) or could slightly degrade it (Retention).

We present a review of our recent studies of Bias Temperature Instability (BTI) in Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) fabricated with different material systems, highlighting the reliability opportunities and challenges of each novel device family. We discuss first the intrinsic reliability improvement offered by SiGe and Ge p-channel technologies, if a Si cap is used to passivate the channel, in order to fabricate a standard SiO2/HfO2 gate stack. We focus on SiGe gate stack optimizations for maximum BTI reliability, and on a simple physics-based model able to reproduce the experimental trends. This model framework is then used to understand the suboptimal BTI reliability and excessive time-dependent variability induced by oxide defect charging in different high-mobility channel gate stacks, such as Ge/GeOx/high-k and InGaAs/high-k. Finally we discuss how to pursue a reduction of charge trapping in alternative material systems in order to boost the device reliability and minimize time-dependent variability.

In modern VLSI devices, a multitude of degradation mechanisms dictates limits on the tolerable voltage conditions to guarantee reliable operation for extended times. The most critical degradation mechanisms such as Bias Temperature Instabilities (BTI) and Hot Carrier Degradation (HCD) are mostly studied in terms of their mean degradation. By obtaining large statistical datasets, covering a multitude of conditions in the {V G ,V D } bias space, typically obtained by measurements on dedicated on-chip FET arrays, we show that we can identify the active degradation mechanisms and understand their impact on both FET time-zero metrics, as well as on the time-dependent variability.

We investigate BTI charge trapping trends in high-k metal gate (HKMG) stacks with a variety of work function metals. Most BTI models suggest charge trapping in oxide defects is modulated by the applied oxide electric field, which controls the energy barrier for the capture process, irrespective of the metal work function. However, experimental data show enhanced or reduced charge trapping at constant oxide electric field for different work function metal stacks. We ascribe this to a different chemical interaction of the metal stack with the dielectric, yielding different defect profiles depending on the process thermal budget. Furthermore, by employing the imec/T.U. Wien physics-based BTI simulation framework “Comphy”, we also show that different metal work functions within a typical range of relevance (4.35-4.75eV) can yield a different charge state of the deep high-k defects, and can therefore have an impact on charge trapping kinetics during BTI stress, particularly in nMOSFETs.

This work presents Si/SiGe superlattice finFETs (FF) for 1.8V/2.5V I/O applications in vertically-stacked Gate-All-Around horizontal nanowire technology (hNW) technology. Superlattice FF have a higher ION than I/O hNW reference devices and can be more easily integrated into a GAA hNW technology than Si I/O FF. These novel I/O FET structures exhibit competitive analog performance and are superior as ESD protection devices.

Charge trapping in the gate-oxide can cause significant degradation and reduce the operating lifetime of the device. Here, we study the kinetics of charge trapping in the InGaAs/Al 2 O 3 /HfO 2 gate-stack using Capture and Emission Time (CET) maps. The existence of two oxide defect bands, respectively above and below the conduction band of InGaAs, is implied by sensing charge trapping at positive and negative oxide electric fields. Within each band, two distinct populations of defect states are observed. The first defect population with relatively higher capture and emission energy barriers is found to affect the long term reliability of the device since the charge trapping in these defect states is slow, while the second population with relatively smaller capture and emission energy barriers affects the device stability particularly under high frequency operation. We argue that it is essential to characterize and study both defect populations in order to accurately estimate device lifetime under different operating applications.

In this work, we detail a novel methodology to extract the magnetisation switching and MgO breakdown characteristics of STT-MRAM devices, from a single d.c. ramped voltage stress (RVS) measurement. This is performed by a two-step process, initially by a robust outlier screening procedure on a piecewise fit to the measured data. Subsequently, these fit results are subjected to k-means cluster analysis to elucidate the magnetisation states present, together with the voltages at which these states change, or breakdown occurs. We validate this methodology by successfully correlating our RVS results with the more widely reported pulsed-breakdown results. An application of this technique examines the impact of scaling MgO tunnel layer thickness. We demonstrate how both the switching and breakdown voltage values reduce with scaling down the MgO tunnel-layer thickness for ultra-thin MgO layers. The switching voltage reduction is more significant than the breakdown voltage reduction, which results in a gain in reliable operation margin on reducing MgO thickness.

Time-dependent variability of modern VLSI devices, due to their associated degradation mechanisms, such as Bias Temperature Instabilities (BTI) and Hot Carrier Degradation (HCD), dictates a limit on the tolerable operating voltage conditions of the device. Based on a large statistical dataset, obtained by measurements on dedicated on-chip FET arrays, we propose a methodology to identify and de-convolute the active degradation mechanisms and subsequently calculate the respective lifetimes in bias {Vg, Vd} space. Utilizing a limited set of parameters for each of the identified failure mechanisms, we show excellent agreement with experimental degradation data over the entire measurable bias space. Finally, by experimental assessment of thermal resistance and degradation activation energies, we can project a self-heating-aware FET lifetime at operating conditions across the entire bias space.

We study hot carrier degradation in Si 0 . 75 Ge 0 . 25 p-FinFETs by measuring degradation maps in the entire bias space and compare with Si counterparts. Hot carrier effects are found to be exacerbated in SiGe due to the reduced impact ionization threshold in small bandgap semiconductors, the larger hole mean free path, and the consequently enhanced generation of secondary electrons. Both hole and electron injections are observed and they partially compensate each other at some stress biases. Even at operating voltages of relevance for core logic applications, off-state stress causes an increased channel off-state leakage due to hot-electron-induced punch-through.

© 1963-2012 IEEE. Total ionizing dose effects are investigated on a physically unclonable function (PUF) based on CMOS breakdown. Devices irradiated to 2 Mrad(SiO2) show less than 11% change in current ratio at 1.2 V. The read-out window of programmed PUFs decreases significantly at high-dose proton irradiation, and then recovers back to the original value after annealing. The proton test results for the pFET selector, the unbroken nFET, and the broken nFET indicate that the threshold-voltage shift of the pFET selector contributes mainly to the degradation of the PUF. ispartof: IEEE Transactions on Nuclear Science vol:65 issue:8 pages:1519-1524 ispartof: location:SWITZERLAND, Geneva status: Published online

We review our recent studies of oxide traps in InGaAs MOS gate stacks for novel high-mobility n-channel MOSFETs. We discuss and correlate various trap characterization techniques such as Bias Temperature Instability, defect Capture-Emission-Time maps (applied here to InGaAs devices), Random Telegraph Noise, hysteresis traces, multi-frequency C-V dispersion, all performed on a variety of device test vehicles (capacitors, planar MOSFETs, finFETs, nanowires). Finally we demonstrate guidelines for developing sufficiently reliable IIIV gate stacks.

We perform a comprehensive analysis of hot-carrier degradation (HCD) in FinFETs. To accomplish this goal we employ our physics-based HCD model and validate it against experimental data acquired in n-FinFETs with a channel length of 28 nm. We use this verified model to study the distribution of the trap density across the fin/stack interface. The methodology is applied to analyze the effect of transistor architectural parameters, namely fin length, width, and height, on HCD. Our results show that at the same conditions HCD becomes more severe in shorter devices and in transistors with wider fins, while the impact of the fin height on the damage is weak. Finally we demonstrate that a proper HCD description can be achieved only with a physics-based model.

In this paper, Epi-Si process is used to investigate the impact of traps and grain boundaries in vertical 3D NAND. With this channel morphology, we show that the defects have a reduced impact on device performances compared to the usual poly-Si channel devices. These results are also confirmed and extrapolated to other geometry using 3D TCAD simulations.

Beyond dimensional scaling, new process options in CMOS roadmap often result in degradation of ESD device performance. Using 3D TCAD and ESD characterization, the impacts of device architecture, middle-of-line contact scheme, and S/D epitaxy process options are explored on ESD diode performance in next generation bulk FF and GAA technologies.

A method for on-chip extraction of random telegraph noise (RTN) parameters from transistors is proposed. Exploiting the nature of exponential distributed RTN events, the proposed circuit enables the automatic extraction of mean RTN time constants from a large array of small-area transistors. The on-chip data processing provides a simplified measurement infrastructure, reduces the measurement time by parallelization and increased efficiency, reduces the data post-processing effort and extends the measurement frequency band. The methodology is demonstrated in a prototype chip fabricated in a 28nm High-k Metal Gate (HK/MG) CMOS technology. The 1.17 mm2 chip includes two arrays of 18,144 transistors each, analog circuitry for sensing and digitizing the RTN signals and a digital signal processing block. The experimental results agree with expectations. ispartof: pages:T132-T133 ispartof: 2017 SYMPOSIUM ON VLSI TECHNOLOGY pages:T132-T133 ispartof: Symposium on VLSI Technology location:Kyoto, Japan date:5 Jun - 8 Jun 2017 status: published

In this paper, we demonstrate for the first time an implant free In 0.53 Ga 0.47 As n-MOSFET that meets the reliability target for advanced technology nodes with a max operating V ov of 0.6 V. In addition, an excellent electron mobility (μ eff, peak =3531 cm2/V-s), low SS lin =71 mV/dec and an EOT of 1.15 nm were obtained. We also report the scaling potential of this stack to 1nm EOT without loss of performance, reliability and further reduction of the sub-threshold swing (SS lin =68mV/dec). On top of the novel IL we presented last year, in this paper we insert a LaSiO x layer between the IL and HfO 2 offering an increased chemical stability of the gate stack. This combination is key and offers both an improved interface quality as well as a reduction of the oxide trap density.

Time-dependent variability of junctionless gate-all-around nanowire pFETs is studied through measurements and simulations. The variability, related to effects such as Random Telegraph Noise (RTN) and Bias Temperature Instability (BTI), is discussed in terms of the distribution of individual charged gate oxide trap threshold voltage shifts. This distribution is shown to be shaped by i) the electrostatics of the device, and ii) percolative source-drain conduction. It is concluded that the time dependent variability of our JL GAA NW pFETs is comparable to previously measured pFinFETs. However, provided that other sources of variability are suppressed, JL FETs time-zero and time-dependent variability may remain high due to the high body doping.