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This paper presents approximate techniques for building models and simulating the response of power distribution systems for high-performance microprocessors. Several distributed equivalent SPICE circuit models were built by extracting the appropriate resistance, inductance, capacitance (RLC) component values using a combination of two-dimensional (2-D) and three-dimensional (3-D) quasi-static field solvers. They were used to assess how well such effects as system transfer impedance and transient characteristics can be predicted. The models include the chip, its controlled collapsed chip connection (C4) connections to the package, the power distribution structure in the package, connector and motherboard. It is found that the response of the entire power system can be treated as a second order system, by which the main features of the performance of the power delivery network are assessed. Samples of transient and frequency domain data for typical microprocessors are given and the effects of some design options are discussed, as are the tradeoffs in model complexity versus the gain of useful design information.

This paper describes the electrical design and evaluation of the Josephson cross‐sectional model (CSM) experiment. The experiment served as a test vehicle to verify the operation at liquid‐helium temperatures of Josephson circuits integrated in a package environment suitable for high‐performance digital applications. The CSM consisted of four circuit chips assembled on two cards in a three‐dimensional card‐on‐board package. The chips (package) were fabricated in a 2.5‐μm (5‐μm) minimum linewidth Pb‐alloy technology. A hierarchy of solder and pluggable connectors was used to attach the parts together and to provide electrical interconnections between parts. A data path which simulated a jump control sequence and a cache access in each machine cycle was successfully operated with cycle times down to 3.7 ns. The CSM incorporated the key components of the logic, power, and package of a prototype Josephson signal processor and demonstrated the feasibility of making such a processor with a sub‐4‐ns cycle time.

This letter describes the first system level test vehicle in Josephson technology. The experiment consists of four circuit chips assembled on two cards in a high density, 3-dimensional, card-on-board package. A data path, which is representative of a critical path of a future prototype processor, was successfully operated with a minimum cycle time of 3.7ns. The path simulates a jump control sequence and a cache access in each machine cycle. This experiment incorporates the essential components of the logic, power and package portions of a Josephson technology prototype.

We have measured the electrical characteristics of chip-to-chip-carrier connectors ideally suited to high-performance Josephson LSI circuits. Self- and mutual inductances between connectors were measured by incorporating the connectors in a dc SQUID (Superconducting Quantum Interference Device) and confirmed by detailed signal delay and crosstalk measurements made with Josephson logic circuits.

A controlled thermal process has been developed for the production of niobium oxide switchable resistors (NOSR), that are suitable for a medium speed, random access, read-write memory application. In particular, the voltage necessary to form the NOSR from the as-fabricated state to the bistable switchable resistor state has been reduced to approximately 2V at 1 mA. The thermal process increases the oxygen vacancy level in the niobium oxide, thereby lowering the bulk resistivity. The applied voltage now primarily appears across the niobium oxide-counterelectrode barrier, and as a consequence a lower external voltage is necessary to produce the same field in this vicinity. The presence of Sb or Bi on the oxide during the heat treatment lowers the subsequent current necessary for forming.

The preparation of amorphous alloys of Mg-Bi by vapour quenching of the constituent elements is described. The electrical conductivity and thermoelectric power of the alloys as a function of temperature and composition are discussed, particular attention being given to the behaviour near the intermetallic compound (Mg3Bi2) composition. Here the properties are found to be in agreement with a model of localized electron states, with the electrons moving by thermally activated hopping.

This paper reviews some recent measuremtns on high‐performance Josephson latching logic, and discusses a compatible ac power scheme which provides good voltage regulation and low clock skew performance for a large computing machine.

An experimental static shift register element using Josephson devices has been designed and fabricated using a one mil minimum linewidth technology. An experimental eight-bit shift register operated with all data patterns at a maximum shift rate of 160 MHz. At 200 MHz, which was the maximum frequency capability of our instrumentation, only limited data patterns could be executed correctly. This problem was found to be associated with the internal power distribution scheme adopted for the design, together with the non-ideal external pulse waveforms. The average power dissipation was only 20µ watt per bit. Computer simulations indicate that the present design with an improved powering scheme is capable of operating at a shift rate of 360 MHz.

This article describes a new method of performing analogue division and its applicability in generating the general function V = (a1V1 + a2V2)m/k/ (b1V1 + b2V2)n/k subject to the condition 0 less-than-or-eq, slant V less-than-or-eq, slant 1. In particular a form of the circuit giving V1(V1 + V2) is described.

This note describes a portable device designed to transfer specimens from a high vacuum evaporator to an AEI EM6G electron microscope in a vacuum better than 01 mtorr at liquid nitrogen temperature. Methods are described for the reduction of the contamination of the specimen by ice in the electron microscope.