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AMD's first Fusion Accelerated Processor Unit (APU) codenamed “Zacate” (Fig. 15.4.1) combines a pair of x86 CPUs cores codenamed “Bobcat”, 1MB L2 Cache, Client Northbridge (CNB), with a DirectX® 11 Radeon™ HD5000 graphics/multimedia controller on a single die. The CNB provides an interface to a single 64b DDR3 memory channel, which can operate at up to DDR3–1066. The Fusion architecture implements an efficient form of unified memory architecture (UMA) where a portion of system memory is reserved as graphics frame buffer memory. The graphics memory controller (GMC) arbitrates between graphics, video and display memory accesses and presents a well-ordered stream of system memory requests through the CNB over dedicated 256b wide read and write busses. These GMC requests bypass all of the CNB coherency mechanisms allowing for fast direct access to memory and exposing most of the available memory bandwidth (8.53GB/s). Compared to two chip solutions, use of the on-die integrated GPU significantly reduces memory latency, improves request ordering, and reduces power. The APU supports display formats including VGA, LVDS, Display Port, DVI or HDMI™. A ×4 Gen2 PCIe® Unified Media Interface (UMI) to an external Fusion Controller Hub (FCH) is supported for system I/O. An additional 4× PCIe Gen2 link supports I/O to external Discrete Graphics chip. more...

Design equations and experimental results for a second-order delta-sigma (/spl Sigma/-/spl Delta/) based infinite impulse response (IIR) filter are presented. Although input and output signals are analog, filtering is performed directly on an oversampled /spl Delta/-/spl Sigma/ modulated signal, thus eliminating the need for any decimation or interpolation filters. Circuit complexity consists of only a single /spl Delta/-/spl Sigma/ analog-digital (A/D) modulator, approximately ten 26-b adders, a 1-b digital-analog converter (D/A) and a low-pass filter. It is shown experimentally that such a filtering technique can realize filter pole-Q's of at least 2600 in the audio frequency range. > more...