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The offset cube, a new 3D network topology, is particularly suited to a through-wafer optoelectronic implementation. This topology is significant because all network links can be implemented with vertical, through-wafer optical connections, with no chip-to-chip wires being required for data transmission. Fully adaptive routing on the offset cube can be undertaken using only two virtual channels per network link. It appears that this fully adaptive protocol can be implemented effectively in hardware.

Advances in VLSI and optoelectronic multichip module technologies are enabling the construction of ultracompact massively parallel processing systems. The technological parameters that define the wirability and delay characteristics of these technologies have a significant impact on the system architecture. An analytical model is presented that allows the design space exploration of the interconnection networks associated with multinode chips packaged on a single multichip module substrate. Possible system designs are evaluated for a two-level interconnect with separate k-ary n-cube networks for interchip and intrachip communication. The impact of several architectural and technological parameters on the optimal network implementation (based on average no-load latency) is analyzed. OCIS codes: 050.1970, 200.4650, 250.0250.

Real-time image processing requires high computational and I/O throughputs obtained by use of optoelectronic system solutions. A novel architecture that uses focal-plane optoelectronic-area I/O with a fine-grain, low-memory, single-instruction-multiple-data (SIMD) processor array is presented as an efficient computational solution for real-time hyperspectral image processing. The architecture is evaluated by use of realistic workloads to determine data throughputs, processing demands, and storage requirements. We show that traditional store-and-process system performance is inadequate for this application domain, whereas the focal-plane SIMD architecture is capable of supporting real-time performances with sustained operation throughputs of 500-1500 gigaoperations/s. The focal-plane architecture exploits the direct coupling between sensor and parallel-processor arrays to alleviate data-bandwidth requirements, allowing computation to be performed in a stream-parallel computation model, while data arrive from the sensors. [C] 2000 Optical Society of America OCIS codes: 100.0100, 110.0110, 100.2000, 100.2550.