Optimal usage of available wiring resources in diffractive-reflective optoelectronic multichip modules

Advances in VLSI and optoelectronic multichip module technologies are enabling the construction of ultracompact massively parallel processing systems. The technological parameters that define the wirability and delay characteristics of these technologies have a significant impact on the system architecture. An analytical model is presented that allows the design space exploration of the interconnection networks associated with multinode chips packaged on a single multichip module substrate. Possible system designs are evaluated for a two-level interconnect with separate k-ary n-cube networks for interchip and intrachip communication. The impact of several architectural and technological parameters on the optimal network implementation (based on average no-load latency) is analyzed. OCIS codes: 050.1970, 200.4650, 250.0250.