1,266 results on '"Cristoloveanu, S."'
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2. Undoped junctionless EZ-FET: Model and measurements
3. Superiority of core–shell junctionless FETs
4. Pseudo-MOSFET transient behavior: Experiments, model, substrate and temperature effect
5. A Novel 1T-DRAM Fabricated With 22 nm FD-SOI Technology
6. A current model for FOI FinFETs with back-gate bias modulation
7. Revisited parasitic bipolar effect in FDSOI MOSFETs: Mechanism, gain extraction and circuit applications
8. A simple test structure for the electrical characterization of front and back channels for advanced SOI technology development
9. Inversion layer electron mobility distribution in fully-depleted silicon-on-insulator MOSFETs
10. Photodiode with low dark current built in silicon-on-insulator using electrostatic doping
11. A2RAM compact modeling: From DC to 1T-DRAM memory operation
12. Impact of contact and channel resistance on the frequency-dependent capacitance and conductance of pseudo-MOSFET
13. New prospects on high on-current and steep subthreshold slope for innovative Tunnel FET architectures
14. Investigation of thin gate-stack Z2-FET devices as capacitor-less memory cells
15. Doping profile extraction in thin SOI films: Application to A2RAM
16. Topology and design investigation on thin film silicon BIMOS device for ESD protection in FD-SOI technology
17. New insights on SOI Tunnel FETs with low-temperature process flow for CoolCube™ integration
18. Kink effect in ultrathin FDSOI MOSFETs
19. A review of the Z2-FET 1T-DRAM memory: Operation mechanisms and key parameters
20. Second Harmonic Generation characterization of SOI wafers: Impact of layer thickness and interface electric field
21. Ultra-low power 1T-DRAM in FDSOI technology
22. Back-gated InGaAs-on-insulator lateral N+NN+ MOSFET: Fabrication and typical conduction mechanisms
23. Low-frequency noise in bare SOI wafers: Experiments and model
24. Fabrication and electrical characterizations of SGOI tunnel FETs with gate length down to 50 nm
25. BIMOS transistor solutions for ESD protection in FD-SOI UTBB CMOS technology
26. Second harmonic generation for contactless non-destructive characterization of silicon on insulator wafers
27. Unusual gate coupling effect in extremely thin and short FDSOI MOSFETs
28. High-resolution mobility spectrum analysis of magnetoresistance in fully-depleted silicon-on-insulator MOSFETs
29. Superior performance and Hot Carrier reliability of strained FDSOI nMOSFETs for advanced CMOS technology nodes
30. Parasitic bipolar effect in ultra-thin FD SOI MOSFETs
31. A Selection of SOI Puzzles and Tentative Answers
32. Floating-Body SOI Memory: The Scaling Tournament
33. Reliability of ultra-thin buried oxides for multi-VT FDSOI technology
34. Investigation of Compressive Strain Effects Induced by STI and ESL
35. Characterization of heavily doped SOI wafers under pseudo-MOSFET configuration
36. A new characterization technique for SOI wafers: Split C(V) in pseudo-MOSFET configuration
37. Characterization and Modeling of Advanced SOI Materials and Devices
38. Recombination Current in Fully-Depleted SOI DIODES: Compact Model and Lifetime Extraction
39. Low-frequency noise and mobility in triple-gate silicon-on-insulator transistors: Evidence for volume inversion effects
40. Tunneling FETs on SOI: Suppression of ambipolar leakage, low-frequency noise behavior, and modeling
41. Performance of (1 1 0) p-channel SOI-MOSFETs fabricated by deep-amorphization and solid-phase epitaxial regrowth processes
42. Low-frequency noise in SOI pseudo-MOSFET with pressure probes
43. Gate-induced drain leakage in FD-SOI devices: What the TFET teaches us about the MOSFET
44. A FinFET memory with remote carrier trapping in ONO buried insulator
45. Detailed investigation of effective field, hole mobility and scattering mechanisms in GeOI and Ge pMOSFETs
46. 3D sequential integration: applications and associated key enabling modules (design & technology)
47. Erratum: Assessment of 180 nm double SOI technology for analog front-end design with back-gate voltage.
48. Low-temperature characterization and modeling of advanced GeOI pMOSFETs: Mobility mechanisms and origin of the parasitic conduction
49. Mobility enhancement by CESL strain in short-channel ultrathin SOI MOSFETs
50. Dynamic body potential variation in FD SOI MOSFETs operated in deep non-equilibrium regime: Model and applications
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