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We like and need Information and Communication Technologies (ICTs) for data processing. This is measurable in the exponential growth of data processed by ICT, e.g., ICT for cryptocurrency mining and search engines. So far, the energy demand for computing technology has increased by a factor of 1.38 every 10 years due to the exponentially increasing use of ICT systems as computing devices. Energy consumption of ICT systems is expected to rise from 1500 TWh (8% of global electricity consumption) in 2010 to 5700 TWh (14% of global electricity consumption) in 2030 [A. S. G. Andrae, Eng. Appl. Sci. Lett. 3, 19–31 (2020)]. A large part of this energy is required for the continuous data transfer between separated memory and processor units, which constitute the main components of ICT computing devices in von-Neumann architecture. This, at the same time, massively slows down the computing power of ICT systems in von-Neumann architecture. In addition, due to the increasing complexity of artificial intelligence (AI) compute algorithms, since 2010, the AI training compute time demand for computing technology has increased tenfold every year, for example, from 1 × 10−6 to 1 × 10+4 Petaflops/day in the period from 2010 to 2020 [J. Wang, see https://ark-invest.com/articles/analyst-research/ai-training/ for information about the cost to train an AI interference system (2020)]. It has been theoretically predicted that ICT systems in the neuromorphic computer architecture will circumvent all of this through the use of merged memory and processor units. However, the core hardware element for this has not yet been realized so far. In this work, we discuss the perspectives for non-volatile resistive switches with hysteretic memristance as the core hardware element for merged memory and processor units in neuromorphic computers. [ABSTRACT FROM AUTHOR]

Recent studies showed an interphase chromosome architecture—a specific coiled nucleosome structure—derived from cryopreserved EM tomograms, and dispersed throughout the nucleus. The images were computationally processed to fill in the missing wedges of data caused by incomplete tomographic tilts. The resulting structures increased z-resolution enabling an extension of the proposed architecture to that of mitotic chromosomes. Here, we provide additional insights into the chromosome architecture that was recently published [M. Elbaum et al., Proc. Natl. Acad. Sci. U.S.A. 119, e2119101119 (2022)]. We build on the defined chromosomes time-dependent structures in an effort to probe their dynamics. Variants of the coiled chromosome structures, possibly further defining specific regions, are discussed. We propose, based on generalized specific uncoiling of mitotic chromosomes in telophase, large-scale reorganization of interphase chromosomes. Chromosome territories, organized as micron-sized small patches, are constructed, satisfying complex volume considerations. Finally, we unveiled the structures of replicated coiled chromosomes, still attached to centromeres, as part of chromosome architecture. [ABSTRACT FROM AUTHOR]

Additive manufacturing (AM) technologies are unleashing the restrictions imposed by conventional manufacturing, allowing the production of innovative designs tailored to improve properties or performance. AM techniques in ceramic production allow the application of novel designs to ceramic parts, opening new opportunities for combining technologies aiming to obtain architected interpenetrating phase composites (IPCs). In this study, alumina structures with different architectures and Computer Aided Design (CAD) structure porosity oriented unidirectionally or bidirectionally, were fabricated by vat photopolymerization technique, namely Digital Light Processing. Afterwards, these structures were infiltrated with an aluminum alloy through investment casting, thus obtaining aluminum-alumina IPCs. Under compression, the IPCs presented a ductile behavior, conversely to the fragile ceramic counterparts. The IPCs compressive strength and absorbed energy were expressively higher than their ceramic counterparts. Comparing the bidirectional IPCs with the unidirectional ones, a significant increase in compressive strength and absorbed energy was observed, from 36.2% to 42.3% and from 164.8% to 358.1%, respectively, due to the greater amount and interconnection of the metal inside the ceramic structure. This study demonstrates the feasibility of this manufacturing route, combining two distinctive technologies, for the fabrication of metal-ceramic architected IPCs, allowing to tailor their mechanical properties and energy absorption capacity for a given application. [ABSTRACT FROM AUTHOR]

Computer vision is a growing field that uses image and video data to help machines understand the world around them. It has applications in areas like medicine, remote sensing, and manufacturing. This special issue contains nineteen scientific articles that cover a range of topics in computer vision, including target detection, facial beauty prediction, and contraband detection. The research aims to improve the accuracy and efficiency of computer vision systems in areas like autonomous driving and surveillance. However, there are challenges that developers need to address, such as algorithm efficiency, the need for labeled data, and biases in AI-based systems. [Extracted from the article]

As manifestations of Industry 4.0. become visible across various applications, one key and opportune area of development are quality inspection processes and defect detection. Over the last decade, computer vision architectures, in particular, object detectors have received increasing attention from the research community, due to their localisation advantage over image classification. However, for these architectural advancements to provide tangible solutions, they must be optimised with respect to the target hardware along with the deployment environment. To this effect, this survey provides an in-depth review of the architectural progression of image classification and object detection architectures with a focus on advancements within Artificially Intelligent accelerator hardware. This will provide readers with an understanding of the present state of architecture–hardware integration within the computer vision discipline. The review also provides examples of the industrial implementation of computer vision architectures across various domains, from the detection of fabric defects to pallet racking inspection. The survey highlights the need for representative hardware-benchmarked datasets for providing better performance comparisons along with envisioning object detection as the primary domain where more research efforts would be focused over the next decade. [ABSTRACT FROM AUTHOR]

In this article, a comprehensive review is presented of recent technological advancements utilizing electromagnetic sensors in the microwave range for detecting human vital signs and lung water levels. With the main objective of improving detection accuracy and system robustness, numerous advancements in front-end architecture, detection techniques, and system-level integration have been reported. The benefits of non-contact vital sign detection have garnered significant interest across a range of applications, including healthcare monitoring and search and rescue operations. Moreover, some integrated circuits and portable systems have lately been shown off. A comparative examination of various system architectures, baseband signal processing methods, system-level integration strategies, and possible applications are included in this article. Going forward, researchers will continue to focus on integrating radar chips to achieve compact form factors and employ advanced signal processing methods to further enhance detection accuracy. [ABSTRACT FROM AUTHOR]

The Internet has become the primary vehicle for doing almost everything online, and smartphones are needed for almost everyone to live their daily lives. As a result, cybersecurity is a top priority in today's world. As Internet usage has grown exponentially with billions of users and the proliferation of Internet of Things (IoT) devices, cybersecurity has become a cat-and-mouse game between attackers and defenders. Cyberattacks on systems are commonplace, and defense mechanisms are continually updated to prevent them. Based on a literature review of cybersecurity vulnerabilities, attacks, and preventive measures, we find that cybersecurity problems are rooted in computer system architectures, operating systems, network protocols, design options, heterogeneity, complexity, evolution, open systems, open-source software vulnerabilities, user convenience, ease of Internet access, global users, advertisements, business needs, and the global market. We investigate common cybersecurity vulnerabilities and find that the bare machine computing (BMC) paradigm is a possible solution to address and eliminate their root causes at many levels. We study 22 common cyberattacks, identify their root causes, and investigate preventive mechanisms currently used to address them. We compare conventional and bare machine characteristics and evaluate the BMC paradigm and its applications with respect to these attacks. Our study finds that BMC applications are resilient to most cyberattacks, except for a few physical attacks. We also find that BMC applications have inherent security at all computer and information system levels. Further research is needed to validate the security strengths of BMC systems and applications. [ABSTRACT FROM AUTHOR]

This letter focuses on the field-programmable gate array (FPGA) implementation of a Class A Middleton noise estimator, aiming to enhance its efficiency and performance. The inherent algorithm of the estimator undergoes strategic enhancements, leveraging median approximations. This endeavor leads to the development of a more streamlined and expeditious architecture. The research not only introduces the refined architecture but also conducts a comparative analysis of its attributes. The outcomes of this investigation show the benefits of algorithmic optimization, as the execution times achieved in hardware significantly surpass those attainable through software-based implementation. This underscores the practicality of the algorithmic refinement and also the notable advantages of the FPGA-based execution in terms of computational speed. [ABSTRACT FROM AUTHOR]

Insect biodiversity and abundance are in global decline, potentially leading to a crisis with profound ecological and economic consequences. Methods and technologies to monitor insect species to aid in preservation efforts are rapidly being developed yet their adoption has been slow and focused on specific use cases. We propose a computer vision model that works towards multi-objective insect species identification in real-time and on a large scale. We leverage an image data source with 16 million instances and a recent improvement in the YOLO computer vision architecture to present a quick and open-access method to develop visual AI models to monitor insect species across climatic regions. [ABSTRACT FROM AUTHOR]

Adversarial training suffers from poor effectiveness due to the challenging optimisation of loss with hard labels. To address this issue, adversarial distillation has emerged as a potential solution, encouraging target models to mimic the output of the teachers. However, reliance on pre‐training teachers leads to additional training costs and raises concerns about the reliability of their knowledge. Furthermore, existing methods fail to consider the significant differences in unconfident samples between early and late stages, potentially resulting in robust overfitting. An adversarial defence method named Clean, Performance‐robust, and Performance‐sensitive Historical Information based Adversarial Self‐Distillation (CPr & PsHI‐ASD) is presented. Firstly, an adversarial self‐distillation replacement method based on clean, performance‐robust, and performance‐sensitive historical information is developed to eliminate pre‐training costs and enhance guidance reliability for the target model. Secondly, adversarial self‐distillation algorithms that leverage knowledge distilled from the previous iteration are introduced to facilitate the self‐distillation of adversarial knowledge and mitigate the problem of robust overfitting. Experiments are conducted to evaluate the performance of the proposed method on CIFAR‐10, CIFAR‐100, and Tiny‐ImageNet datasets. The results demonstrate that the CPr&PsHI‐ASD method is more effective than existing adversarial distillation methods in enhancing adversarial robustness and mitigating robust overfitting issues against various adversarial attacks. [ABSTRACT FROM AUTHOR]

This paper aims to propose innovative actions of advanced technological solutions and consequent necessary institutional decisions to achieve in a reasonable time the definitive confidential data protection and data sovereignty, based on available scientific results. Confidential data protection is a fundamental and strategic issue in next-generation Internet systems to guarantee data sovereignty and the respect of human rights as stated in the foundation of the United Nations. Even if presently many international regulations are decisive steps to guarantee data protection within normative contexts, they are not adequate to face new technologies, such as facial recognition, automatic profiling, position tracking, biometric data, AI applications, and many others in the future, as they are implemented without any awareness by the interested subjects. Therefore, a new approach to data protection is mandatory based on innovative and disruptive technological solutions. A recent OECD report highlighted the need for the so-called Privacy-Enhancing Technologies (PETs) for the effective protection of confidential data, even more urgent for the coexistence of privacy and data sharing in international contexts. A common feature of these technologies is the use of software methodologies that can run on currently available microprocessors and their present immaturity. More effective and definitive protection can be achieved with another methodological approach based on the paradigm of 'Data Usage Control'. This new concept guarantees data protection policy by default and initial design and it requires a new architecture of the data and a new HW&SW architecture of the computers. This contribution has a two-fold objective: first, to clarify why regulations alone and present technological proposals are not adequate for the effective and definitive protection of data and, second, to indicate the new necessary technological approach and the simultaneous institutional actions required to achieve the definitive protection and sovereignty of data in reasonable times, based on the results already available in the scientific literature. [ABSTRACT FROM AUTHOR]

The current article discusses Sierpinski networks, which are fractal networks with certain applications in computer science, physics, and chemistry. These networks are typically used in complicated frameworks, fractals, and recursive assemblages. The results derived in this study are in mathematical and graphical format for particular classes of these networks of two distinct sorts with two invariants, K-Banhatti Sombor (KBSO) and Dharwad, along with their reduced forms. These results can facilitate the formation, scalability, and introduction of novel interconnection network topologies, chemical compounds, and VLSI processor circuits. The mathematical expressions employed in this research offer modeling insights and design guidelines to computer engineers. The derived simulation results demonstrate the optimal ranges for a certain network. The optimization assistant tool deployed in this work provides a single maximized value representing the maximum optimized network. These ranges can be put into service to dynamically establish a network according to the requirements of this paper. [ABSTRACT FROM AUTHOR]

Neuromorphic computing (NC) is a crucial step toward realizing power-efficient artificial intelligence systems. Hardware implementation of NC is expected to overcome the challenges associated with the conventional von Neumann computer architecture. Synaptic devices that can emulate the rich functionalities of biological synapses are emerging. Out of several approaches, electrolyte-gated synaptic transistors have attracted enormous scientific interest owing to their similar working mechanism. Here, we report a three-terminal electrolyte-gated synaptic transistor based on Fe3O4 thin films, a half-metallic spinel ferrite. We have realized gate-controllable multilevel, non-volatile, and rewritable states for analog computing. Furthermore, we have emulated essential synaptic functions by applying electrical stimulus to the gate terminal of the synaptic device. This work provides a new candidate and a platform for spinel ferrite-based devices for future NC applications. [ABSTRACT FROM AUTHOR]

Neuromorphic devices that parallelize perception, preprocessing, and computation functions are expected to play a significant role in future non‐von Neumann architecture computers. Herein, a new retina‐inspired broadband self‐powered optoelectronic synaptic device based on 2D/3D heterojunction of epitaxial InSe on GaN(0001) is reported. Few‐layer n‐type InSe is grown on p‐type GaN by physical vapor deposition in an ultra‐high vacuum (UHV) environment. The devices are fabricated using a shadow mask assisted UHV electrode deposition technique. High‐resolution transmission electron microscopy images reveal that an atomically thin amorphous layer, which induces highly efficient charge trapping, is formed at the InSe/GaN interface. The photoresponse spans from visible to near‐infrared, and the response time is prolonged to 103 ms owing to the deep trapping levels. Thus, synaptic functions, including excitatory postsynaptic current, paired‐pulse facilitation with a high index of up to 170%, short‐term plasticity, and high‐pass filtering characteristics, are realized. Additionally, the synapses demonstrated the merit of realizing image sharpening and arithmetic operations on the same device under infrared and visible light illumination. This study provides a new platform of 2D/3D heterostructures for robust optoelectronic synapses that may find applications in post‐Moore era neuromorphic vision systems. [ABSTRACT FROM AUTHOR]

Energy distribution networks represent crucial infrastructures for modern society, and various simulation tools have been widely used by energy suppliers to manage these intricate networks. However, simulation calculations include a large number of fluid control equations, and computational overhead limits the performance of simulation software. This paper proposes a universal parallel simulation framework for energy pipeline networks that takes advantages of data parallelism and computational independence between network elements. A non-pipe model of an energy supply network is optimized, and the input and output of the network model in the proposed framework are modified, which can reduce the development burden during the numerical computations of the pipeline network and weaken the computational correlation between different simulated components. In addition, independent computations can be performed concurrently through periodic data exchange procedures between component instances, improving the parallelism and efficiency of simulation computations. Further, a parallel water pipelines network simulation computing paradigm based on a heterogeneous computer hardware architecture is used to evaluate the proposed framework's performance. A series of tests are conducted to verify the accuracy of the proposed framework, and simulation errors of less than 5% are achieved. The results of multi-threaded simulation experiments have demonstrated the feasibility of the proposed framework in a parallel computing approach. Moreover, an Advanced Micro Devices (AMD) Deep Computing Unit (DCU)-parallel program is implemented into a water supply network simulation system; the computational efficiency of this system is compared with that of its serial counterpart. The experimental results show that the proposed framework is appropriate for high-performance computer architectures, and the 18x speed-up ratio demonstrates that the parallel program based on the proposed universal framework outperforms the serial program. That provides the basis for the application of pipe network simulation on high-performance computers. [ABSTRACT FROM AUTHOR]

In today's digital landscape, organizations face significant challenges, including sensitive data leaks and the proliferation of hate speech, both of which can lead to severe consequences such as financial losses, reputational damage, and psychological impacts on employees. This work considers a comprehensive solution using a microservices architecture to monitor computer usage within organizations effectively. The approach incorporates spyware techniques to capture data from employee computers and a web application for alert management. The system detects data leaks, suspicious behaviors, and hate speech through efficient data capture and predictive modeling. Therefore, this paper presents a comparative performance analysis between Spring Boot and Quarkus, focusing on objective metrics and quantitative statistics. By utilizing recognized tools and benchmarks in the computer science community, the study provides an in-depth understanding of the performance differences between these two platforms. The implementation of Quarkus over Spring Boot demonstrated substantial improvements: memory usage was reduced by up to 80% and CPU usage by 95%, and system uptime decreased by 119%. This solution offers a robust framework for enhancing organizational security and mitigating potential threats through proactive monitoring and predictive analysis while also guiding developers and software architects in making informed technological choices. [ABSTRACT FROM AUTHOR]

In this paper, we first analyze a real storage system consisting of 72 SSDs utilizing either Hardware RAID (HW-RAID) or Software RAID (SW-RAID), and show that SW-RAID is up to 7× faster. We then reveal that with an increasing number of SSDs, the limited I/O parallelism in SAS controllers and multi-enclosure handshaking overheads cause a significant performance drop, minimizing the total I/O Per Second (IOPS) of a 144-SSD system to less than a single SSD. Second, we disclose the most important architectural parameters that affect a large-scale storage system. Third, we propose a framework that models a large-scale storage system and estimates the system IOPS and system resource usage for various architectures. We verify our framework against a real system and show its high accuracy. Lastly, we analyze a use case of a 240-SSD system and reveal how our framework guides architects in storage system scaling. [ABSTRACT FROM AUTHOR]

Modern computer designs support composite prefetching, where multiple prefetcher components are used to target different memory access patterns. However, multiple prefetchers competing for resources can sometimes hurt performance, especially in many-core systems where cache and other resources are limited. Recent work has proposed mitigating this issue by selectively enabling and disabling prefetcher components at runtime. Formulating the problem with machine learning (ML) methods is promising, but efficient and effective solutions in terms of cost and performance are not well understood. This work studies fundamental characteristics of the composite prefetcher selection problem through the lens of ML to inform future prefetcher selection designs. We show that prefetcher decisions do not have significant temporal dependencies, that a phase-based rather than sample-based definition of ground truth yields patterns that are easier to learn, and that prefetcher selection can be formulated as a workload-agnostic problem requiring little to no training at runtime. [ABSTRACT FROM AUTHOR]

GPUs are widely used for diverse applications, particularly data-parallel tasks like machine learning and scientific computing. However, their efficiency is hindered by architectural limitations, inherited from historical RISC processors, in handling memory loads causing high register file contention. We observe that a significant number (around 26%) of values present in the register file are typically used only once, contributing to more than 25% of the total register file bank conflicts, on average. This paper addresses the challenge of single-use memory values in the GPU register file (i.e. data values used only once) which wastes space and increases latency. To this end, we introduce a novel mechanism inspired by CISC architectures. It replaces single-use loads with direct memory operands in arithmetic operations. Our approach improves performance by 20% and reduces energy consumption by 18%, on average, with negligible (<1%) hardware overhead. [ABSTRACT FROM AUTHOR]

Emergent states are temporal group phenomena that arise from collective affective, behavioral, and cognitive processes shared among the group's members during their interactions. Cohesion is one such state, mainly conceptualized by scholars as affective in nature, and frequently distinguished into the two dimensions social and task cohesion. Whereas social cohesion is related to the need of belonging to a group, task cohesion is related to the group's goals and tasks. In this article, we emphasize the importance of behavioral interaction dynamics to predict cohesion's dynamics. Drawing from Social Science insights, we investigate the interplay between social and task cohesion to predict their dynamics across group tasks from nonverbal behavioral features. Three computational architectures exploiting transfer learning are presented. Transfer learning capitalizes on information learnt by a model for a specific dimension to predict the dynamics of the other dimension. Results show that integrating the influence of social cohesion to predict dynamics of task cohesion outperforms state-of-the-art. To predict dynamics of social cohesion, a model integrating the reciprocal impact of social and task cohesion significantly improves performance with respect to the state-of-the-art and a model only integrating the impact of task cohesion on dynamics of social cohesion. [ABSTRACT FROM AUTHOR]

Self-supervised learning has shown value for uncovering informative movement features for human activity recognition. However, there has been minimal exploration of this approach for affect recognition where availability of large labelled datasets is particularly limited. In this paper, we propose a P-STEMR (Parallel Space-Time Encoding Movement Representation) architecture with the aim of addressing this gap and specifically leveraging the higher availability of human activity recognition datasets for pain-level classification. We evaluated and analyzed the architecture using three different datasets across four sets of experiments. We found statistically significant increase in average F1 score to 0.84 for pain level classification with two classes based on the architecture compared with the use of hand-crafted features. This suggests that it is capable of learning movement representations and transferring these from activity recognition based on data captured in lab settings to classification of pain levels with messier real-world data. We further found that the efficacy of transfer between datasets can be undermined by dissimilarities in population groups due to impairments that affect movement behaviour and in motion primitives (e.g. rotation versus flexion). Future work should investigate how the effect of these differences could be minimized so that data from healthy people can be more valuable for transfer learning. [ABSTRACT FROM AUTHOR]

This article introduces a deniable ring signature scheme within the framework of a ring signature protocol, which allows a member of the ring to assert or deny their role as the signature's originator without the involvement of a trusted third party. Deniable ring signatures find applications in various scenarios where balancing privacy protection with supervised oversight is crucial. In this work, we present a novel deniable ring signature scheme based on the ISRSAC digital signature, tailored for environments with regulatory requirements, empowering regulators to hold malicious signers accountable. We formally validate the scheme's correctness, unforgeability, anonymity, traceability, and non-frameability through rigorous proofs. Additionally, we conduct a comparative analysis of the communication and computational overheads associated with our proposed scheme, demonstrating its superiority in practical scenarios such as electronic auctions and anonymous reporting mechanisms. [ABSTRACT FROM AUTHOR]

Graph processing is a vital component of many AI and big data applications. However, due to its poor locality and complex data access patterns, graph processing is also a known performance killer of AI and big data applications. In this work, we propose to enhance graph processing applications by leveraging fine-grained memory access patterns with a dual-path architecture on top of existing software-based graph optimizations. We first identify that memory accesses to the offset, edge, and state array have distinct locality and impact on performance. We then introduce the Skyway architecture, which consists of two primary components: 1) a dedicated direct data path between the core and memory to transfer state array elements efficiently, and 2) a data-type aware fine-grained memory-side row buffer hardware for both the newly designed direct data path and the regular memory hierarchy data path. The proposed Skyway architecture is able to improve the overall performance by reducing the memory access interference and improving data access efficiency with a minimal overhead. We evaluate Skyway on a set of diverse algorithms using large real-world graphs. On a simulated four-core system, Skyway improves the performance by 23% on average over the best-performing graph-specialized hardware optimizations. [ABSTRACT FROM AUTHOR]

Virtualization technologies are extensively utilized in data centers, particularly cloud computing. This facilitates data center management and diminishes the number of physical machines (servers) and, subsequently, their cooling requirements, leading to cost, space, and power consumption reductions. When applications in data centers are executing independent parallel transactions, but with similar performance requirements, the appropriate level of virtual machine consolidation on a server poses a fundamental challenge for capacity planning. This article introduces a method to evaluate the performance speedup achieved through virtualization on any server and the effects of virtualization and consolidation overheads on physical or virtual machine scalability. This research formalizes the speedup and overheads, using classical computer architecture statements. but at the same time proposes a new method to analyze these overhead amounts and types, showing the scalability and efficiency of different consolidations in the same server and its comparison against no consolidation. This work also proposes a new way to determine the optimal number of physical servers and the optimal number of consolidated virtual machines for a given transaction workload. The real experimentation was performed with different workload sizes, types of virtualizations and different servers. The method presented also facilitates the representation of linear scalability against the real degree of parallelism of either physical machines or consolidated virtual machines for a given transaction workload, as well as striking the right balance between speedup and energy in virtual server consolidation. [ABSTRACT FROM AUTHOR]

The count, location, and size of shrimp larvae are important observations for their intensive breeding, which could evaluate the culture density, growth, and yield. Recent works on the counting of dense aquatic objects in an image are mainly accomplished by the density map regression based on convolutional neural network (CNN). These regression methods only give the estimated density map and the corresponding count, but cannot locate and size the objects accurately. To realize the noninvasive counting, locating, and sizing during aquatic breeding, we propose a novel detection architecture in computer vision for the larvae of Cherax quadricarinatus. In particular, a new shrimp larvae counting network (SLCNet) using the density map regression is designed to output the estimated density map of the shrimp larvae image and predict the corresponding number of the shrimp larvae. The local peak filtering (LPF) is applied to the estimated density map to locate the coordinates of every shrimp larva. We then use the K-nearest neighbor (KNN) and the bounding box search to find the fitting bounding boxes of the shrimp larvae in sparse regions and calculate the body length of the shrimp larvae in the fitting bounding boxes with the aid of the least squares regression method. Compared with typical CNN-based counting models, the mean absolute error and root mean square error of the proposed SLCNet are 4.13 and 5.75, respectively, and the counting accuracy is up to 98.57%. Then, we perform the detection of the location and size of the shrimp larvae using the density map estimated by the SLCNet. The locating and sizing accuracy can reach 90.6% (i.e., F1 value) and 90.28%, respectively. It proves that this detection architecture could be used as technical support for subsequent studies on larva growth and behavior recognition. [ABSTRACT FROM AUTHOR]

The rapid advancements in artificial intelligence (AI) have demonstrated great success in various applications, such as cloud computing, deep learning, and neural networks, among others. However, the majority of these applications rely on fast computation and large storage, which poses significant challenges to the hardware platform. Thus, there is a growing interest in exploring new computation architectures to address these challenges. Compute-in-memory (CIM) has emerged as a promising solution to overcome the challenges posed by traditional computer architecture in terms of data transfer frequency and energy consumption. Non-volatile memory, such as Quantum-dot transistors, has been widely used in CIM to provide high-speed processing, low power consumption, and large storage capacity. Matrix-vector multiplication (MVM) or dot product operation is a primary computational kernel in neural networks. CIM offers an effective way to optimize the performance of the dot product operation by performing it through an intertwining of processing and memory elements. In this paper, we present a novel design and analysis of a Quantum-dot transistor (QDT) based CIM that offers efficient MVM or dot product operation by performing computations inside the memory array itself. Our proposed approach offers energy-efficient and high-speed data processing capabilities that are critical for implementing AI applications on resource-limited platforms such as portable devices. [ABSTRACT FROM AUTHOR]

Radio sensing is a key envisioned feature for next-generation wireless systems, allowing the use of communication infrastructure and air interface components to also perceive the environment. Enabling efficient use of radio access network (RAN) resources to meet various communication and sensing use case requirements is a primary goal in such systems. This article bridges the gap among RAN architecture requirements, along with radio and signal processing techniques to realize the integration of radar sensing into next-generation cellular systems, e.g., the open RAN (O-RAN) framework. Motivated by the O-RAN disaggregated architecture, this article introduces a framework to analyze sensing processing from the perspective of the radio unit (RU)–distributed unit (DU) functional split and the fronthaul throughput requirements of interfaces between RUs and DUs. Accordingly, the feasibility of adopting sensing in current architectures while meeting fronthaul throughput limitations is demonstrated. Further, it is shown that receiver (Rx) processing techniques tailored for cellular system (e.g., to enable wideband sensing over disjoint bandwidths) can efficiently fit into the DU processing framework. Evaluation results revealing detection performance gains are also presented. [ABSTRACT FROM AUTHOR]

With the ongoing expansion of user numbers and the diversity of business types, wireless networks are progressing toward broader spatial dimensions and increased functionality. With respect to coverage, the space–air–ground integrated network (SAGIN) is considered a promising solution for providing seamless global connectivity to emerging services. In terms of functionality, wireless networks are expected to offer not only communication services but also sensing and computing services, which are crucial for certain businesses. However, within SAGIN there is a significant variance in performance among different types of radio access networks (RANs). This necessitates a reconsideration of system architecture and handover selection schemes to meet the quality of service (QoS) requirements of various business applications. The main focus of this article is to explore the integration of sensing and mobile edge computing (MEC) with SAGIN and also to examine the system architecture, selection schemes, and handover procedures. We first provide an overview of SAGIN’s capabilities and highlight its integrated architecture. Subsequently, we introduce several handover selection schemes, followed by an elaboration on the redesigned handover procedure for SAGIN. Finally, we present some simulation results and discuss challenges that need to be addressed in practical implementation. [ABSTRACT FROM AUTHOR]

Distributed public ledgers, the key to modern cryptocurrencies and the heart of many novel applications, have scalability problems. Ledgers such as the blockchain underlying Bitcoin can process fewer than 10 transactions per second (TPS). The cost of transactions is high, and the time to confirm a transaction is in the minutes. We present the BlockGraph, a scalable distributed public ledger inspired by principles of computer architecture. The BlockGraph exploits the natural locality of transactions to allow publishing independent transactions in parallel. It extends the blockchain with three new transactions to create a unified consistent ledger out of essentially independent blockchains. The most important change is the introduction of the blockstamp transaction, which essentially checkpoints a local blockchain and secures it against attack. The result is a locality-based, simple, secure, sharding protocol which keeps all transactions readable. This paper introduces the BlockGraph protocol, proves that it is consistent and can achieve many thousands of TPS. Using our implementation (a small extension to Bitcoin core) we demonstrate that it, in practice, can significantly improve throughput. [ABSTRACT FROM AUTHOR]

In this study, we obtain a sex prediction algorithm based on CNN in two ways - building a red Convolutional Neural Network (CNN) model from scratch and via transfer learning. We built a model from scratch and compared it with fine-tuned EfficientNetB1. We use these models for gender determination using periocular images and compare the two models depending on the accuracy of the models. The CNN model proposed from scratch yields an accuracy of 94.46% while the fine-tuned EfficientNetB1 yields an accuracy of 97.94%. This paper is one of the first works in determining gender from periocular images in the visible spectrum using a CNN model built from the outset. [ABSTRACT FROM AUTHOR]

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In the current subsea industry scenario, autonomous underwater vehicles (AUVs) are widely used for expeditions and explorations. However, the mission duration is limited due to the limitations in the battery capacity. To increase the endurance, there is a need for a submerged docking station (DS) to charge the battery, also to update the next mission profile. In this letter, deep learning (DL) technique aided short-range vision guidance is envisaged for a reliable and precise AUV homing operation. Intelligent control algorithms with an efficient DL-based you only look once (YOLO) v5-image processing techniques are used for DS detection and tracking and deployed in an edge computer integrated into AUV prototype. The developed illuminated DS and AUV prototype with high-definition camera has been demonstrated in test tank at depth of 2 m. An analysis was conducted on the DS data set, which comprised 132 images of clear and turbid water, 13 were designated for testing, 40 for validation, and 79 for training purposes. The results were observed that the probability of detecting the DS is 95%, detection range is 5 m, the probability of homing toward the DS is CEP 90 with the position error of 5% in less-turbid waters and in high-turbid waters, 60% is the probability of DS detection with position error up to 25%, detectable range is 1 m. The proposed embedded hardware is extremely useful for underwater reliable homing applications. [ABSTRACT FROM AUTHOR]

Recent GPUs provisioned with large register files (RFs) cannot fully utilize the bandwidth between the RFs and execution pipelines, as the current policy for allocating operand (OP) collectors defers the RF accesses until all the source OPs become ready. To tackle this issue, this letter introduces a new OP collector allocation mechanism called Triple-A. Triple-A comprises four key operations. First, Triple-A proactively allocates an OP collector (OC) to a warp instruction even if one of its source OPs is not yet ready, taking advantage of GPUs’ in-order execution. Second, a computation result can be directly forwarded to an early allocated OC along with a data dependence, reducing OP loading time from the RFs. Third, Triple-A bypasses RF write operations if the forwarded data is not consumed by any other instruction. Finally, the early allocation is further enhanced with latency-aware optimization, alleviating the potential performance degradation caused by allocating OCs aggressively. Together, these techniques synergistically improve the register bank utilization, demonstrating a 14.1% improvement in performance and an 11.8% reduction in RF energy consumption compared to the state-of-the-art GPUs. [ABSTRACT FROM AUTHOR]

Building and testing software for embedded systems can be challenging with an impact on delivery time, design reproducibility, and collaboration among project contributors. To accelerate project development, presented here is an automated build flow that utilizes Xilinx PetaLinux, and field programmable gate array (FPGA) hardware description and integrates with the GitLab continuous integration and continuous deployment (CI/CD) framework for embedded targets. This build flow automates the complete process of FPGA implementation, PetaLinux configuration, and cross-compilation of software essentials for the target system-on-chip (SoC). The system has been successfully deployed in cross-compiling the control and command toolset for the Positron Emission Tomography scanner (PhenoPET) and the implementation of the message queuing telemetry transport (MQTT) service on a Xilinx Zynq Ultrascale MPSoC. This approach can be easily adapted to other projects with specific requirements. [ABSTRACT FROM AUTHOR]

This essay makes a bibliographic review in the field of the seminal research of Organizational Networks, through a conceptual and instrumental analogy using an integration analysis of MaccInnis. In its development, seven different components of Organizational Networks and phenomena linked to Computer Networks were identified. By delimiting the specific configurations of each network, it is possible to propose a link between the elements of computer architecture and the field of study of Organizational Networks to support the understanding of the latter and thus contribute both to the strengthening of academic research and to the evaluation of their managerial implications in current environments of growing complexity and competitiveness. [ABSTRACT FROM AUTHOR]

This research examines the impact of three widely utilized regularization approaches - data augmentation, weight decay, and dropout -on mitigating overfitting, as well as various amalgamations of these methods. Employing a Convolutional Neural Network (CNN), the study assesses the performance of these strategies using two distinct datasets: a flower dataset and the CIFAR-10 dataset. The findings reveal that dropout outperforms weight decay and augmentation on both datasets. Additionally, a hybrid of dropout and augmentation surpasses other method combinations in effectiveness. Significantly, integrating weight decay with dropout and augmentation yields the best performance among all tested method blends. Analyses were conducted in relation to dataset size and convergence time (measured in epochs). Dropout consistently showed superior performance across all dataset sizes, while the combination of dropout and augmentation was the most effective across all sizes, and the triad of weight decay, dropout, and augmentation excelled over other combinations. The epoch-based analysis indicated that the effectiveness of certain techniques scaled with dataset size, with varying results. [ABSTRACT FROM AUTHOR]

The manuscript theoretically discusses various important aspects for donor atom based single qubit operations in silicon (Si) quantum computer architecture at room temperature using a single nitrogen (N) deep‐donor close to the Si/SiO2 interface. Quantitative investigation of room temperature single electron shuttling between a single N‐donor atom and the interface is the focus of attention under the influence of externally applied electric and magnetic field. To apprehend the realistic experimental configurations, central cell correction along with effective mass approach is adopted throughout the study. Furthermore, a detailed discussion currently explores the significant time scales implicated in the process and their suitability for experimental purposes. Theoretical estimates are also provided for all the external fields required to successfully achieve coherent single electron shuttling and their stable maintenance at the interface as required. The results presented in this work offer practical guidance for quantum electron control using N‐donor atoms in Si at room temperature. [ABSTRACT FROM AUTHOR]

Fog computing is a computer architecture consisting of fog nodes, a collection of near-user edge devices. These fog nodes collaborate to perform computational services like data retrieval, processing, storage, etc. Resource allocation is one of the most critical and challenging problems in the fog environment for industrial applications. The significant aspects to consider while allocating resources are response time, throughput, and energy consumption. The proposed work formulated the resource allocation problem as a bi-objective minimization problem. The main aim of the work is to reduce energy consumption and makespan while allocating service requests to virtual machines. The proposed technique uses the league championship algorithm to select an efficient resource for productive and resourceful service allocation of tasks in fog computing. The proposed algorithm's performance is assessed by comparing it to three well-known metaheuristic algorithms. Finally, the simulation results show that the proposed algorithm is superior in terms of makespan and energy consumption. [ABSTRACT FROM AUTHOR]

What is a supercomputer and why is it needed? What place does it occupy among computing equipment? Thanks to this article, we will determine the evolution and role of the supercomputer in the modern world and in the life of an average citizen. A supercomputer is a class of the most powerful computer systems available, which are evaluated in comparison with currently existing general purpose computer systems and the level of technology development. In general, the term "supercomputer" refers to a complex of server computers. All of them are connected to each other and work in parallel through a high-speed network. The similarity of a home computer and a supercomputer lies in their functions – data storage and processing, belonging to the same von Neumann architecture (the architecture of computing machines, the feature of which is the joint storage of data and machine commands in cells of the same memory). But the difference is huge in quantitative characteristics: these are the arrays of data that can be processed on these devices and the speed of performing the assigned tasks. By the way, a new unit of measurement – FLOPS – was proposed for measuring the speed of supercomputers. It is thanks to this value that performance is measured - the higher the number, the more powerful the computer is and which serves as the basis for ranking supercomputers. Today, supercomputers help solve a number of tasks in various fields – medicine, physics, mathematics, energy, etc. and are considered advanced computing technology. Traditionally, supercomputers are not considered rare: their development is ongoing and they bring a lot of benefits in many areas. In the future, powerful computing machines can become the main assistants in fields closely related to machine learning and artificial intelligence.