Search

Background and Objectives: Considering the fast growing low-power internet of things, the power/energy and performance constraints have become more challenging in design and operation time. Static and dynamic variations make the situation worse in terms of reliability, performance, and energy consumption. In this work, a novel slack measurement circuit is proposed to have precise frequency management based on timing violation measurement.Methods: Proposed slack measurement circuit is based on measuring the delay difference between the edge clock pulse and possible transition on path end-points (primary outputs of design). The output of proposed slack monitoring circuits is a digital code related to the current state of target critical path delay. In order to convert this digital code to equivalent delay difference, the delay of a reference gate is mandatory which is basic unit in proposed monitor. This monitor enables the design to have more precise and efficient frequency management, while maintaining the correct functionality regarding low-power mode. Results: Applying this method on a MIPS processor reduces the amount of performance penalty and recovery energy overhead up to 30% with only 2% additional hardware. Results for benchmark applications in low-power mode, show 7-30% power improvement in normal execution mode. If the application is resilient against occurred errors duo to timing violations, proposed method achieves 20-60% power reduction considering approximate computation as long as application is showing resilience. The performance of proposed method depends on the degree of application resilience against the timing errors. In order to keep generality of propsoed monitor for different applications, the resilience threshold is user programmable to configure according to the requirements of each application.Conclusion: The results show that precise frequency scheduling is more energy/power efficient in static and dynamic variation management. Utilizing a proper monitor capable of measureing the amount of violation will help to have finer frequency management. At the other hand, this method will help to use the resilience of application according to estimation about the possible error value based on measured vilation amount.

Background and Objectives: Considering the fast growing low-power internet of things, the power/energy and performance constraints have become more challenging in design and operation time. Static and dynamic variations make the situation worse in terms of reliability, performance, and energy consumption. In this work, a novel slack measurement circuit is proposed to have precise frequency management based on timing violation measurement. Methods: the Proposed slack measurement circuit is based on measuring the delay difference between the edge clock pulse and possible transition on path end-points (primary outputs of design). The output of the proposed slack monitoring circuits is a digital code related to the current state of target critical path delay. In order to convert this digital code to equivalent delay difference, the delay of a reference gate is mandatory which is the basic unit in the proposed monitor. This monitor enables the design to have more precise and efficient frequency management, while maintaining the correct functionality regarding low-power mode. Results: Applying this method on a MIPS processor reduces the amount of performance penalty and recovery energy overhead up to 30% with only 2% additional hardware. Results for benchmark applications in low-power mode, show 7-30% power improvement in normal execution mode. If the application is resilient against occurred errors duo to timing violations, the proposed method achieves 20-60% power reduction considering approximate computation as long as application is showing resilience. The performance of the proposed method depends on the degree of application resilience against the timing errors. In order to keep generality of the proposed monitor for different applications, the resilience threshold is user programmable to configure according to the requirements of each application. Conclusion: The results show that precise frequency scheduling is more energy/power efficient in static and dynamic variation management. Utilizing a proper monitor capable of measuring the amount of violation will help to have finer frequency management. On the other hand, this method will help to use the resilience of application according to estimation about the possible error value based on measured violation amount. [ABSTRACT FROM AUTHOR]

Near-threshold computing brings several times of magnitude improvement in energy efficiency of digital circuits. However, it also introduces several times of deteriorated delay variations caused by process, voltage, and temperature (PVT) variations. In situ timing monitoring-based adaptive techniques can mitigate excessive timing margins caused by PVT variations, but current frequency and/or voltage tuning methods cause large performance loss. In this paper, we propose a low overhead timing error prediction monitor and a super-fast clock stretching circuit to solve this problem. They are both optimized for near threshold voltage of 0.5 V. When there are timing margins, the frequency will be increased. Until when the timing is intense due to variations, timing monitors will generate a predicted alarm signal. Accordingly, the system clock will be stretched immediately to avoid real timing errors. Applied on a 40-nm CMOS Bitcoin Miner chip, simulation results show that the whole system operating at near-threshold voltage can increase the frequency to up to 2.1× compared with the original non-monitored circuit. Our method can increase the energy efficiency to mitigate near-threshold variations effectively.

To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This article presents two variants of a 32-bit RISC CPU targeted for near-threshold voltage. Both CPUs are placed on the same die and manufactured in 28 nm CMOS process. They employ timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing performance and energy efficiency at a given operating point. Measurements show minimum energy of 3.15 pJ/cyc at 400 mV, which corresponds to 39% energy saving compared to operation based on static signoff timing.

Adaptive voltage frequency scaling (AVFS) techniques based on in-situ timing monitoring can mitigate the excessive timing margin caused by process, voltage and temperature (PVT) variations. However, they usually adjust the frequency by clock gating, clock half-division, or phase locked loop configuration, which cause large performance loss or need a long lock time. Thus, a compact structured adaptive clock stretching circuit is proposed here for very rapid frequency adjustment. It is very useful for AVFS systems by stretching the clock cycle with only within-a-cycle response time. The proposed architecture generates multi-phase clocks through a series of delay elements and continuously picks an appropriate phase clock to form a stretched clock. It also uses a process voltage temperature monitor to adjust the phase clock selection and makes this circuit suitable under PVT variations. Fabricated in 40-nm CMOS process, it only occupies a core area of 85* $83~{\mu }\text{m}^{2}$. Measurements show that it can stretch the clock cycle immediately upon the stretch signal with within-a-cycle response time. It has a wide voltage range from 0.43 V to 1.1 V, with power consumptions of $38.2~{\mu }\text{W}$ at 0.43 V/10 MHz and 4.55 mW at 1.1 V/1.2 GHz. Plus, it can provide configurable stretch amounts for the AVFS system. Thus, it can provide a within-a-cycle, low overhead frequency adjustment solution for AVFS systems. [ABSTRACT FROM AUTHOR]

To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This article presents two variants of a 32-bit RISC CPU targeted for near-threshold voltage. Both CPUs are placed on the same die and manufactured in 28 nm CMOS process. They employ timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing performance and energy efficiency at a given operating point. Measurements show minimum energy of 3.15 pJ/cyc at 400 mV, which corresponds to 39% energy saving compared to operation based on static signoff timing. [ABSTRACT FROM AUTHOR]