135 results on '"Clerc, Sylvain"'
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2. New insights on diagenetic chlorite and its source material in turbiditic sandstones of contrasted reservoir quality in the Lower Cretaceous Agat formation (Duva oil and gas field, northern Norwegian North Sea)
3. Digital Design Implementation Flow and Verification Methodology
4. Timing-Based Closed Loop Compensation
5. Open Loop Compensation
6. Body-Bias Calibration Based Temperature Sensor
7. Body-Bias for Digital Designs
8. Introduction
9. Diagenesis and reservoir quality evolution of the Lower Cretaceous turbidite sandstones of the Agat Formation (Norwegian North Sea): Impact of clay grain coating and carbonate cement
10. Impact of sediment provenance and depositional setting on chlorite content in Cretaceous turbiditic sandstones, Norway.
11. Low-Power Event-Driven Spectrogram Extractor for Multiple Keyword Spotting: A proof of concept
12. Role of Depositional Environment on Clay Coat Distribution in Deeply Buried Turbidite Sandstones: Insights from the Agat Field, Norwegian North Sea
13. Does porewater or meltwater control tunnel valley genesis? Case studies from the Hirnantian of Morocco
14. Porewater pressure control on subglacial soft sediment remobilization and tunnel valley formation: A case study from the Alnif tunnel valley (Morocco)
15. Subglacial to proglacial depositional environments in an Ordovician glacial tunnel valley, Alnif, Morocco
16. Depositional model in subglacial cavities, Killiney Bay, Ireland. Interactions between sedimentation, deformation and glacial dynamics
17. Charge Collection Physical Modeling for Soft Error Rate Computational Simulation in Digital Circuits
18. New Insights on Diagenetic Chlorite and its Source Material in Turbiditic Sandstones of Contrasted Reservoir Quality in the Early Cretaceous Agat Formation (Duva Oil and Gas Field, Northern Norwegian North Sea)
19. Circuit Monitoring Across Design Life-Cycle in 28nm FD-SOI and 40nm Bulk CMOS technologies
20. Chlorite coating patterns and reservoir quality in deep marine depositional systems – Example from the Cretaceous Agat Formation, Northern North Sea, Norway
21. A commercial 65 nm CMOS technology for space applications: heavy ion, proton and gamma test results and modeling
22. Sedimentological and deformational criteria for discriminating subglaciofluvial deposits from subaqueous ice-contact fan deposits: A Pleistocene example (Ireland)
23. Innovative materials, devices, and CMOS technologies for low-power mobile multimedia
24. A 3.0$_\mu$W@5fps QQVGA self-controlled wake-up imager with on-chip motion detection, auto-exposure and object recognition
25. Guest Editorial Special Section on the 45th IEEE European Solid-State Circuits Conference (ESSCIRC)
26. A 3.0μW@5fps QQVGA Self-Controlled Wake-Up Imager with On-Chip Motion Detection, Auto-Exposure and Object Recognition
27. Comparative evaluation of Body Biasing and Voltage Scaling for Low-Power Design on 28nm UTBB FD-SOI Technology
28. A 225 μm ${}^{2}$ Probe Single-Point Calibration Digital Temperature Sensor Using Body-Bias Adjustment in 28 nm FD-SOI CMOS
29. A 0.40pJ/cycle 981 μm2 voltage scalable digital frequency generator for SoC clocking
30. Design methodology with body bias: From circuit to engineering
31. Detailed SET Measurement and Characterization of a 65 nm Bulk Technology
32. On-chip supply power measurement and waveform reconstruction in a 28nm FD-SOI processor SoC
33. 30% static power improvement on ARM Cortex®-A53 using static biasing-anticipation
34. A 28nm FD-SOI standard cell 0.6–1.2V open-loop frequency multiplier for low power SoC clocking
35. Investigating the single-event-transient sensitivity of 65 nm clock trees with heavy ion irradiation and Monte-Carlo simulation
36. A 0.33V/-40°C Process/Temperature Closed-Loop Compensation SoC Embedding All-Digital Clock Multiplier and DC-DC Converter Exploiting FDSOI 28nm Back-Gate Biasing
37. Subglacial depositional models and tunnel valley infill : example in the Quaternary record (Bray, Ireland) and application to the Upper Ordovicien record in the anti-Atlas (Alnif, Morocco)
38. 28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors
39. 8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing
40. A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking
41. Experimental model of adaptive body biasing for energy efficiency in 28nm UTBB FD-SOI
42. Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI
43. 65 nm fault tolerant latch architecture based on transient propagation blocking
44. A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking
45. Switched-capacitor DC/DC converters in nanometer CMOS technologies for micro-power energy management
46. New D-Flip-Flop Design in 65 nm CMOS for Improved SEU and Low Power Overhead at System Level
47. Experimental Soft Error Rate of Several Flip-Flop Designs Representative of Production Chip in 32 nm CMOS Technology
48. 0.42-to-1.20V read assist circuit for SRAMs in CMOS 65nm
49. Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI
50. Subglacial cavity depositional model in Killiney Bay, Ireland
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