Search

International audience; Due to contextual traffic conditions, the computation of optimized or shortest paths is a very complex problem for both drivers and autonomous vehicles. This paper introduces a reinforcement learning mechanism that is able to efficiently evaluate path durations based on an abstraction of the available traffic information. The authors demonstrate that a cache data structure allows a permanent access to the results whereas a lazy politics taking new data into account is used to increase the viability of those results. As a client of the proposed learning system, the authors consider a contextual path planning application and they show in addition the benefit of integrating a client cache at this level. Our measures highlight the performance of each mechanism, according to different learning and caching strategies.

International audience; Despite the parallelism and sparsity in neural network models, their transfer into hardware unavoidably makes them susceptible to hardware-level faults. Hardware-level faults can occur either during manufacturing, such as physical defects and process-induced variations, or in the field due to environmental factors and aging. The performance under fault scenarios needs to be assessed so as to develop cost-effective fault-tolerance schemes. In this work, we assess the resilience characteristics of a hardware accelerator for Spiking Neural Networks (SNNs) designed in VHDL and implemented on an FPGA. The fault injection experiments pinpoint the parts of the design that need to be protected against faults, as well as the parts that are inherently fault-tolerant.

International audience; In this paper, we consider a symbolic mechanism designed to help guide the performance of actions of a Belief-Desire-Intention (BDI) agent under both concurrency and relevance criteria. Behind the planning activity which can optimistically estimate the relevance of traces, we propose to directly supervise the best effort execution of the intentions as to keep track of the most relevant ones in case of failures. To support the presented method, a typical use case is given that targets the automated guidance of an autonomous vehicle.

International audience; Dans l'objectif de la lutte contre les Chevaux de Troie Matériels, nous proposons d'optimiser une méthode appelé Strong Logic Locking. La mesure de sécurité de cette méthode se base sur les cliques d'un graphe de relation, plus les cliques sont grandes et nombreuses, meilleure sera la sécurité. Nous proposons deux approches pour modéliser et résoudre ce problème.

International audience; We propose an anti-piracy security technique based on locking for analog and mixed-signal circuits designed in FD-SOI. We show that obfuscating the body-bias voltages of tunable transistors is an effective way for inducing high functionality corruption. The obfuscation is achieved by constituting a secret key from the concatenation of the input digital codes of the body-bias generators that produce the correct body-bias voltages. We also propose a slight modification of the bodybias generator that increases prohibitively the time complexity of counterattacks aiming at finding an approximate key. The proposed locking scheme is demonstrated on a Σ∆ modulator used in highly-digitized RF receiver architectures.

International audience; Meteorix is a Universitary CubeSat dedicated to be a demonstrator for the detection and characterisation of meteors and space debris. Its payload is an onboard camera and detection chain. Usually, cameras on CubeSat are used for daylight observations and this proceeding present some tests realized with a sensitive CMOS camera, which is also used in the martian rovers for imaging purposes. In-lab tests were conducted to measure the spectral response. First on-sky images were performed during the 2020 Geminids meteor shower from the Paris area. Follow-up tests were performed from Observatoire de Haute-Provence during the 2021 η-Aquariids meteor shower. Capabilities and needed modifications for meteor detection were identified.

International audience

International audience

Recently, the enormous cost of owning and maintaining a modern semiconductor manufacturing plant has coerced many companies to go fabless. By outsourcing the manufacturing IC/IP to third-party and often off-shore companies, the process has been extended to potentially untrustworthy companies. This has resulted in several security threats to the semiconductor industry such as counterfeiting, reverse engineering, and HTs insertion. In this thesis, we propose an anti-piracy countermeasure to protect AMS ICs/IPs, a novel HT attack for AMS ICs/IPs, and a novel PUF. More specifically, we propose an anti-piracy technique based on locking for programmable analog circuits. The proposed technique leverages the programmability fabric to implement a natural lock-less locking. We discuss its implementation and its resilience capabilities against foreseen attacks. The proposed HT attack for analog circuits leverages the test infrastructure. The HT is hidden effectively in a digital core and transfers its payload to the analog circuit via the test bus and the interface of the analog circuit to the test bus. Its key characteristic is that it is invisible in the analog domain. The proposed HT is demonstrated on two case studies. This thesis sheds light on the importance of developing new security and trust countermeasures tailored for analog circuits. The proposed PUF, called "neuron-PUF", uses a single spiking neuron as the source of entropy. Its key characteristic is that it uses a single PUF cell and temporal redundancy to generate an arbitrarily long key, which results in significant low area and power overheads compared to mainstream PUFs, such as delay-based and memory-based PUFs.; Récemment, les coûts faramineux d'une usine de fabrication de semi-conducteurs ont contraint de nombreuses entreprises à renoncer à avoir leur usine en propre. En externalisant la fabrication de CI/PI à des sociétés tierces, le procédé de fabrication a été confié à des sociétés potentiellement peu fiables. Il en résulte des menaces de sécurité pour l'industrie des semi-conducteurs, telles que la contrefaçon, la rétro-ingénierie et l'insertion de HT. Dans cette thèse, nous proposons une contre-mesure anti-piratage pour protéger les CI/PI AMS, une nouvelle attaque HT pour les CI/PI AMS et une nouvelle PUF. La technique anti-piratage que nous proposons est basée sur le verrouillage des circuits analogiques configurables. Notre technique exploite le mécanisme de configuration du circuit pour y introduire une fonction verrouillage. Nous présentons son implémentation et ses capacités de résilience contre les attaques. L'attaque HT proposée pour les circuits analogiques exploite l'infrastructure de test. Le HT est introduit dans le sous-système numérique du système AMS et transfère sa charge utile au circuit analogique via le bus de test. Le HT est invisible dans le domaine analogique. Le HT est montré sur deux études de cas. Cette thèse montre l'importance de nouvelles contre-mesures de sécurité et de confiance adaptées aux CI analogiques. La fonction PUF proposée utilise un neurone à impulsions comme source d'entropie. Sa caractéristique principale est de n'utiliser qu'une seule cellule PUF et une redondance temporelle pour générer une clé arbitrairement longue, ce qui réduit les coûts additionnels en surface et en énergie par rapport aux fonctions PUF traditionnelles.

International audience; We propose a novel Physical Unclonable Function (PUF) concept based on a single spiking neuron. The inherent variability of the neuron results in a chip-unique analog spiking pattern that is digitized to produce a chip-unique digital key. A stability booster is also employed based on self-masking to obtain a fully stable digital key. The PUF is area and power effective since a single PUF cell is used to produce an arbitrarily sized digital key. We demonstrate PUF quality metrics close to ideal values and argue that the PUF is resilient against various physical attacks.

International audience; Fault diagnosis methodologies for analog circuits lag far behind those for their digital counterparts. In this paper, we show how the generic Symmetry-based Built-In Self-Test (BIST) (or SymBIST), originally proposed for defect-oriented postmanufacturing test and on-line test, can be seamlessly reused for the purpose of diagnosis. BIST can offer better insights into the circuit and, thereby, can assist diagnosis towards resolving ambiguity groups. Using SymBIST we demonstrate high diagnosis resolution and fast diagnosis cycle for an industrial Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC).

International audience; This article presents a universal implementation of a Maximum Power Point Tracking solution for a kinetic energy harvester composed of an electrostatic transducer in association with a capacitive charge pump. The proposed MPPT solution, based on "perturb and observe" method, selects automatically and in real time the optimal electrical state of the charge pump (the voltage of the reservoir capacitor), so to guarantee the maximum of the extracted power under current operation conditions. The proposed solution is implemented alongside a Power Management Integrated Circuit (PMIC) which offers a possibility to control the reservoir's voltage.

International audience; This work proposes a highly tunable motion estimation architecture. We implement the Horn and Schunck algorithm with the hierarchical extension for larger motion estimations in FPGAs. Different architectures are explored dealing with interpolation, pipeline, parallelism and arithmetic format, in order to fit performance. We show in our exploration, how the different cores of our system should be used to increase the throughput. Our smallest design achieves a 30.8 Mpixel/s in a 1024×1024 resolution and the fastest 507 Mpixel/s which is one of the fastest ever achieved, as far as we know, for FPGAs.

International audience; Rapid developments in semiconductor technology have substantially increased the computational capability of computers. As a result of this and recent developments in theory, machine learning (ML) techniques have become attractive in many new applications. This trend has also inspired researchers working on integrated circuit (IC) design and optimization. ML-based design approaches have gained importance to challenge/aid conventional design methods since they can be employed at different design levels, from modeling to test, to learn any nonlinear input-output relationship of any analog and radio frequency (RF) device or circuit; thus, providing fast and accurate responses to the task that they have learned. Furthermore, employment of ML techniques in analog/RF electronic design automation (EDA) tools boosts the performance of such tools. In this paper, we summarize the recent research and present a comprehensive review on ML techniques for analog/RF circuit modeling, design, synthesis, layout, and test.

The ongoing globalization and specialization of the integrated circuit (IC) supply chain has led semiconductor companies to share their valuable intellectual property (IP) assets with numerous parties for means of manufacturing, testing, etc. As a consequence, sensitive IPs and ICs are being exposed to untrusted parties, resulting in serious piracy threats such as counterfeiting or reverse engineering. In this thesis we develop methods to secure analog and mixed signal IPs/ICs from piracy threats within the supply chain.We propose an anti-piracy methodology for locking mixed-signal ICs via logic locking of their digital part. Furthermore, we propose an anti-reverse engineering methodology camouflaging the effective geometry of layout components. Finally, we propose an attack to break all analog circuit locking techniques that act upon the biasing of the circuit.The presented techniques have the potential to protect analog and mixed-signal circuits against a large subset of all the possible risk scenarios while inflicting low overheads in terms of area, power and performance.; La mondialisation et la spécialisation de la chaîne d'approvisionnement des circuits intégrés (CI) ont conduit les entreprises de semi-conducteurs à partager leur précieuse propriété intellectuelle (PI) avec de nombreuses parties pour les faire fabriquer, tester, etc. En conséquence, les PI et les CI sensibles sont exposés à des parties potentiellement malveillantes, ce qui entraîne de graves menaces de piratage telles que la contrefaçon ou la retro ingénierie. Dans cette thèse, nous développons des méthodes pour sécuriser les IP/CI analogiques et mixtes contre les menaces de piratage dans la chaîne d'approvisionnement.Nous proposons une méthodologie anti-piratage pour verrouiller les circuits intégrés mixtes via l'application de logic locking à leur partie numérique. En outre, nous proposons une méthodologie contre la rétro ingénierie camouflant la géométrie effective des composants de layout. Enfin, nous proposons une attaque pour contourner toutes les techniques de verrouillage des circuits analogiques qui agissent sur la polarisation du circuit.Les techniques présentées ont le potentiel de protéger les circuits analogiques et mixtes contre une grande partie de tous les scénarios de risque possibles tout en infligeant de faibles coûts en termes de surface, de puissance et de performance.

International audience; We demonstrate an attack to break all analog circuit locking techniques that act upon the biasing of the circuit. The attack is based on re-synthesizing the biasing circuits and requires only the use of an optimization algorithm. It is generally applicable to any analog circuit class. For the attacker the method requires no in-depth understanding or analysis of the circuit. The attack is demonstrated on a bias-locked Low-Dropout (LDO) regulator. As the underlying optimization algorithm we employ a Genetic Algorithm (GA).

International audience; We propose an anti-piracy security approach for programmable analog and mixed-signal (AMS) Integrated Circuits (ICs). The security approach relies on functionality locking by leveraging the inherent programmability and utilizing the configuration settings as secret keys or, equivalently, the programming bits as key-bits. When invalid keys are applied, the circuit is untuned and, as a result, its functionality breaks, i.e., at least one of the performances violates its specification. As long as the calibration algorithm that produces the configuration settings can be kept secret, the proposed approach can serve as a countermeasure against all types of counterfeiting, i.e., cloning, overbuilding, remarking, and recycling. An important advantage of the proposed approach is that it is lock-less. It leaves the design intact, there is no change to the design flow, and there is no performance penalty and no area or power overheads due to the lock operation. We demonstrate it on a Σ∆ Analogto-Digital Converter (ADC) with 194-bit programmability and complex calibration algorithm used in the context of highlydigitized, multi-standard RF receivers.

International audience; The design and manufacturing steps of a chip typically involve several parties. For example, a chip may comprise several third-party Intellectual Property (IP) cores and the Integrated Circuit (IC) fabrication may be outsourced to a third-party foundry. IP cores and ICs are shared with potentially untrusted third parties and, as a result, are subject to piracy attacks. Even more, any legally purchased chip may be reverse-engineered to retrieve the design down to transistorlevel and, thereby, it is also subject to piracy attacks. In this paper, we propose MixLock, an anti-piracy countermeasure for mixed-signal IP cores and ICs. MixLock protection is based on inserting a lock mechanism into the design such that correct functionality is established only after applying a key which is the designer's secret. The lock mechanism acts on the mixedsignal performances by leveraging logic locking of the digital part. MixLock presents several key attributes. It is generally applicable, it is non-intrusive to the sensitive analog section, it incurs no performance penalty and has very low area and power overheads, it is fully automated, and it is capable of co-optimizing security in both the analog and digital domains. We demonstrate MixLock on a Σ∆ Analog-to-Digital Converter (ADC) using hardware measurements and an audio demonstrator.

The error-resiliency of Artificial Intelligence (AI) hardware accelerators is a major concern, especially when they are deployed in mission-critical and safety-critical applications. In this paper, we propose a neuron fault tolerance strategy for Spiking Neural Networks (SNNs). It is optimized for low area and power overhead by leveraging observations made from a largescale fault injection experiment that pinpoints the critical fault types and locations. We describe the fault modeling approach, the fault injection framework, the results of the fault injection experiment, the fault-tolerance strategy, and the fault-tolerant SNN architecture. The idea is demonstrated on two SNNs that we designed for two SNN-oriented datasets, namely the N-MNIST and IBM’s DVS128 gesture datasets. Junta de Andalucía-US-1260118 Universidad de Sevilla-VI PPIT

International audience; We propose a Hardware Trojan (HT) attack for analog circuits with its key characteristic being that it cannot be prevented or detected in the analog domain. The HT attack works in the context of Systems-on-Chip (SoCs) comprising both digital and analog Intellectual Property (IP) blocks. The attacker could be either the SoC integrator or the foundry. More specifically, the HT trigger is placed inside a dense digital IP block where it can be effectively hidden, whereas the HT payload is in the form of a digital pattern transported via the test bus or generated within the test bus, reaching the Design-for-Test (DfT) or programmability interface of the victim analog IP with the test bus. The HT payload unexpectedly activates the DfT and sets the victim analog IP into some possibly partial and undocumented test mode or changes the nominal programmability. The HT payload can be designed to result in performance degradation or complete malfunction, i.e., denial of service. We demonstrate this HT attack scenario on two analog IPs, namely a low-dropout (LDO) regulator using simulation and an RF receiver using hardware measurements.

International audience; We propose a Built-In Self-Test (BIST) paradigm for analog and mixed-signal (A/M-S) Integrated Circuits (ICs), called symmetry-based BIST (SymBIST). SymBIST exploits inherent symmetries in an A/M-S IC to construct signals that are invariant by default, and subsequently checks those signals against a tolerance window. Violation of invariant properties points to the occurrence of a defect or abnormal operation. SymBIST is designed to serve as a functional safety mechanism. It is reusable ranging from post-manufacturing test, where it targets defect detection, to on-line test in the field of operation, where it targets low-latency detection of transient failures and degradation due to aging. We demonstrate SymBIST on a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). SymBIST features high defect coverage, short test time, low overhead, zero performance penalty, and has a fully digital interface making it compatible with modern digital test access mechanisms. Index Terms-Analog and mixed-signal integrated circuit testing, built-in self-test, design-for-test, defect-oriented test, defect simulation, on-line test, concurrent error detection.

International audience

International audience; This focus paper proposed for the track "Energy Harvesting and Power Efficient Electronics" addresses the new generation of conditioning circuits based on active energy extraction techniques, designed by the term "synchronous conditioning circuits". Initially proposed for enhancing energy yield of piezoelectric transducers having intrinsic poor quality, these techniques are now a part of the established method not only for piezoelectric devices, but also for triboelectric transducers. Their recent success is due to intensive use of integrated CMOS technologies optimized for low-energy power converters, which allowed to build highly efficient systems even in the case when the input energy is of few microwatts. This paper shortly reviews the synchronous energy extraction technique and their applications, and then discusses recent successful implementations in CMOS technologies.

International audience; In this paper we present an autonomous Power Management Integrated Circuit PMIC for an electret-biased electrostatic kinetic energy harvester with a Bennet's doubler conditioning circuit. The circuit is designed in high voltage 0.35μm standard bulk CMOS technology. It supplies a low voltage load from the energy extracted from a high voltage transducer. The circuit is provided with a “cold start” mechanism and with a “safe mode” (Recovery) feature that permits to the system to stay active (awake) for a longer time after external vibrations stop temporarily. An ultra-low static power hysteresis comparator is designed for a specific control of the capacitive transducer's conditioning circuit. The autonomy of the system is ensured by a voltage regulator that supplies the internal blocks of the circuit with 1.1 V. The measured maximum end-to-end efficiency of the implemented system is 75% when the available input power was of 80 μW.

The increasing need for validating heterogeneous Systems on Chip (SoC) before their costly fabrication gives rise to the development of numerous virtual prototyping tools, allowing not only the modeling of such systems, but also the simulation of the environment in which they will be embedded, including the crucial software. SoC designers indeed require flexible simulation frameworks that follow a component-based approach and that cover a wide field of physical/engineering disciplines… and no questions asked about the simulation intrinsics. Furthermore, for SMEs, laboratories, and enthusiastic makers with limited funding, the cost of these frameworks makes them unaffordable, especially when the target system hardware is supposed to be Open Source too. In this paper, we detail the principles of an Open Source SystemC Multi-Disciplinary Virtual Prototyping (SystemC MDVP) framework, which directly tackles with all these issues. We introduce the key concepts and methodology (relationships between Models of Computation and overall synchronization techniques) and insist on the importance of a “correct by construction” global model elaboration that allows to generate the hierarchy of solvers that make up the final simulator. We then show that a new Model of Computation, Electrical Network, has been added to SystemC MDVP to handle components with non-linear beahviors. The paper concludes with a quick presentation of the echOpen project which aims at designing a low-cost portable echography device modeled and simulated with the nresented nrincinles.

International audience; The immunity of jitter with respect to supply voltage is one of the desirable characteristics of digitally controlled oscillators (DCO) for clocking applications. This paper presents a design of such an oscillator with a high frequency resolution and small area in 28 nm technology. In order to reduce the dependence of the oscillator frequency on its voltage supply, differential amplifiers are used as inverters (delay cells) and a bias circuit with a stable voltage output is employed to bias the oscillator. From post-layout simulations, this DCO achieves a dynamic range from 1.13 to 1.54 GHz with the use of differential delay cells, the variation of the output frequency is less than 4.5% over all the frequency range, for VDD variation of 10%. The frequency control has 9.2 bits, giving an average frequency step of 722 kHz. This DCO achieves a phase noise of-74 dBc/Hz@1MHz or an jitter equivalence of 2.3 ps. The maximal power consumption of this DCO at maximum frequency is 840 µW, which is a low figure comparing to the state-of-the-art implementation with typical power of sub-milliwatts for the similar frequency range. Index Terms-All-Digital Phase Locked Loop (ADPLL), Digitally controlled oscillator (DCO), differential inverter ring

In this brief, we present a tunable bandpass RF Sigma-Delta modulator with a fixed set of feedback DAC coefficients. The sampling frequency, $f_{s}$ , is tuned with the center frequency, $f_{0}$ , in order to maintain a fixed normalized center frequency, $f_{0}/f_{s}$ . Any variation in the loop delay is compensated to maintain a fixed normalized loop-delay $t_{d}/T_{s}$ . The bandpass Sigma-Delta, reported in this brief, is based on an LC resonator with tunable center frequency from 1.5 to 3.0 GHz and a corresponding sampling frequency from 6.0 to 12.0 GHz. For an oversampling ratio of 64, the ADC achieves the same SNDR of 37 dB and the same Dynamic Range of 45 dB over the complete tuning range. This performance is achieved for a bandwith of 47 MHz at 1.5GHz and a Bandwidth of 93 MHz at 3 GHz. The ADC, fabricated in a 65 nm CMOS process, consumes only 13 mW from a 1.2 V supply. In order to compare this circuit with the state of the art, we use not only the conventional ADC Figure of Merit but we also use a Figure of Merit dedicated to RF circuits. In this case, the measured chip center frequency, noise figure and non-linearity are also taken into account in the comparison.

International audience; The deployment of Artificial Intelligence (AI) hardware accelerators in a variety of applications, including safety-critical ones, requires assessing their inherent reliability to hardware-level faults and developing cost-effective fault tolerance techniques. This entails performing large-scale fault simulation experiments. However, transistor-level fault simulation is prohibitive and fault simulation should be carried out at a higher abstraction level. In this work, we focus on spiking neural networks (SNNs), and we follow a bottom-up approach starting from transistor-level simulations for developing a neuron behavioral-level fault model that can be readily employed for performing behavioral-level fault simulation of deep SNNs.

Triboelectric nanogenerators have attracted wide attention due to their promising capabilities of scavenging the ambient environmental mechanical energy. However, efficient energy management of the generated high-voltage for practical low-voltage applications is still under investigation. Autonomous switches are key elements for improving the harvested energy per mechanical cycle, but they are complicated to implement at such voltages higher than several hundreds of volts. This paper proposes a self-sustained and automatic hysteresis plasma switch made from silicon micromachining, and implemented in a two-stage efficient conditioning circuit for powering low-voltage devices using triboelectric nanogenerators. The hysteresis of this microelectromechanical switch is controllable by topological design and the actuation of the switch combines the principles of micro-discharge and electrostatic pulling, without the need of any power-consuming control electronic circuits. The experimental results indicate that the energy harvesting efficiency is improved by two orders of magnitude compared to the conventional full-wave rectifying circuit., Conditioning efficiently high-voltage triboelectric nanogenerators for low-voltage applications remains a challenge. Here, the authors demonstrate two orders of magnitude improvement of the energy harvesting efficiency by applying a conditioning circuit with self-sustained and automatic hysteresis MEMS micro-plasma switches.

International audience; We present a Hardware Trojan (HT) attack scenario for analog circuits. The characteristic of this HT is that it does not reside inside the victim analog circuit. Instead, it resides on an independent digital circuit on the same die where it is triggered, yet its payload is applied only to the analog circuit after being transferred via the common test infrastructure and the test interface of the analog circuit. This HT attack cannot be detected or prevented in the analog domain and it exploits the dense digital circuit to hide effectively its footprint.

International audience; This paper proposes an in-depth analysis of the tri-state inverter based digitally controlled oscillator. This oscillator topology has been reported in numerous publication, however its features remain poorly understood. In this study, we propose to focus on these lacks. We specifically addressed the oscillation period and the associated jitter as these quantities are the design key parameters. In this paper, we propose analytical expressions taking into consideration the design, the technology as well as the input code. These equations are suitable for hand calculations and have helped to establish a design methodology for rapid implementation. Two circuits have been designed in STMicroelectronics CMOS 65nm process. The first one was evaluated through simulations. Then, the measurement results obtained with the second circuit manufactured within the same technology node are presented. Finally, the experimental data support the proposed theory.

The long-term monitoring of cardiovascular signs requires a wearable and connected electrocardiogram (ECG) healthcare device. It increases user’s comfort and diagnosis quality of chronic cardiac and/or high-risk patients. This paper covers the enormous data to be transmitted from the ECG device to the physician’s, namely the cardiologist’s, control unit. Existent ECG devices uniformly sample analog signals and convert them to digital samples which are compressed before data transmission. However, event-driven sampling simultaneously compresses and samples. Therefore, this paper quantitatively compares successive approximation register analog-to-digital converter (SAR ADC) with discrete wavelet transform (DWT) compression and level-crossing analog-to-digital converter (LC-ADC). Evaluation metrics are the percent root-mean-square difference (\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$ {\text{PRD}} $$\end{document}PRD), bit compression ratio (\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$ {\text{BCR}} $$\end{document}BCR) and data length in bits. When a 12-bit reconstruction is operated on the outputs of an 8-bit LC-ADC with 12-bit and 10-kHz reference counter, the \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$ {\text{BCR}} $$\end{document}BCR is equal to 80% for 75% of test ECG signals. That is better than the 71.87% \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$ {\text{BCR}} $$\end{document}BCR of the 12-bit 1-kHz SAR ADC with DWT compression. The modeled LC-ADC guarantees a signal quality in terms of \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$ {\text{PRD}} $$\end{document}PRD comparable to the \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$ {\text{PRD}} $$\end{document}PRD of the SAR ADC with DWT compression. The data length in bits of the LC-ADC is lower than the data length in bits of the SAR ADC with more than 14-bit resolution with DWT compression for 82% of the test ECG signals. However, for lower resolutions, to obtain lower power consumption for radiofrequency transmission, a better alternative remains the SAR ADC with DWT compression.

International audience; In this paper, we propose a defect-oriented Built-In Self-Test (BIST) paradigm for analog and mixed-signal (A/M-S) Integrated Circuits (ICs), called symmetry-based BIST (Sym-BIST). SymBIST exploits inherent symmetries into the design to generate invariances that should hold true only in defect-free operation. Violation of any of these invariances points to defect detection. We demonstrate SymBIST on a 65nm 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) IP by ST Microelectronics.

International audience; Virtual prototyping and co-simulation of mixed analog/digital embedded systems have emerged as a promising research topic, but usually assume an already Hardware/Software partitioned system. The paper presents a new approach for high-level system partitioning of such mixed systems, by expressing the structure and the behaivour of the analog parts with SysML diagrams. A tool already able to handle some aspects of analog design after partitioning has been extended to be able to handle partitioning, thus completing the methodology. As a real-world case study, we show the design of the hardware part of a medical application.

This article presents a methodology for sizing transistors of a multistage, multipath capacitor-less feed-forward compensated operational amplifiers employed in advanced CMOS process implementation of continuous-time bandpass $\Sigma \Delta $ -modulators. This article describes the methodology: on system level, dealing with the placement of poles and zeros; and on the circuit level, discussing issues related to biasing, frequency response and other important performance metrics of the basic diff-pair. Algorithms are provided to simplify mathematical aspects of the work. The validity and the limitations of the proposed methodology are further discussed from the single-pole system used to model the individual amplification stages of the multistage amplifier. The worthiness of the proposed methodology in sizing the transistors of complex amplifier structures, such as the capacitor-less multistage, multipath feed-forward-compensated amplifiers is demonstrated using two design examples. A third-order amplifier with a dc gain of 52.6 dB and that reaches a unity-gain frequency of above 14 GHz while consuming only 5.6 mA from a 1-V supply; and a fourth-order amplifier with dc gain of 73.5 dB that achieves a 25.7-dB gain at 1 GHz while consuming 4.8 mW are designed in 28-nm CMOS FDSOI.

International audience; Due to traffic conditions that are very context dependent, the computation of optimized or shortest paths is a very complex problem for both drivers and autonomous vehicles. In this paper, we introduce a learning mechanism that is able to efficiently evaluate path durations based on an abstraction of the available traffic information. We demonstrate that a cache data structure allows a permanent access to the results whereas a lazy politics taking new data into account is used to increase the viability of those results. Our measures highlight the performance of each mechanism, according to different learning strategies.

International audience

International audience; The Embedded Higher-order Agent (E-HoA) architecture presented in this paper addresses the growing need for context-aware ambient systems, such as autonomous vehicles. This multi-process architecture, to be embedded into the control loop of these vehicles, includes a Belief-Desire-Intention agent that can consistently assist the symbolic execution of intentions. It also performs the appropriate conversion of these intentions into real physical vehicle maneuvers based on ROS. The proposed architecture offers gradually 4 levels of reactivity, from arch-reflex to the deep modification of the previously built symbolic execution plan. The presented use-case, the daily delivery of a network of pharmacy offices by an autonomous vehicle taking into account contextual (spatio-temporal) traffic features, shows the efficiency and the modularity of the architecture, as well as the scalability of the reaction levels.

International audience; We treat the problem of analog Integrated Circuit (IC) obfuscation towards Intellectual Property (IP) protection against reverse engineering. Obfuscation is achieved by camouflaging the effective geometry of layout components via the use of fake contacts, which originally were proposed for gate camouflaging in digital ICs. We present a library of obfuscated layout components, we give recommendations for effective camouflaging, we discuss foreseen attacks and the achieved resiliency, and we propose security metrics for assessing the hardness of reverse engineering. The proposed methodology is demonstrated on an operational amplifier and an RF Σ∆ Analog-to-Digital Converter (ADC). Index Terms-Hardware security and trust, analog and mixed-signal integrated circuits, IP/IC piracy, reverse engineering, design obfuscation, camouflaging.

Embedded systems are commonly built upon heterogeneous digital and analog integrated circuits, including sensors and actuators. Model-driven approaches for designing software and hardware are generally limited to the digital parts of systems. In the present paper, we adopt a global view on the extensions made to an integrated modeling and simulation tool, TTool. In this tool, the verification and virtual prototyping of embedded systems is described at different abstraction levels and extended in order to handle analog/mixed-signal systems. An extensive case study spans these levels and illustrates the usefulness of our approach.

International audience; This article argues that labor activists initiated Silicon Valley's anti-toxics movement and were the driving force behind environmental remediation in the region in the first half of the 1980s. In order to unionize semiconductor plants, activists associated with SCCOSH and United Electrical, Radio, and Machine Workers, a left-wing union, attacked corporate negligence regarding worker safety and health. SCCOSH later allied itself with the Central Labor Council of Santa Clara County to push for the cleanup of aquifers contaminated by the semiconductor industry. The activists ultimately failed to organize Silicon Valley, but their campaigns led to a revolution in safety among microelectronics firms and to large-scale remediation efforts conducted under the EPA's Superfund program.

This paper presents a methodology to analyze the substrate noise coupling and reduce their effects in smart power integrated circuits. This methodology considers the propagation of minority carriers in the substrate. Hence, it models the lateral bipolar junction transistors that are layout dependent and are not modeled in conventional substrate extraction tools. It allows the designer to simulate substrate currents and check their effects on circuits functionality. The proposed methodology employs a dedicated tool for substrate network generation referred to as AUTOMICS. We applied the methodology on two test cases. The first case is a dc–dc buck converter chip fabricated with a 0.35 $\mu\text{m}$ high-voltage-CMOS technology. The dc coupling current between the switches and the bandgap circuit is simulated and verified with measurements. The second test case is an automotive industrial chip that has a latch-up failure due to substrate coupling. In transient simulations, the failure has been reproduced as in measurements. This highlights the stronghold of the methodology since it can be used to prevent this type of failures before fabrication. The proposed methodology can reduce the number of redesigns in the automotive industry. Hence, it shortens the time-to-market, improves the robustness of the design, and reduces the cost.

International audience; In this paper we present an autonomous Power Management Integrated Circuit PMIC for an electret-biased electrostatic kinetic energy harvester with a Bennet's doubler conditioning circuit. The circuit is designed in high voltage 0.35 μm standard bulk CMOS technology. It supplies a low voltage load from the energy extracted from a high voltage transducer. The circuit is provided with a "cold start" mechanism and with a "safe mode" (Recovery) feature that permits to the system to stay active (awake) for a longer time after external vibrations stop temporarily. An ultra-low static power hysteresis comparator is designed for a specific control of the capacitive transducer's conditioning circuit. The autonomy of the system is ensured by a voltage regulator that supplies the internal blocks of the circuit with 1.1 V. The proposed design consumes less than 400 nW making it adequate for use with existing state-of-the art capacitive harvesting MEMS devices.

This brief presents an active distributed clock generator for manycore systems-on-chip consisting of a $10\times 10$ network of coupled all-digital phase-locked loops, achieving less than 38 ps phase error between neighboring oscillators over a frequency range of 700–840 MHz at $V_{\text {DD}} = 1.1$ V. The network is highly robust against $V_{\text {DD}}$ variations. An energy cost of 2.7 $\mu \text{W}$ /MHz per node is 7 times lower than that in analog implementations of similar architectures and is twice lower than that in conventional H-tree architectures. This is the largest on-chip all-digital phase-locked loop network ever implemented. With clock generation nodes linked only locally, this solution is proven to be scalable. The presented clock generation network does not require any external reference, except for the start-up frequency selection, generating a synchronized signal in fully autonomous mode and maintaining frequency stability within 0.09% during 1700 seconds. Such a network of frequency and phase synchronized oscillators can be used as a source for local clocking areas.

International audience; This tutorial aims to build a RISC-V processor using only free VLSI CAD tools with a symbolic technology approach (a refined Mead-Conway method as formerly used by MOSIS). The toolchain is currently organized as follow: A design description in VHDL language. Simulation with GHDL. Logical synthesis with Yosys. We use a frontend to convert VHDL into Verilog (from Alliance). Physical design (place & route) using Coriolis. DRC & LVS using Alliance. Timing analysis with Tas & Yagle. Symbolic to real translation (Alliance).Our first objective is to design a RISC-V for AMS 350nm node.The choice of symbolic technology is mainly made for three reasons: Node portability: From one symbolic layout, you may target multiple technologies. Community: Symbolic layout does not contain any NDA related information. As such it can freely be published and shared. Security.:With a published layout, everybody can check that the chip send back from the foundry is exactly what it should be (no hardware trojan).

International audience; In this paper, we demonstrate a recently proposed security technique for mixed-signal circuits in the context of a real application. The security technique, called MixLock, is based on logic locking of the digital section of the mixed-signal circuit and can be used as a countermeasure for reverse engineering and counterfeiting. We demonstrate MixLock in an audio application, where the underlying Σ∆ ADC that digitizes the audio input is locked. We show the effect that locking has on the recorded audio quality based on a metric that counts the resultant glitches per second and by also providing a link where the interested reader can download and listen to output audio samples for locked and unlocked versions of the Σ∆ ADC.

International audience; This work presents a 4 th-order multi-stage, multi-path, feed-forward-compensated operational amplifier in 65 nm CMOS technology. It is designed to meet the requirements of a continuous-time bandpass Σ∆ modulator with multi-GHz sampling frequency. The designed amplifier is modular with each stage implemented based on a unit differential amplifier block and it meets its targets with smart placement of poles and zeros. The amplifier is simulated under the loading condition of a single-amplifier resonator which is in turn part of a 6 th-order Σ∆ modulator. The unloaded amplifier reaches a unity-gain-frequency of 38.29 GHz and a DC gain of 58 dB. With a parallel load of 440 fF and 300 Ω, representing the maximum load, the op-amp, including common-mode and biasing circuits, consumes a total of 18.98 mA from a supply voltage of 1.2 V. It is unconditionally stable with a phase margin of 54 • and has gains of 35 dB and 23 dB at 1 GHz and 2 GHz respectively.

International audience; Unlike the digital domain where the use of standard cell libraries considerably reduces the design time, in the analog domain, it is practically impossible to store in the same library all the functions that can cover the entire possible range of data, with all application associated electrical specifications. On the other hand, given the fact that such a library would be very quickly obsolete due to the fast evolution of technologies, it is obvious that without the help of appropriate CAD tools to design parameterized modules, the analog may become a serious bottleneck in terms of design time and cost of a System on Chip.

International audience; We present a universitary CubeSat space mission called Meteorix dedicated to the detection and characterization of meteors and space debris. The primary objective is to assess a robust statistics on meteoroids and space debris that enter the Earth atmosphere. At present, their fluxes and properties are not yet determined accurately. These estimates will allow to quantify the delivery of extraterrestrial material on Earth, and possible consequences on aeronomy (e.g. noctilucent clouds and atomic layer). These estimations are also crucial to estimate impact risks for artificial satellites during meteor showers. The knowledge of the flux of space debris will allow to bring some constraints to the space agency models of space surveillance. There are several secondary objectives such as to bring information on ablation, fragmentation, rotation processes by studying photometric variations; to determine the trajectory in connection with Earth-ground network such as FRIPON network developed in France in order to find the dynamical origin of the meteoroid; and also the detection of other fainter luminous atmospheric such as luminous transient events. The technological objective is dedicated to the real-time autonomous detection of meteors on board of a CubeSat. This CubeSat is a 3U developed by students at Sorbonne University. The project has validated the feasibility phase.

International audience; Hardware-implemented neural networks are foreseen to play an increasing role in numerous applications. In this paper, we address the problem of post-manufacturing test and self-test of hardware-implemented neural networks. In particular, we propose a self-testable version of a spiking neuron circuit. The self-test wrapper is a compact circuit composed of a low-precision ramp generator and a small digital block. The self-test principle is demonstrated on a spiking neuron circuit design in 0.35µm CMOS technology.